Bond Pad Research Articles

Comprehensive Comparative Analysis of Microstructure of Sn-Ag-Cu (SAC) Solder Joints by Traditional Reflow and Thermo-Compression Bonding (TCB) Processes

Thermal-compression bonding (TCB) process has been considered to successfully fabricate the 3D stacked interconnection with ultra-fine pitch I/O bumped thin flip-chip and achieve package miniaturization, such as high bandwidth memory (HBM) modules that exceed capabilities of traditional thermal reflow process. Until now, a conventional reflow process has been the de facto solder interconnection method in microelectronic packaging. The alternative, TCB process has not been employed commonly for solder interconnection method as TCB-bonded solder joints have yet failed to prove their reliabil-ity such as upon thermal cycling and electro-migration (EM). A significant difference in solder reflow (i.e. melting and solidi-fication) technique may affect solder grain and crystallographic characteristics, thus affecting the reliability performance of 3D package modules. In addition, there has not been any fundamental and comparative study between the conventional reflow bonding and TCB processes. Also, the degradation mechanism of TCB-processed flip-chip packages upon EM failure has not been clearly defined. Here we show that the Cu6Sn5 intermetallic compound (IMC) morphology at Sn-Ag-Cu (96.5 wt./3.0 wt./0.5 wt.% SAC-305) solder joint interfaces and the texture of β-Sn crystallographic orientation of SAC-305 solder joint upon TCB-utilized flip-chip fabrication drives premature EM failure. We found that the lack of the IMC layer of TCB-processed solder joints facilitates the diffusion of Cu and Ni atoms at the solder-Cu bond pad interfaces, and furthermore the thermomigration (TM) caused by Joule heating at the TCB interface could provide synergistic impact on the EM. In ad-dition, through statistical studies using EBSD results, higher lattice coherency of β-Sn crystallographic texture was observed for TCB-processed solder joint that adds to a much faster diffusion of Cu and Ni atoms during the EM test, which is respon-sible for leaving defects both within the solder and at the interfaces of the joint. Our results demonstrate an insightful deriv-ing force of EM from the solder joint the microstructure and the crystal orientation that allows for juxtaposition of two most widely used bonding technologies, reflow bonding and TCB.

Novel Electronic Packaging Method for Functional Electronic Textiles

A novel packaging method that enables the reliable mounting and protection of bare die within a textile yarn has been investigated. The reliability of electronic textiles is highly challenging given the flexibility of the fabric and the rigors of typical applications. Achieving reliable operation requires novel packaging approaches. In order to maximize the reliability and to minimize stresses in the electronic package, the die should be located as close as possible to the central axis of the overall assembly. The die is bonded to a bottom Kapton substrate that contains patterned conductive interconnects and bond pads forming the functional circuit. The circuit is protected by a molded Kapton film that has recesses formed where the die is located. This approach has been compared with three other traditional packaging technologies during washing, twisting, and cyclical bending tests. The novel electronic packaging method shows the best performance in all tests surviving up to 45 wash cycles.

Maximal Q Factor for an On-Chip, Fuse-Based Trimmable Capacitor

This paper presents a circuit for realising a fuse-programmable capacitor on-chip. The trimming mechanism is implemented using integrated circuit fuses which can be blown in order to lower the resulting equivalent capacitance. However, for integrated circuits, the non-zero fuse resistance for active fuses and finite fuse resistance for blown fuses limit the Q factor of the resulting capacitor. In this work, we present a method on how to arrange the fuses in order to achieve maximal worst-case Q factor for the given circuit topology given the process parameters and requirements on capacitance. We also analyse and discuss the accuracy and limitations of the topology with regard to fuse resistance and parasitic elements such as bond pads.

Photosensitive Glass-Ceramics for Heterogeneous Integration

The push for heterogeneous integration requires very unique material properties with respect to processing, material constants, and integration capabilities with other materials (such as copper, II...

A 2.2 to 2.9 GHz Complementary Class-C VCO With PMOS Tail-Current Source Feedback Achieving – 120 dBc/Hz Phase Noise at 1 MHz Offset

The performance of low-powered transceivers is required to meet stringent specifications for an advanced wireless radio application. It is critical for a voltage-controlled oscillator (VCO) to meet multi-standard and multiple frequency operation with low-power consumption and amplitude enhanced complementary mode of operation. This paper proposes a novel technique for wide tuning range in a complementary class-C VCO employing a capacitive-source degeneration (CSD) to meet multi-standard operation for low-power transceivers. The technique that employs two sets of symmetrical split PMOS biased current source operating in the subthreshold region achieves the desired low phase noise (PN) performance at a tuning range of 2.2-2.9 GHz with a supply headroom of 1.2 V. The control of the dc bias point reduces the conduction angle, which improves the current efficiency, power consumption, and PN. Concurrently, an auxiliary -g m NMOS only class-B oscillator is incorporated to mitigate the start-up issue of the class-C VCO. At the center frequency of 2.45 GHz, the proposed VCO achieves a power consumption of 1.73 mW, phase noise of -120 dBc/Hz at the 1-MHz offset, and a figure-of-merit (FoM) of 185.41 dBc/Hz at 1 MHz. The total active chip area is only 0.3-mm 2 excluding bond pads. The proposed VCO serves as a promising solution for low-power wireless communication systems.

Hybrid Approach to Conduct Failure Prognostics of Automotive Electronic Control Unit Using Stress Sensor as <italic>In Situ</italic> Load Counter

A model/sensor hybrid approach is implemented to conduct failure prognostics of an automotive electronic control unit (ECU). A 3-D finite-element model simulating a complex ECU is built, and its predictability is calibrated and verified by an optical displacement measurement technique called moire interferometry. On the sensor front, a silicon-based piezoresistive stress sensor is embedded into the ECU to provide in situ stress measurements during operations. A stress metric is defined using the stress values of 12 cells in each sensor, and it is converted to in situ loading histories using the calibrated finite-element model. The modeling and verification steps that lead to the predictive finite-element model are described. The proposed hybrid approach is implemented using the data obtained from a molded ECU subjected to thermal cycling conditions, and the forces at an interface between an aluminum wire bond and metal pad are investigated.

Design of Solder Connections for Self-Assembly of Optoelectronic Devices

Abstract In surface mount assembly, advantage is taken of the high surface tension of molten solder to self-align ball grid array packages and flip chip die. However, in these applications, the volume of solder applied as paste by stencil printing is not sufficiently well controlled to achieve the precise alignment required for optoelectronic devices. We believe that the requirement on solder volume control for assembly of optoelectronic devices can be relaxed by designing the bond pads so that the height or alignment of connections is controlled by the surface tension of the solder rather than its volume. Our design approach to accomplishing this is to connect auxiliary pads to the primary attachment pad, which act as solder reservoirs. Surface tension causes the solder to be redistributed among these pads to achieve a uniform pressure throughout the solder volume. This phenomena is governed by the Young-Laplace equation, ΔP = γκ, in which ΔP represents the difference in pressure within and outside the solder, γ the surface tension of the solder, and κ the local curvature of the solder surface. Thus, the design of the set of primary and auxiliary pads is critically important to realizing the desired control of joint height. In this article, we describe the use of the Surface Evolver software package in combination with analytical models, to analyze the behavior of various connection configurations with respect to variations in printed solder volume. Specifically, we calculate the equilibrium shape of the solder surface over the connected set of pads and examine how control of joint height is affected by the number, size, and geometry of auxiliary pad configurations.

Problemi korozije u elektronskim sistemima

Microelectronics and, chiefly, silicon integrated circuit microelectronics, has created astonishing capabilities over the last 40 years. Speedy advancement in CMOS transistor equipment leading to the gigahertz speeds common today has necessitated chief changes in semiconductor manufacturing technology and the expansion of high frequency compatible packaging. The progress of an optimized formulation for electroless nickel (EN) plating with a long life span to make a deposit with good corrosion resistance (CR). The electroless deposition of Ni-P alloys is widely used in diverse fields such as aerospace, automation, electronics, nuclear, oil and gas production, and valve industries. Lead frame is the primary package metallurgical bond pad interface in microelectronic devices which provides external interconnection. The most predominant lead frame material is copper with tin plating. Over the years, galvanic corrosion and copper oxidation are two major reliability concerns for any microelectronics packages with copper lead frame, when operating under high humidity environment.

Bond strength evaluation of heat treated Cu-Al wire bonding

Bond strength evaluation of wire bonding in microchips is the key study in any wire bonding mechanism. The quality of the wire bond interconnection relates very closely to the reliability of the microchip during performance of its function in any application. In many reports, concerns regarding the reliability of the microchip are raised due to formation of void at the wire-bond pad bonding interface, predominantly after high temperature storage (HTS) annealing conditions. In this report, the quality of wire bonds prepared at different conditions, specifically annealed at different HTS durations are determined by measurements of the strength of the interface between the bond wire and the bond pad. The samples are tested in pull test and bond shear test. It was observed that the higher bonding temperature as well as the longer duration of HTS increased the bond strength. This is represented through the analysis of the measurements of ball shear strength. This is due to the fact that higher bonding temperature and longer HTS promoted better growth of the Cu-Al IMC layer. A transmission electron microscopy - energy dispersive X-ray analysis (TEM-EDX) has been carried out to observe the formation of the Cu-Al IMC layer in the sample.

Electrically packaged silicon-organic hybrid (SOH) I/Q-modulator for 64 GBd operation.

Silicon-organic hybrid (SOH) electro-optic (EO) modulators combine small footprint with low operating voltage and hence low power dissipation, thus lending themselves to on-chip integration of large-scale device arrays. Here we demonstrate an electrical packaging concept that enables high-density radio-frequency (RF) interfaces between on-chip SOH devices and external circuits. The concept combines high-resolution Al2O3 printed-circuit boards with technically simple metal wire bonds and is amenable to packaging of device arrays with small on-chip bond pad pitches. In a set of experiments, we characterize the performance of the underlying RF building blocks and we demonstrate the viability of the overall concept by generation of high-speed optical communication signals. Achieving line rates (symbols rates) of 128 Gbit/s (64 GBd) using quadrature-phase-shift-keying (QPSK) modulation and of 160 Gbit/s (40 GBd) using 16-state quadrature-amplitude-modulation (16QAM), we believe that our demonstration represents an important step in bringing SOH modulators from proof-of-concept experiments to deployment in commercial environments.

Vision-Based Robotic Manipulation of Flexible PCBs

Recently, increasing demands on automatic soldering of flexible printed circuit boards (PCBs) have been reflected in the fast expanding computer, communication, and consumer electronics manufacturing. However, the deformation of flexible PCBs results in the changing shape and hence the varying position of solder pads on flexible PCBs under applied forces, which opens up challenges for robotic soldering of flexible PCBs. This paper presents a vision-based control scheme for robotic soldering of flexible PCBs. The proposed controller enables the robot to automatically contact, then actively deform the flexible PCB into a desired configuration, such that the well-deformed PCB can be soldered in an automatic soldering machine. Both operations of contacting and active deformation are smoothly integrated into a single continuous controller and automatically transited by assessing the physical contact online. Neural-network techniques are employed to approximate the unknown deformation model and the uncalibrated camera model. The dynamic stability of the closed-loop system is rigorously proved with Lyapunov methods, and experimental results are presented to illustrate the performance of the proposed controller.

Design of Solder Connections for Self-Assembly of Optoelectronic Devices

Abstract The cost of optoelectronic assemblies is significantly higher than that of electronic assemblies due in large part to the method of assembly. A typical computer circuit board is built by screen printing solder paste onto a printed wiring board, placing components on the board at rates of several thousand per hour, and then reflowing the solder paste in a conveyor oven. By contrast, optoelectronic assemblies are built up in a sequential process in which epoxy is dispensed for a single component, which is placed and held in position until the epoxy is cured. Many minutes are required to build an optoelectronic assembly, such as a laser module, by this approach, also the precision robotic placement tool needed for this process costs in excess of a million dollars. The demand for all types of optoelectronic components in communications, computing, automotive, medical and aerospace applications is great, but the high cost of manufacture is constraining growth, so clearly a better method of assembly is needed. In surface mount assembly, advantage is taken of the high surface tension of molten solder to self-align ball grid array packages and flip chip die. However, in these applications, the volume of solder applied as paste by stencil printing is not sufficiently well controlled to achieve the precise alignment required for optoelectronic devices. We believe that the requirement on solder volume control for assembly of optoelectronic devices can be relaxed by designing the bond pads so that the height or alignment of connections is controlled by surface tension of the solder rather than its volume. Our design approach to accomplishing this is to connect auxiliary pads to the primary attachment pad, which act as solder reservoirs. Surface tension causes solder to be redistributed among these pads to achieve a uniform pressure throughout the solder volume. This phenomena is governed by the Young-Laplace equation, ΔP = γκ, in which ΔP represents the difference in pressure within and outside the solder, γ the surface tension of the solder and κ the local curvature of the solder surface. Thus, the design of the set of primary and auxiliary pads is critically important to realizing the desired control of joint height. In this paper we describe the use of the Surface Evolver software package in combination with analytical models, to analyze the behavior of various connection configurations with respect to variations in printed solder volume. Specifically, we calculate the equilibrium shape of the solder surface over the connected set of pads and examine how control of joint height is affected by the number, size and geometry of auxiliary pad configurations. We also discuss results from some preliminary experiments that we are conducting to validate our modeling results.

Explore High Bonding Reliability of Cu Wire Bonded Devices under Extreme Halide Contaminated Environments

Abstract Copper has rapidly replaced gold as the preferred wire bonding material in microelectronic packaging due to its lower cost and many performance advantages. However, halides induced corrosion-related failures need to be carefully controlled to ensure maximum bonding reliability. Literature reported corrosion studies mostly focus on intermetallic compounds as the corrosion vulnerability. Utilizing a novel corrosion screening approach, we established that the bimetallic contact between Cu balls and Al bond pad is the real driver for the observed heavy Al pad corrosion induced by chloride ions [1]. We identified, for the first time, H2 evolution was the coupling cathodic half reaction to the Al bond pad corrosion. With these improved mechanistic insights, we developed an effective corrosion inhibition strategy that utilizes chemical vapor deposition to selectively bond corrosion inhibitors to these critical Cu ball/Al pad interfaces. A new corrosion-screening platform was developed to evaluate the effectiveness of this inhibitor protection treatment. After intentionally loaded chloride contaminants on the die surface, the molded Cu wire bonded devices with selected inhibitor treatment were subjected to PCT stress tests. The subsequent failure analyses, showed selected inhibitor treatment is highly effective of preventing Al bond pad corrosion even under the massive attack of heavy Cl− ion contamination and extensive delamination.

Deriving lifetime predictions for wire bonds at high temperatures

We report a method to predict wire bond lifetimes. Wire bond resistance increase due to thermal stress can be modelled by the Arrhenius equation, permitting prediction of wire bond reliability in a product prior to qualification if sufficient experimental data is collected and statistically analysed. Activation energies for various experiment “legs” are determined by stressing a number of wire bonds at 3 different temperatures, then, using survival analysis techniques for accelerated failure time models, extrapolating results to use conditions. Example lifetime predictions for Cu and PCC wire bonds on Al pads are shown to illustrate the method, using a small number of test dies that incorporate four-wire resistance measurements of wire bond pairs, with two ball bond sizes and two different wire types, stressed at precise temperatures with in-situ resistance monitoring in the University of Waterloo's “mini-oven” reliability test systems. These results show that typical Cu wire bonds on Al bond pads can be highly reliable up to 163 °C without encapsulation or 155 °C with encapsulation, with estimated lifetimes of 12,000 h with <1 ppm failure rate, assuming a failure condition of 10% resistance change.

The Bondability and Reliability of a Ternary Ag Alloy Wire on an Al Bonding Pad under N&lt;sub&gt;2&lt;/sub&gt;-Free Conditions

The Bondability and Reliability of a Ternary Ag Alloy Wire on an Al Bonding Pad under N&lt;sub&gt;2&lt;/sub&gt;-Free Conditions

Influence of heat flow direction on solder ball interfacial layer

Abstract This paper deals with the research of an intermetallic layer of SAC305 solder balls soldered from three directions of the heat flow in the ball-attach process for BGA package. From the point of view of the heat flow direction, the samples were soldered by infrared heating. The heat sources were placed on the top, bottom and both lateral sides of the BGA package. After the solder balls-attach process, a metallographic cross-section was performed, followed by selective etching to visualize the relief of the intermetallic layer. Images of the interfacial between the solder and solder pad were taken from the created samples, followed by measurement of the average thickness and root mean square roughness of the intermetallic layer. The results showed changes in the intermetallic layer. The largest thickness of the intermetallic layer was observed on samples soldered from the top and both sides. Soldering with the bottom infrared heater resulted to the smallest thickness of the intermetallic layer. The same trend was in the roughness of the IMC layer. The greatest roughness was found for samples soldered by the top and both side heaters. The top soldered samples exhibit the smallest roughness.

Glass Frit Wafer Bonding for Encapsulating Monolithic Integrated CMOS-MEMS Devices

CMOS-MEMS integration is getting a more and more important topic with growing expectations and requirements on the function and performance of micro sensors. The integration of ASICs and memories to MEMS sensor structures allows by calibration the compensation of side effects (temperature influences, stress influences, …) and manufacturing tolerances. Thus, very accurate sensors, at acceptable cost structures for high volume applications become feasible. These high volume applications are often for mobile devices or other use cases where the form factor is important as well – here the wafer level integration and the wafer level packaging (wafer bonding) also offer many opportunities. This paper addresses a 0.35µm CMOS process (X-FAB XH035 technology) based integrated sensors. The sensor structure is constructed by using standard features of the CMOS components. To reach the required performance on chip, ASIC including memories are needed. All these features are on one and the same wafer – MEMS and CMOS are side by side monolithically integrated in the same piece of silicon. To make the sensor functional, parts of the CMOS structures need to be undercut by silicon etching from the wafer front side. This requires the opening of the CMOS passivation to get access to the silicon and a very special release etch process. In a next step, these released very fragile structures need to be protected mechanically on wafer level by bonding a structured cap wafer. Additionally, in this step a hermetically sealed cavity with the MEMS structure is formed. By a dicing process the silicon over the wire bond pad area is finally removed to enable wafer probing (Fig. 1 and 2 show this configuration). By advanced packaging processes (die and wire bonding and special plastic moulding) the final device is realized in a small and thin package. In this very complex technology wafer bonding is a key process. Glass frit wafer bonding was chosen as bonding process as it allows a quite simple process set up. The Glass paste can be printed on top of the structured cap wafer and after the multiple temperature step glass conditioning (firing) the wafer can be bonded on the processed MEMS/CMOS wafer. However, many side effects need to be considered in this process to fulfil the sensor performance spec and to get a stable production process. These aspects are here shortly named and will be discussed in detail in the related full paper: The bonding has to be done on top of CMOS structures, actually on top of the CMOS passivation. The passivation stack itself should not be changed - so the bonding surface is silicon nitride, due to its hydrophobic nature it is rather difficult to bond. Additionally, any damages of passivation need to be avoided. Due to the fact that any glass frit is containing sharp filler particles to adapt the thermal coefficient of extension of the glass to the silicon, a paste material has to be used with low particle sizes to prevent a damaging of the passivation. By additionally using a flat passivation, variant local stress can be avoided - this is preventing from passivation cracks. The bond interface has to be of high quality. The bond needs to be mechanically strong and hermetically sealed. The requirement for this is a very good screen printing process – fig. 3 shows such an optimal structure. By means of screen printing process improvements this could be stably achieved. The second important point here is the bonding temperature: it has to be high enough to let the glass flow wet the surface to allow a sealing and strong bonding. Here optimizations resulted in a nearly 100 % yield of sealed devices and prevented the removal of any caps in the later process steps like dicing. This application of the glass fit bonding shows that this process can be used for very sophisticated applications. The investigation provided a new understanding of the material, the bonding process and boundary conditions. Acknowledgements: The authors would like to thank Dr. Frank Seifert (Fraunhofer ENAS Chemnitz) for supporting the screen printing process optimization and Dr. Appo van der Wiel (Melexis) for advising about device integration aspects. Figure 1

Failure Mode and Mechanism Analysis for Cu Wire Bond on Cu/Low-k Chip by Wire Pull Test and Finite-Element Analysis

In this paper, failure mode and mechanism analysis on Cu wire bond and bond pad reliability for Cu/low-k chip are investigated through wire pull test and finite-element analysis (FEA). The wire pull test has been carried out for the bonded Cu wires with changing pull position to reveal different failure modes. Failed load is monitored and failure mode is analyzed for different wire pull test conditions. It is observed that the pull position influences failed pull force and failure mode. Failure modes include broken wire neck and wire wedge, ball lift, and pad peel and the failed force decreases with a changing pull location from the ball bond toward the wedge bond. FEA simulation is performed to help further understand failure mechanism and establish failure criteria. Finally, failure mechanism and criteria are presented for different failure modes and materials. In addition, the influence of wire loop height is also studied.

Characterization of the Contamination Factor of Electroless Ni Plating Solutions on the ENIG Process

The electroless nickel immersion gold process often produces defects, such as pinholes and black pads that can cause brittle fractures at the interface between the solder and metal pad. Contamination in electroless Ni plating solutions with increasing metal turn over (MTO) is believed to be one of the causes of the formation of surface defects. MTO means indirectly Ni bath life, with ‘‘0 MTO’’ indicating a freshly plating bath and ‘‘2 MTO’’ an aged plating bath, which is supplemented twice with the initial amount of metallic salts and the reducing agent. In this study, surface defects on the Ni-plated layer were investigated to understand the correlation between the MTO solutions and defect factors by solder resist (SR) dissolution. The characteristics of the contaminated MTO solutions were analyzed by total organic carbon and liquid chromatography mass spectrometry (LC-MS). LC-MS detected the component (melamine) of the hardener of the SR at 2.14 ppm in the 2 MTO, and 2.52 ppm in the 2.5 MTO solutions. Electroless nickel plating was conducted in a 0 MTO solution with hardener addition. Pinholes were observed in solutions containing more than 2 ppm of a hardener. In particular, the content of phosphorus in the defective area was higher than that in the non-defective area. Consequently, as the MTO solution increased, the hardener was dissolved in the Ni solution, which caused defects in the nickel surface layer, such as pinholes and black pads.

Application of laser heating and its effects on bonding strengths for varied copper wire purity levels

Gold as the medium of interconnection is rapidly being replaced by copper as a means of creating connectivity in integrated circuit packaging. However, the use of copper wire is known to pose many threats in integrated circuit packaging, especially for devices with very thin die structures. The process of wire bonding which involves the formation of free air ball can be risky to the quality of integrated circuit packaging. The impact of hard copper free air ball onto the bonding surfaces may damage the bond pad and the silicon die. These challenges require innovative solutions that are able to be applied to integrated circuit packaging with minimal thermal and mechanical effect on the device. Through recent research, it is apparent that the laser processing technology can provide viable innovative solutions to electronic packaging. This research paper investigates the application of laser heating on copper wire bonding technology and its effects on bonding strength for three copper wire purity types, 99.9% purity (3 N), 99.99% purity (4 N), and 99.999% purity (5 N) copper wires. Wire bonding was performed on bond pads consisting of NiPdAu metallization under 16 different temperature conditions. Results of this study showed that different copper purity levels exhibit different bonding strengths with the application of laser heating. It is shown in this research that significantly higher as-bonded ball shear strengths were obtained when laser heating was applied at all three copper wire purity types. The results of this study can be helpful for integrated circuit packaging with copper wire bonding on thin die structures. Copper wires with lower purity levels are shown as a viable option by further improving the wire bonding quality with the application of laser heating without the need to use excessive bonding temperature, higher bonding force, and excessive ultrasonic energy.Gold as the medium of interconnection is rapidly being replaced by copper as a means of creating connectivity in integrated circuit packaging. However, the use of copper wire is known to pose many threats in integrated circuit packaging, especially for devices with very thin die structures. The process of wire bonding which involves the formation of free air ball can be risky to the quality of integrated circuit packaging. The impact of hard copper free air ball onto the bonding surfaces may damage the bond pad and the silicon die. These challenges require innovative solutions that are able to be applied to integrated circuit packaging with minimal thermal and mechanical effect on the device. Through recent research, it is apparent that the laser processing technology can provide viable innovative solutions to electronic packaging. This research paper investigates the application of laser heating on copper wire bonding technology and its effects on bonding strength for three copper wire purity types, 99.9...