Board-level Test Research Articles

Radiation tests of a CubeSat OBC

Nano-satellites, which are following the CubeSat standard have established for demanding industrial and scientific applications with critical requirements on reliability and radiation tolerance. The employment of commercial off-the-shelf components enables a state-of-the-art performance but requires extensive testing to avoid and mitigate malefunctions due to the space environment. The CubeSat mission CLIMB is representative for future missions with a complex payload, a high power budget and a harsh radiation exposure. For this reason, a comprehensive irradiation study of its on-board-computer was done. The total ionizing dose damage of 50krad was evaluated at a 60Co source. As a consequence of this test, specific components were exchanged before performing single event effect studies at the synchrotron accelerator MedAustron. A board-level test revealed that the majority of effects concern the central micro controller wherefore was followed by a component-level test. Those irradiation tests make use of a pencil beam to map the device under test, which provides additional information to localize effects - by the timestamp - at the expense of an increased irradiation time compared to a homogeneous exposure. In this paper, we summarize the major findings of the test campaign and mitigation means and present a procedure for single event effect studies at medical accelerators.

Prediction of Board Level Pad Cratering Strength With the Predefined Failure Criteria From Joint Level Testing

Abstract Conventional reliability tests for the evaluation of pad cratering resistance are mainly classified into two categories: the board level test and the joint level test. The board-level test is to imitate the loading conditions during normal operation. However, this type of test is expensive and not flexible. The joint level test is used extensively in the industry because it has the advantages of lower cost, higher throughput, and more quantitative results. It also allows the elimination of confounding factors such as PCB and component stiffness. Therefore, it is always desirable to predict the board level performance by a joint level test. In order to achieve this objective, the correlation between the joint level and the board-level tests must be fully understood. Nevertheless, a precise correlation between the two types of tests for pad cratering evaluation is yet to be defined. This study investigates the pad cratering failure mode for the correlation of critical failure factors between joint and board level tests. An intermediate critical failure factor could be taken as a failure criterion in board-level testing for failure detection. For verifying the validity of such a failure criterion, an experimental study should be performed. The 4-point bending test is chosen as the board-level test for critical failure factor validation. In addition, an innovative pin shear test method is developed as the joint level test for failure factor detection. Both test methods are assessed by a series of parametric studies with an optimized process to ensure the accuracy of the results. From the results of the experimental study and simulation, the critical failure factor correlation is established between the board level 4-point bending and the joint level pin shear test. Using finite element analysis (FEA), the critical failure strain is identified from the pin shear test model and will be employed as the board level failure criterion. Subsequently, the obtained failure criterion is verified by a 4-point bending model. As a result, this indirect correlation method can predict the board level failure with various geometric parameters.

Numerical and Experimental Analyses of Component Failure Risk in a Mobile Phone Under Drop Test

Owing to the complex stress condition of the on-board devices in a mobile phone under drop impact condition, high test cost, and long validation period are usually spent on product-level drop test for product design. Most of the standardized test protocols including the Joint Electron Device Engineering Council (JEDEC) standard for handheld electronic products are essentially based on board-level tests, not taking into account the interaction between the printed circuit board (PCB) and other internal components, so the accurate experimental validation of product-level drop reliability remains time-consuming. This article established a finite element model of a whole mobile phone for the simulation of its product-level drop tests. By conducting simulation of six-side and four-corner drop postures, it is found that the risk of overstress failure of the critical large chips and solder joints on the PCB are relatively higher in the case of back drop and front drop. The bending of the PCB and the collision between the shielding frame and the front frame of the mobile phone are the decisive factors that bring the overstress failure risk of the chip and solder joint. Finally, a series of product-level drop tests were conducted and compared with the simulations, with a variance of stress value within 20%, which proves that the simulation model could provide useful insights for the reliability design and validation phase during the development of new products.

Property of Sn-37Pb solder bumps with different diameter during thermal shock

PurposeThe impact strength of solder joint under high strain rate was evaluated by board level test method. However, the impact shear test of single solder bump was more convenient and economical than the board level test method. With the miniaturization of solder joints, solder joints were more prone to failure under thermal shock and more attention has been paid to the impact reliability of solder joint. But Pb-free solder joints may be paid too much attention and Sn-Pb solder joints may be ignored.Design/methodology/approachIn this study, thermal shock test between −55°C and 125°C was conducted on Sn-37Pb solder bumps in the BGA package to investigate microstructural evolution and growth mechanism of interfacial intermetallic compounds (IMCs) layer. The effects of thermal shock and ball diameter on the mechanical property and fracture behavior of Sn-37Pb solder bumps were discussed.FindingsWith the increase of ball size, the same change tendency of shear strength with thermal shock cycles. The shear strength of the solder bumps was the highest after reflow; with the increase of the number of thermal shocks, the shear strength of the solder bumps was decreased. But at the time of 2,000 cycles, the shear strength was increased to the initial strength. Minimum shear strength almost took place at 1,500 cycles in all solder bumps. The differences between maximum shear strength and minimum shear strength were 9.11 MPa and 16.83 MPa, 17.07 MPa and 15.59 MPa in φ0.3 mm and φ0.4 mm, φ0.5 mm and φ0.6 mm, respectively, differences were increased with increasing of ball size. With similar reflow profile, the thickness of IMC decreased as the diameter of the ball increased. The thickness of IMC was 2.42 µm and 2.17 µm, 1.63 µm and 1.77 µm with increasing of the ball size, respectively.Originality/valuePb-free solder was gradually used to replace traditional Sn-Pb solder and has been widely used in industry. Nevertheless, some products inevitably used a mixture of Sn-Pb and Pb-free solder to make the transition from Sn-Pb to Pb-free solder. Therefore, it was very important to understand the reliability of Sn-Pb solder joint and more further research works were also needed.

Analysis and implementation of SDH protocol in 10Gbps POS signal

The data transmission network based on synchronous digital Hierarchy (SDH) can fundamentally solve the problems of capacity, quality, network management, security and so on in the network transmission of IP services. POS (Packet Over SDH) technology is a way to implement IP service in SDH data transmission network. An analytical solution of SDH protocol with Stratix5 FPGA as the core is studied. According to the SDH standard defined by ITU-T, the analytical circuit of SDH protocol in 10Gbps POS signal is designed on FPGA. The circuit is divided into data receiving module, line overhead module, channel spending module and status register output module, to complete data receiving, information extraction, and output of state information and net load data. The results of functional simulation and board level test show that the scheme is accurate, efficient and consistent with the standard, which can provide some reference value for the development of SDH technology.

Design and Implementation of Abnormal Behavior Detection Based on Deep Intelligent Analysis Algorithms in Massive Video Surveillance

Aiming at the high complexity of existing crowd abnormal detection models, the inability of traditional CNN to extract time-related features, and the lack of training samples, an improved spatial-temporal convolution neural network is proposed in this paper. The algorithm firstly uses the aggregation channel feature model to process the surveillance image, and selects the suspected object region with saliency characteristics. Then, the scaled correction and feature extraction are performed on the obtained suspected object region. The corresponding low-level features are obtained and input into the deep network for deep feature learning so as to enhance the representation ability. Finally, the deep feature is input into the least squares SVM classification model to obtain the final abnormal behavior detection result. The embedded chip Hi353I is used as the hardware processor to realize the real-time abnormal behavior detection effect. Our proposed deep intelligent analysis algorithm is used as abnormal Behavior Detector in the board level test. The results show that most of abnormal behaviors can be detected and the alarming message can be timely transmitted in the real-time surveillance.

Vertical GaN power rectifiers: interface effects and switching performance

The emergence of free-standing GaN substrates enables the development of vertical GaN-on-GaN devices with high-power ratings and high frequencies. The Schottky interface plays an important role in determining the current transport mechanisms and the forward/reverse electrical performance of the vertical GaN Schottky barrier diodes. Moreover, given its direct bandgap and ultrashort minority carrier lifetime, it is of particular interest and importance to evaluate the fast switching performance of the vertical GaN power rectifiers. In this paper, we discuss the technology, physical mechanisms and characterizations of vertical GaN power rectifiers with high-quality interfaces and fast switching performances, including: (a) accurate characterization and carrier transport mechanisms of the Schottky interface; (b) Schottky interface engineering with optimized post-metallization annealing and a tunneling-enhancement layer; (c) fast reverse recovery performance that is characterized by high-speed board-level tests. The investigations and analysis on the interface effects and switching performance of the vertical GaN power rectifiers are valuable for high-efficiency and high-frequency power electronics applications.

Characterization of a COTS-Based RF Receiver for Cubesat Applications.

This paper reports the experimental results of a test campaign performed on the radio-frequency (RF) receiver prototype operating at a 2025–2110 MHz frequency range, designed and fabricated for CubeSat applications. The prototype has been tested through a board-level test approach for the verification of the functional requirements and a component-level one for specific characterization measures. The tests have shown the following results: a −115–−70 dBm sensitivity range, 390 MHz intermediate frequency, a 0 dBm output power level with ±1 dB error, a 2.34 dB noise figure, and a 4.86 W power absorption. Such results have been largely achieved implementing an automatic gain control system by cascading two Commercial Off-The-Shelf (COTS) amplifiers. Moreover, an innovative technique based on RF test points has been successfully experimented and validated to measure the S-parameters of a custom low-pass filter integrated on the receiver, showing the possibility of even characterizing the single COTS components exposed to radiation through a unique board-level test setup. The technique may have a great impact on the cost reduction of electronic boards for space applications, since it would avoid using expensive evaluation boards for each COTS component that needs a radiation test.

The Algorithm of Direct Current Smooth Filtering Based on the Minimum Resource Consumption in FPGA

The algorithm of direct current smooth filtering was proposed in this paper to satisfy the requirement of minimum resource consumption in FPGA and to meet the goal of calculation period in minimum length. In this work, the detail circuit was designed by FPGA and the key circuit was simulated by the modalism. The result of board-level test is shown that the dither amplitude of original direct current was decreased significantly at 90%. The amplitude was in the stable state to reach expected smoothing effects.

Electrothermal coupling analysis and experimental verification for wirebond devices

The thermal performance of a powered wirebond device with package level and board level test specimens was investigated by both analytical and experiment methods. The effects of thickness and thermal conductivity of the molding compound and heat spreader attached to the top surface of the molding compound on the performance of the Au wire and silicon die were modeled and evaluated by three-dimensional electrothermal coupling analysis. An advanced quad flat no-lead (QFN) sample was selected to experimentally measure the maximum allowable current in Au wire for packages either with or without molding compound. Two failure modes, namely the fusing of the wire and the decomposition temperature of the molding compound, were established in analysis. A board level test specimen with a thermal test die was also employed to measure the real time package thermal performance. The major achievement of this work is in the complete combination of modeling, experiment, and optimization for thermal performance evaluation purpose of a powered wirebond device. Results of this physical analysis can provide a reliable and useful guide to estimate the maximum allowable currents in Au wires for a wirebond device under practical application conditions.

Study of Jtag-Tap Controller for Board Level Testing

Study of Jtag-Tap Controller for Board Level Testing

Run-time reconfigurable instruments for advanced board-level testing

The last decade has seen increasingly rapid growth in the prevalence of FPGA devices. Today, FPGAs are extensively used in all commercial sectors, like communications, consumer, military and industry. Test engineers also recognized a great potential of FPGAs for test and measurement (T&M) purposes. The main benefit of FPGA devices is a possibility for hardware reconfiguration. This feature turns FPGAs into a flexible hardware base for T&M instrumentation. Multiple different instruments can be implemented and executed on the same FPGA device, thus significantly reducing the expense of purchasing stand-alone hardware instruments. At the same time, FPGAs being integrated to the system can also be exploited as a platform for embedded instrumentation (EI) [1]. In this work, we consider an approach that temporarily reuses an existing on-board FPGA resource to carry out necessary manufacturing tests. As the allocated FPGA logic is reclaimed for functional use after the test is finished, the presented technique does not require hardware changes and thus does not introduce additional costs.

Experimental Study on 28nm Chip/Package Interactions in eWLB (Embedded Wafer Level BGA) Fan-Out Wafer Level Packages

To meet the continued demand for form factor reduction and functional integration of electronic devices, WLP (Wafer Level Packaging) is an attractive packaging solution with many advantages in comparison with standard BGA (Ball Grid Array) packages. The advancement of fan-out WLP has made it a more promising solution as compared with fan-in WLP, because it can offer greater flexibility in enabling more IO's, multi-chips, heterogeneous integration and 3D SiP. In particular, eWLB (Embedded Wafer Level BGA) is a fan-out WLP solution which can enable applications that require higher I/O density, smaller form factor, excellent heat dissipation, and thin package profile, and it has the potential to evolve in various configurations with proven integration flexibility, process robustness, manufacturing capacity and production yield. It also facilitates integration of multiple dies vertically and horizontally in a single package without using substrates. For eWLB fan-out WLP, the structural design as well as selection of materials is very important in determining the process yield and long term reliability. Therefore it is necessary to investigate the key design factors affecting the reliability comprehensively. This work is focused on an experimental study on the chip-package interactions in eWLB fan-out WLP with multilayer RDL's. Standard JEDEC component and board level tests were carried out to investigate reliability, and both destructive and non-destructive analyses were performed to investigate potential structural defects. Warpage, die cracking and other failures were characterized through metrology measurements and electrical tests. Board assembly processes (including SMT, underfill, etc.) were also studied. The influence of materials and structural design on the package reliability will be demonstrated. Thermal characterization and thermo-mechanical simulation results will also be discussed.

Column-grid-array (CGA) versus ball-grid-array (BGA): board-level drop test and the expected dynamic stress in the solder material

Board level drop test is considered with an objective to develop a physically meaningful analytical predictive model for the evaluation of the expected impact-induced dynamic stresses in the solder material. Ball-grid-array (BGA) and column-grid-array (CGA) designs are addressed. Intuitively it is felt that while the application of the CGA technology to relieve thermal stresses in the solder material might be quite effective (owing to the greater interfacial compliance of the CGA in comparison with the BGA), the situation might be quite different when the PCB/package experiences dynamic loading. This is because the mass of the CGA joints exceeds considerably that of the BGA interconnections and the corresponding inertia forces might be substantially larger in the case of a CGA design. The numerical example carried out for rather arbitrary, but realistic, input data has indicated that the dynamic stresses in the solder material of the CGA design are even higher than the stresses in the BGA interconnections. This means particularly that the physically meaningful drop height in board-level tests should be thoroughly selected and that this height should be different, for BGA and CGA designs.

Board level drop test: exact solution to the problem of the nonlinear dynamic response of a PCB to the drop impact

An analytical predictive model has been developed for the evaluation of the nonlinear dynamic response of a printed-circuit-board (PCB) to the drop impact during board-level testing. The hypothesis of “heavy-and-flexible” PCB is used in the analysis: the surface-mounted-devices (SMDs) are assumed to be small enough not to affect the PCB’s flexural rigidity, but their masses have been considered and accounted for by “spreading out” the SMD total mass over the PCB surface. The analysis is restricted to the fundamental mode of vibrations, and the method of principal coordinates is used to evaluate the response. The exact solution to the nonlinear differential equation for the principal coordinate has been obtained. Another important finding is that the nonlinear amplitudes were determined even without solving the nonlinear differential equation of motion. The main objective of the analysis is to provide design guidelines for constructing a feasible experimental setup. A simply supported board is suggested as the most appropriate structure for an adequate test vehicle: the experimental data for such a board, as far as the behavior of the solder material in the second level of interconnections is concerned, can be easily and reliably interpreted and extrapolated for the practical use. The developed model enables one to predict the induced bending moments and the in-plane (membrane) forces that could be applied in the subsequent analyses to the PCB areas in the proximity of the package and its solder joint interconnections.

Optimization of Boundary Scan Tests Using FPGA-Based Efficient Scan Architectures

This paper presents a method for optimization of board-level scan test with the help of reconfigurable scan-chains (RSCs) implemented in a programmable logic of FPGA. Despite that the RSC concept is a well-known solution for scan-based test time reduction, the usage of RSC may lead to un-acceptable hardware overhead. In our work, we are targeting a completely new approach of exploiting on-board FPGA resources that being unconfigured are typically available during the manufacturing test phase for carrying out tests using temporarily implemented virtual RSC structures. As the allocated FPGA logic is re-claimed for functional use after the test is finished, the presented method delivers all the advantages of RSCs at no extra hardware cost. Experimental results show that the proposed virtual RSCs can fit into all available commercial FPGAs providing a significant test time reduction in comparison with state-of-the-art Boundary Scan test tecnique.

Standardization of automated industrial test equipment for mass production of control systems

Power converters and their controls electronics are key elements for the operation of the CERN accelerator complex, having a direct impact on its availability. They must be designed to achieve a high Mean Time Between Failure (MTBF) and hardware reliability must be ensured by board level testing before hardware is assembled and installed. In this framework, the National Instrument PCI extension for Instrumentation (PXI) was chosen as standard platform for the development of testers. This paper reports on the design strategy and approach used focusing on the tester hardware, firmware and software development.

TCT Reliability of Organic Passivation Layer for WLCSP

Wafer level chip scale packages (WLCSP) have been increasingly used in portable electronic products such as mobile phones. Solder bumps with redistribution layer (RDL) are typical interconnect technology for WLCSP applications. One of the major concerns in joint reliability is the failure by temperature cyclic stresses. In addition, in terms of heat tolerance or device yields, process temperature of RDL dielectric is limited around 200deg.C in some packaging applications. According to our board level reliability test for temperature cycle test (TCT), photosensitive polyimide (PI) which is 200deg.C curable material has lower fail rate than polybenzoxazole (PBO) by TCT. In this study, we compared the actual board level test and Finite Element Analysis (FEA) during temperature cycle test, and correlated the mechanical and fatigue properties of passivation layer material with TCT reliability.

Hierarchical Test Integration Methodology for 3-D ICs

In this paper, we propose a hierarchical test integration method for 3-D ICs. The method can handle a die with logic cores and memory cores. In addition to handle the test controlling of a hierarchical 3-D IC, furthermore, it also can support the test controlling of a 3-D IC with multiple towers. For a 3-D IC, the hierarchical test integration method uses two types of 1149.1-based test interfaces for the bottom die and nonbottom dies. Therefore, the test access ports for the two test interfaces are the same. Also, the number of required test pads of the proposed test interface is only 4. Furthermore, the test interface is compatible with the IEEE 1149.1 standard for the board-level testing.

An ARM-based debugging system for multi-pole array acoustic logging tools

This paper presents a debugging system for multi-pole array acoustic logging (MPAL) tools. The debugging system proposed in this study can debug the MPAL tool system, sub-system and local electronics. In the test equipment, we have used principal and subordinate structures, and interconnected the host computer and the front-end machine via Ethernet. The front-end machine is based on the ARM7 (advanced reduced instruction set computing (RISC) machine) technique, the processor of which runs an embedded operating system, namely, uClinux OS. We have analyzed the system telecommunication, human-machine interface circuit, transmitter mandrel interface circuit, receiver mandrel interface circuit, and board-level test interface circuit. The software used in the system consists of the embedded front-computer software and the host application software. We have explained in detail the flow chart of the boot loader in the embedded front-computer software. The host application software is composed of four application subroutines, which match with the functional modules of the system hardware. A net communication program based on the server/client mode is implemented by means of socket programming and multi-thread programming. Test results indicate that the data transmission rate of the system is higher than 1 MB/s, which completely meets the current requirements of the data transmission rate between the tool system and the wireline telemetry device. Application of the debugging system, which includes multiple level test methods, shows that the proposed system can fully meet the test requirements of MPAL at various levels.