Abstract
The algorithm of direct current smooth filtering was proposed in this paper to satisfy the requirement of minimum resource consumption in FPGA and to meet the goal of calculation period in minimum length. In this work, the detail circuit was designed by FPGA and the key circuit was simulated by the modalism. The result of board-level test is shown that the dither amplitude of original direct current was decreased significantly at 90%. The amplitude was in the stable state to reach expected smoothing effects.
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