Board Level Reliability Research Articles

Board level reliability analysis of chip resistor assemblies under thermal cycling: A comparison study between SnPb and SnAgCu

Accelerated thermal cycling (ATC) tests are conducted for various chip resistor assemblies using the lead-based (SnPb) and lead-free (SnAgCu) solders. The corresponding life prediction models are developed by employing the well-established energy density approach. The life prediction model constants are obtained from the ATC test data. The models are utilized to predict the lifetimes of chip resistor assemblies under a mobile device field condition. The analysis indicates that the lead-free solder used in the chip resistor assembly would offer a longer lifetime under a field condition compared to the lead-based solder regardless of chip resistor types even when a reverse trend is observed in the ATC test results.

Finite Element Analyses for Critical Designs of Low-Cost Wafer-Level Chip Scale Packages

With the advantages of high performance and low cost, the wafer-level chip scale package (WLCSP) is widely used in integrated circuit fabrication today with rapidly growing demand in the semiconductor packaging industry. As WLCSP moves toward thinner, smaller, lower cost, and fine-pitch package designs to meet the increasing requirements of electronic products, a lot of challenges need to be overcome. The most important challenge is preventing failure and enhancing package reliability. To understand the mechanical behaviors of WLCSP, comprehensive finite-element analyses (FEAs) for various WLCSP structures, including the general design with one under-bump-metallurgy layer, one redistribution layer (RDL), and two polymer layers on a passivated wafer (called 2P2M WLCSP in this paper, which means that there are two polymer layers and two metal layers on the passivated wafer), the low-cost designs of 2P1M WLCSP (with two polymer layers and only one RDL on a passivated wafer) as well as 1P1M WLCSP (with only one polymer layer and one RDL on a passivated wafer) were carried out. Different parameters in WLCSP were investigated to look for critical factors that impact the corresponding stresses. Moreover, the board level reliability thermal cycling test that followed JEDEC standard was used, which suggested that the solder cracks were observed mostly near the intermetallic compound layer in WLCSP structures and aligned with the FEA results. Hence, by employing reliable modeling, not only can the critical factors that affect the stress responses be obtained but also can the proper parameters to provide the best reliability in WLCSP be determined. This paper offers a good reference and can effectively serve as design guidelines in cases of significant factor selection analyses on WLCSP designs.

Failure Analysis of Board-Level Sn-Ag-Cu Solder Interconnections Under JEDEC Standard Drop Test

This work investigates the board-level drop reliability of printed circuit boards (PCBs) assembled using three chip-size packages subjected to Joint Electron Device Engineering Council (JEDEC) standard drop test condition B. The acceleration and dynamic strain responses at several locations of the board-level package in the time and frequency domain are comprehensively investigated. The results in the time domain suggest that the dynamic response of the board-level package has two phases: forced vibration and free vibration. The maximum response occurs at the first half free vibration cycle. The acceleration response at the center of the PCB is larger than at the edges, whereas the dynamic strain response is just the opposite. The results in the frequency domain show that the first mode is fundamental. In addition, failure analysis is performed using the dye-and-pry test and cross-section test, suggesting that the brittle cracking occurs at the layer between the integrated circuit (IC) pad and the solder, not only through intermetallic compound (IMC) but also along the surface between the IC pad and IMC.

Improving WLCSP Reliability Through Solder Joint Geometry Optimization

The effects of solder joint geometry on wafer-level chip-scale package reliability have been studied both through simulations and board level reliability testing. In reliability tests on a 3.9×3.9mm2 die, an enhancement of nearly 2× in thermal cycling reliability was achieved by optimizing the solder joint and under-bump pad stack. In particular, undersizing the printed circuit board pad to produce a more spherical solder joint and reducing the polymer via size under the bump appear to be very important for improving thermal cycling results. Data collected here shows that joint geometry changes can be implemented without compromising drop performance. Methods learned were applied to the qualification of a 6.0×6.0mm2 die, a large platform for WLCSP applications.

High Reliability Fine Pitch WLCSP for High Pin Count Applications

Wafer Level Chip Scale Packages (WLCSP) have seen wider adoption in hand held as well as automotive electronics in recent years due to their unmatched form factor reductions and improved electrical performance. WLCSP's have gained popularity in high pin count IC's with tighter pitches and increased reliability requirements. Enhanced board level reliability is achieved by using solder spheres with higher silver content. Traditionally, automotive applications require an improvement in thermal cycling over WLCPS found in hand held applications. This paper will study the differences in solder alloy and include a comparison to under filled parts to meet these reliability requirements. This study shows characteristic life that exceeds the industry standard requirements for the drop and thermal testing reliability testing.

Board-Level Solder Joint Reliability of Edge- and Corner-Bonded Lead-Free Chip Scale Package Assemblies Subjected to Thermal Cycling

In this paper, we present the results of thermal cycling test for edge- and corner-bonded lead-free chip scale packages (CSPs), which was carried out on the basis of the IPC-9701 test standard. Six materials were used in this study: four edge-bond adhesives and two corner-bond adhesives. These adhesives were compared with CSPs with full capillary flow underfill (FCFU) and without adhesives. The thermal cycling test results show that corner-bond adhesive has comparable solder joint reliability performance with CSP without adhesive, and is better than edge-bond adhesive, followed by CSPs with FCFU. In addition, the adhesives with a low coefficient of thermal expansion, a high glass transition temperature and a intermediate storage modulus yielded good performance. Results of detailed failure analysis indicate that the dominant failure mode is solder bulk fatigue cracking near package and/or printed circuit board (PCB) pads, and that the location of critical solder joints change from die edges to package corners with the introduction of adhesives.

Board-Level Solder Joint Reliability of Edge- and Corner-Bonded Lead-Free Chip Scale Package Assemblies Subjected to Thermal Cycling

In this paper, we present the results of thermal cycling test for edge- and corner-bonded lead-free chip scale packages (CSPs), which was carried out on the basis of the IPC-9701 test standard. Six materials were used in this study: four edge-bond adhesives and two corner-bond adhesives. These adhesives were compared with CSPs with full capillary flow underfill (FCFU) and without adhesives. The thermal cycling test results show that corner-bond adhesive has comparable solder joint reliability performance with CSP without adhesive, and is better than edge-bond adhesive, followed by CSPs with FCFU. In addition, the adhesives with a low coefficient of thermal expansion, a high glass transition temperature and a intermediate storage modulus yielded good performance. Results of detailed failure analysis indicate that the dominant failure mode is solder bulk fatigue cracking near package and/or printed circuit board (PCB) pads, and that the location of critical solder joints change from die edges to package corners with the introduction of adhesives.

Board Level Reliability of Solder Joint with a Low CTE PCB

With increasing market demands of electric products for smaller, thinner, and faster, printed circuit board (PCB) are pushed to accommodate these requirements. A PCB with low CTE and high elastic modulus could be an alternative to be able to meet the requirements needed for the next generation of high-performance microsystems. In this study, the board level reliability test was performed to evaluate solder joint reliability of low CTE PCB and conventional PCB. Solder joint could be generated the failure due to stresses induced by large coefficient of thermal expansion (CTE) mismatch between silicon and printed circuit board (PCB) under temperature variation. Also, in daily use portable devices such as cellular phones, PDAs, and MP3 players, it is common for them to be subjected to accidental drop impacts resulting in damage and hence failures. Therefore, the reliability performance of solder joints during temperature cycling and drop test is a key issue and it was focused to obtain the board level reliability of solder joint on low CTE PCB. After board level reliability test, cross-section SEM and OM was done to analyze fracture modes of solder joint reliability.

ChipletT, A Cost-Effective, High Reliability, Embedded Die Fan-Out Package Based on Multilayer Flex Laminate with Enhanced Thermal Performance

Fan-Out Wafer Level Packaging (FO-WLP) technology has been developed in recent years to overcome the limitations of Fan-in WLP (FI-WLP) packages and to add more functionality to WLP. Fan-Out packages expand the WLP market to higher pin count devices and add multiple die System in Package (SiP) capability. In this paper, a novel approach to low cost fan-out packaging based on polyimide flex circuits and wafer level Embedded Die Customization (EDC) is discussed. ChipletT refers to Fan-Out packaging. ChipsetT refers to System in Package developed with WABE (Wafer and Board Level Embedding) technology. WABE technology is based on co-lamination of multi layer polyimide flex wiring and conductive z-axis sintered metal interconnections. Using WABE technology, ultra thin fan-out packages (0.4mm) can be fabricated with lower processing costs, higher throughput and with 3D extendibility. Embedded Die Customization is performed at the wafer level and involves optimization of the die-to-embedding process by using optimized wafer level processing capabilities including polymer processing, copper plating and wafer thinning. Reliability of the ChipletT packages, both component level and board level is evaluated. ChipletT packages show high reliability in component level testing and board level testing (Thermal Cycling and Drop Testing). The thermal performance of ChipletT packages were also evaluated in this study. Thermal resistance parameters θja and θjc were simulated with and without thermal vias for both face up and face down configurations. ChipletT provides a new low cost fan out packaging option with proven component level and board level reliability performance.

Process and Reliability of Embedded Micro-Wafer-Level Package (EMWLP) Using Low Cure Temperature Dielectric Material

In this paper, we present the evaluation results of low cure temperature (less than 200°C) dielectric materials (LCTDMs) in terms of processability and adhesion to silicon nitride and mold compound substrates. The results showed that the LCTDMs have good adhesion to the above substrates. Integration of thin-film passives such as inductors, capacitors, and band-pass filters were also demonstrated on mold compound wafer platform using electroplated copper (Cu) and LCTDM. Thin-film passives fabricated on the mold compound platform using LCTDM showed better performance by two times when compared to the passives fabricated on a high-resistivity silicon wafer. Reliability test vehicles of multichip embedded micro-wafer-level package (EMWLP) were fabricated using Cu redistribution line (RDL), LCTDM, and electroplated Cu under bump metallization with lead-free (Pb-free) solder bump interconnects. Test vehicles were subjected to various package-level and board-level reliability tests as per the JEDEC standards, and failure analysis was carried out after reliability tests. EMWLP with LCTDM passed package-level reliability tests such as unbiased highly accelerated stress test, thermal cycling (TC), and moisture sensitivity test level 3. Test vehicles with underfill passed board-level TC and drop tests. A complete description of dielectric material evaluation for EMWLP, process development of thin-film passives fabrication, and multilayer RDL integration on reconfigured mold compound wafer and its reliability results are discussed.

Study on MEMS board-level package reliability under high-G impact

Under high-G (104 g or above) impact load conditions, the reliability of micro electro mechanical systems (MEMS) board-level package and interconnection are critical concerned that influence the mission success of total projectile. This paper conducts a research on this problem to analyze package reliability using finite element modelling (FEM) and simulation method. Theoretical analysis and mathematical model for failure mechanism of MEMS package under high-G impact are conducted and established. A FEM dynamic analysis is conducted on a typical MEMS board-level leadless chip carrier (LCC) package. Results show that the solder joints are one of the key weakness points that influence the reliability of MEMS package. The maximum effective stress in the structure occurs at the outer corner in the outermost solder point, and the alloy cover and printed circuit board (PCB) have a greater deformation.

Optimal design of thin-profile fine-pitch ball grid array package under drop impact test

This article describes the board-level drop reliability of thin-profile fine-pitch ball grid array (TFBGA) subjected to Joint Electron Device Engineering Council (JEDEC) drop test conditions featuring an impact pulse profile with a peak acceleration of 1500 G and a pulse duration of 0.5 ms. The solder ball is assumed to be an elastoplastic model and the other components linear elastic ones. Both the global/local finite element and the finite grid region methods are introduced to improve the accuracy and the convergence during the meshing process. Meanwhile, the contact impact process during the drop test is translated into the effective support excitation load on the printed circuit board (PCB) through the support excitation scheme to simplify the analysis. By means of optimal parameters of the Taguchi robust design, the average stress of the solder ball at the PCB side surface becomes 80.9 MPa, which shows a 57 per cent reduction compared to the original stress of 189.7 MPa. As a result, the impact reliability of the TFBGA package is significantly improved. Finally, the JEDEC drop test is conducted to verify the optimal results obtained by the Taguchi method.

Low Cost, High Reliability WLCSP for Higher Pin Counts

The proliferation of Wafer Level Chip Scale Packages (WLCSPs) in portable handheld products has occurred due to the minimalist form factor, high reliability and low cost packaging that they afford. As the demand for WLCSPs has grown exponentially in recent years, the industry has also been coping concurrently with the technical challenges associated with increasing array sizes and more demanding end user reliability requirements. Since handsets are inherently prone to being dropped, they are particularly susceptible to this type of component failure though striking a proper balance of mechanical robustness and thermal cycling performance has remained an ongoing industry goal. Similar to other packages, WLCSPs have transitioned over the past decade from lead-based solder alloys to Lead Free (LF) solders. LF solder connections are especially susceptible to brittle fracture and can result in variations in drop test performance from one bump structure to the next. This paper will provide an overview of process and material add-on strategies that have been shown to considerably improve mechanical robustness for bump structures or bumping applications that are inherently less robust than others. Such supplemental improvements can result in passing Board Level Reliability qualification requirements which may otherwise be elusive or have limited levels of reliability reproducibility.

Advances in WLCSP Technologies to Enable Cost Reduction

This paper will provide examples that significantly reduce overall package cost by removing photolithography layers. Each photomask layer removed saves in material costs, capital depreciation costs, overhead, and process cycle time. Materials, package size, and internal qualification vehicles are carefully chosen as part of Amkor's product introduction for the proposed process flows (CSPX3 and CSPX2). This paper examines material options for these structures, with a focus on the redistribution layer and solder alloys. Package level and board level reliability data along with a description of the failure modes are presented.

Board-Level Solder Joint Reliability Study of Land Grid Array Packages for RF Application Using a Laser Ultrasound Inspection System

Microelectronics packaging technology has evolved from through-hole, and bulk configuration to surface-mount, and small-profile ones. Today’s electronics industry is also transiting from SnPb to Pb-free to meet environmental requirements. Land grid array (LGA) package has been becoming popular in portable electronics in terms of low profile on the printed wiring boards and direct Pb-free assembly process compatibility. With the package profile shrinking and operating power increasing, solder joint quality and reliability has become a major concern in microelectronics manufacturing. The solder joint failure at the package level or board level will cause electronic devices not to function during service. In this paper, board-level solder joint reliability of the LGA packages under thermal loading is studied through thermal cycling tests. A novel laser ultrasound-interferometric system developed by the authors is applied to inspect solder joint quality during the thermal cycling tests. While the laser ultrasound inspection technique has been successfully applied to flip chips and chip scale packages, this study is the first application of this technique to overmolded packages. In this study, it is found out that the LGA packages can withstand 1000 temperature cycles without showing crack initiation or other failure mechanisms in the solder joints. The laser ultrasound inspection results match the visual observation and X-ray inspection results. This study demonstrates the feasibility of this system to solder joint quality inspection of overmolded packages. In particular, the devices constituting the objective of this study are radio frequency modules, which are encapsulated through overmolding and are mounted on a typical four-layer FR4 board through LGA terminations.

Lead-Free Solder Material and Chip Thickness Impact on Board-Level Reliability for Low-K WLCSP

This paper evaluates the effect of the solder ball material and chip thickness on board-level reliability using low-K wafer-level chip-scale packaging (WLCSP). The composition of the three evaluated solder ball materials includes SnAg <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1.0</sub> Cu <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</sub> , SnAg <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2.0</sub> Cu <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</sub> , and SnAg <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2.6</sub> Cu <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.6</sub> . The chip thickness is ranging from 200, 300, and 775 ¿m. Initially, the high temperature storage and ten-time multiple reflow tests were used as the wafer-level reliability test items. The work uses both the low speed (500 ¿m/s) and the high speed (200 mm/s and 1 m/s) solder ball shear test to compare the shear force, displacement, and fracture energy of the three solder compositions. The high speed shear test result shows the high silver content correlates to small displacement and the low fracture energy. Next, the finite element model was employed to compare the board level chip and solder ball stress for these three different chip thicknesses. The finite element method simulation results indicate the thinner chip implies the preferred thermal fatigue cycles. In addition, the drop test results show the chip thickness of 200 and 300 ¿m improve the drop test performance (81 drops and 88 drops) by 20.9%-31.34% than that of chip thickness of 775 ¿m. Moreover, the chip thickness of 200 and 300 ¿m substantially enhance the thermal fatigue life (665 cycles and 655 cycles) by 81.44%-84.21% than that of chip thickness of 775 ¿m using the SnAg <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1.0</sub> Cu <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</sub> . Notably, the experimental results correlate well with the simulation trend. This work provides a design guideline for selecting the favorable solder materials and the chip thickness to obtain the satisfactory board-level reliability of the low-K WLCSP packaging.

Advanced analysis on board trace reliability of WLCSP under drop impact

Through an aggressive product development program which includes experiment and simulation, Amkor has developed the next level of WLCSP (CSP nl™), a product which exhibits superior board level reliability when subjected to drop impact, a strong requirement for portable electronics. Failure mechanism of WLCSP under drop test has been established. Depending on type of WLCSP and test board design, three primary failure modes can be observed, i.e. copper (Cu) board trace crack, Cu RDL (redistribution layer) vertical crack and Cu/Under Bump Metallization (UBM) delamination. CSP nl can exhibit distinct failure modes under different test board and/or CSP nl designs, resulting in a vast difference in drop test lifetimes. The primary failure mode is shifted whenever the weakest link is removed through design improvement. This paper will focus on detailed analysis of copper board trace crack under drop test, using an integrated approach of testing, failure analysis, material characterization and modeling. Board design guidelines are formulated to understand the effects of I/O position, board trace routing direction, board trace width, tear drop design, PCB pad size, stack-up thickness, and alloy materials on board trace reliability. Comparison is also made on possible impact on Cu RDL reliability.

Drop Test Simulation for the Component-Level Reliability of Module Packages

The component-level drop reliability of micro-electronic packages has been a concern. Proper modeling approaches can significantly reduce the time and costs and provide valued data support not only on the failure analysis but also on product development. Based on finite element methods, the presented study performed explicit dynamic drop modeling to simulate the actual drop tests using ANSYS and LS-DYNA. A generic over-molded LGA (land grid array) module was selected and 3D parametric models were utilized to carry out the study. As in the actual drop test, the standard JEDEC test board and JEDEC drop condition were applied. The over-molded modules together with the test board under 1500G gravity was simulated to identify the failure locations. The results were fairly correlated to the actual FA observation. Potential key factors such as solder pad size, pitch size, module size, and thickness were studied through the parametric modeling. The impact of board side defect, such as solder void, was also studied because it is common to have this kind of defect in assembly. Besides component-level drop reliability, we also studied the board-level drop reliability by investigating the LGA solder stress.

Investigation on the failure criterion of reliability testing for Pb-free BGA packages

Daisy-chained test vehicles are commonly used in board level reliability testing. By continuously monitoring the in-situ daisy chain resistance change over time, a failure could be captured during cycling and eventually the failure data could be used to establish the solder joints failure distribution under different testing conditions. One of the most debatable matters is that when should one to determine a failure to occur. Per IPC 9701A [1] a failure is defined as 10 1000-ohm events in 1 micro-second duration for event detector or 20% increase over the baseline resistance for data logger. Other threshold values such as 100, 300, or 500 ohms are also commonly used by packaging reliability community. Such a wide range of failure threshold values may introduce significant delta in terms of cycle numbers for Pb-free solder joints if different criteria would be used as reported by Henshall, etc [2]. Therefore a systematic study of the impact of using such diversified resistance values on the final failure distribution is necessary and important such that no big difference among reliability results from different sources. The purpose of this study is to investigate the impact of different failure thresholds on Pb-free solder joint failure distribution for most commonly used packages. The test vehicle, designed on an 8″×15″ double-sided printed circuit board (PCB) with multiple test sites, was populated on both sides with daisy-chained components. To reflect the real situation, the components were selected to include different package types (FCBGA, PBGA, CSP, QFN, etc), different pitches (0.4–1.0 mm), and different package size (6–50mm). The assembled test vehicles then went through 0C–100C thermal cycling, the cycle numbers corresponding to different resistance thresholds were recorded and compared. The test results showed that the failure threshold has significant impact on Pb-free solder joint failure distribution, thus it is important to unify the failure criterion such that the reliability results from different sources could be compared side by side. For some packages especially small wire-bond packages that have relatively low baseline resistance, the 20% failure criterion may be too sensitive to the resistivity changes caused not by solder joint failure but other events such as connection cable resistivity change over time or temperature.

Electromigration Performance of WLPs with Standard and Polymer Core Balls

This talk will compare the electromigration performance of wafer level packages having standard SnAgCu solder with those having solder balls with polymer cores. Information on package construction, process, and board level reliability of packages having balls with polymer cores was presented earlier (2009 International Wafer Level Packaging Conference, San Jose, CA). In the new ball variation, the structure is made of a large solid polymer core, which is plated with a thin layer of copper and covered with a layer of SnAg. The polymer core within the solder ball ensures that the standoff height remains constant during board assembly, and acts as a stress absorption layer between the Si and the PCB during any thermal excursion and drop testing. Such characteristics allow extension of the wafer level package from small pin count (~30 I/O) to higher pin count (100+ I/O) without the need for redistribution layers. For electromigration, bump resistances were monitored continuously at different current densities and temperatures for the two package types. Equivalent performance was obtained. Similar failure modes were observed in both cases, with pancake-like void formation growing outward from the pad corners due to current crowding. Equivalent performance was obtained, with both packages exhibiting MTTF of 1200 hrs at 150C, and 550 hrs at 165C. Application to a modified Black's equation to predict MTTF and account for current crowding, heating, and stress will also be discussed.