Block Transfer Research Articles

Fine-resolution analysis of products of intrachromosomal homeologous recombination in mammalian cells.

Mouse Ltk- cell lines that contained a herpes simplex virus type 1 (HSV-1) thymidine kinase (tk) gene with a 16-bp insertion mutation linked to either a defective HSV-2 tk gene or a hybrid tk sequence comprised of HSV-1 and HSV-2 tk sequences were constructed. HSV-1 and HSV-2 tk genes have 81% nucleotide identity and hence are homeologous. Correction of the insertion mutant HSV-1 tk gene via recombination with the hybrid tk sequence required an exchange between homeologous tk sequences, although recombination could initiate within a region of significant sequence identity. Seven cell lines containing linked HSV-1 and HSV-1-HSV-2 hybrid tk sequences gave rise to tk+ segregants at an average rate of 10(-8) events per cell division. DNA sequencing revealed that each recombinant from these lines displayed an apparent gene conversion which involved an accurate transfer of an uninterrupted block of information between homeologous tk sequences. Conversion tract lengths ranged from 35 to >330 bp. In contrast, cell lines containing linked HSV-1 and HSV-2 tk sequences with no significant stretches of sequence identity had an overall rate of homeologous recombination of <10(-9). One such cell line produced homeologous recombinants at a rate of 10(-8). Strikingly, all homeologous recombinants from this latter cell line were due to crossovers between the HSV-1 and HSV-2 tk genes. Our results, which provide the first detailed analysis of homeologous recombination within a mammalian genome, suggest that rearrangements in mammalian genomes are regulated by the degree of sequence divergence located at the site of recombination initiation.

A CELT and MCST capable VME slave interface

We report on the development of a VME slave interface for the CLEO III detector implemented in an ALTERA EPM7256 CPLD. This includes the first implementation of the chained block transfer protocol (CELT) and multi-cast cycles (MCST) as defined by the VME-P task group of VIPA. Within VME64 there is no operation that guarantees efficient readout of large blocks of data that are sparsely distributed among a series of slave modules in a VME crate. This has led the VME-P task group of VIPA to specify protocols that enable a master to address many slaves at a single address. Which slave is to drive the data bus is determined by a token passing mechanism that uses the *IACKOUT, *IACKIN daisy chain. This protocol requires no special features from the master besides conformance to VME64. Non-standard features are restricted to the VME slave interface. The CLEO III detector comprises /spl sim/400,000 electronic channels that have to be digitized, sparsified, and stored within 20 /spl mu/s in order to incur less than 2% dead time at an anticipated trigger rate of 1000 Hz. 95% of these channels are accounted for by only two detector subsystems, the silicon microstrip detector (125,000 channels), and the ring imaging Cerenkov detector (RICH) (230,400 channels). The occupancy after sparsification in either of these two detector subsystems is expected to be less than 1%, resulting in event fragments on the order of 10 KBytes each, spread over 4, and 8 VME crates, respectively. We developed a chip set that sparsifies, tags, and stores the incoming digital data on the data boards, and includes a VME slave interface that implements MCST and CELT protocols. In this paper, we briefly describe this chip set and then discuss the VME slave interface in detail.

An introduction to FASTCAMAC (60 megabytes/sec in CAMAC?)

FASTCAMAC is a high speed block transfer protocol with data rates up to twenty times faster than normal CAMAC. FASTCAMAC is compatible with the CAMAC data acquisition standard. The new protocol is presented as a short tutorial for the data acquisition user. Emphasis is on FASTCAMAC as an extension to CAMAC with discussion of compatibility, performance and system aspects.

ATM block transfer capability vs. available bit rate service

AbstractATM Block Transfer is an ATM transfer capability, which has been standardized in the May 1996 version of ITU‐T Recommendation 1.371. Two transmission modes for ABT exist, namely the delayed and immediate transmission modes, giving rise to ABT/DT and ABT/IT, respectively, which can run in the elastic or rigid modes. The Available Bit Rate (ABR) service is an ATM layer service, which has been worked by the ATM Forum and specified in the UNI Spec. 4.0 voted in June 1996. The aim of this paper is to give the high level description of ABT and ABR and to draw attention to their common features and their differences. It turns out that the service offered by ABR is much more sophisticated but also more fragile than that offered by elastic ABT/DT. Since the implementation of ABR requires a deeper modification of the existing ATM switches and cross‐connects than elastic ABT/DT, an interworking scenario between these two capabilities, compatible with the cross‐connects used in the current ATM networks, is proposed.

Correction of severe foot deformity using the external ring fixateur. A case report

Summary The correction of neglected talipes equinus varus is a challenging problem. The dangers of soft tissue breakdown, and neurovascular damage, as well as unsatisfactory function, have widely been reported. A safe method with the use of a ring fixateur is presented, minimizing the risk of soft tissue or neurovascular damage. Prior to progressive correction by means of the ring fixateur, an anterolateral tarsectomy is performed. The correction is stabilized by a subtalar reorienting bone block arthrodesis and transfer of the anterior tibial tendon. A case of a 26-year-old patient with bilateral severe talipes equinus varus is reported.

The role of attention in automatization: does attention operate at encoding, or retrieval, or both?

In this research, we investigated whether attention operates in the encoding of automatized information, the retrieval of automatized information, or in both cases. Subjects searched two-word displays for members of a target category in focused-attention or divided-attention conditions that were crossed with block (training vs. transfer). To see whether subjects encoded all available items or only attended items, we compared performance for subjects in different training conditions but in the same transfer condition. Subjects encoded attended items. To see whether subjects retrieved all the items they had in memory, or only items associated with that to which they were attending at retrieval, we compared performance for subjects in the same training conditions but in different transfer conditions. Subjects retrieved attended items. Attention was found to operate at both encoding and retrieval. These findings support the instance theory of automaticity, which predicts the role of attention at encoding and retrieval.

The controlled cell transfer capability

A Controlled Cell Transfer (CCT) capability has been proposed to ITU for definition in Recommendation I.371. The CCT capability, if accepted, will bring the number of ATM transfer layer capabilities to five. The other four capabilities being Deterministic Bit Rate (DBR), Statistical Bit Rate (SBR), ATM Block Transfer (ABT) and Available Bit Rate (ABR). It is believed that this capability will endow the ATM network with LAN like service over the wide area. In this article, we discuss the features and mechanisms of the proposed CCT capability. We also discuss the applications that CCT is targeted at supporting and present results of simulation studies, highlighting the advantages of CCT.

An investigation of the friction and wear properties of nanometer Si 3N 4 filled PEEK

The nanometer Si 3N 4 filled polyetheretherketone (PEEK) composite blocks were prepared by compression molding. The friction and wear properties of nanometer Si 3N 4 filled PEEK were investigated on a block-on-ring machine by running the PEEK composite block against a plain carbon steel (AISI 1045 steel) ring. The morphologies of the wear traces and the transfer film were observed by scanning electron microscopy (SEM) and X-ray photoelectron spectroscopy (XPS). It was found that nanometer Si 3N 4 filled PEEK composite exhibits considerably lower frictional coefficient and wear rate than pure PEEK. Especially, the lowest wear rate is obtained with the composite containing 7.5 wt.% Si 3N 4. The SEM pictures of the wear traces indicate that with the frictional couple of carbon steel ring/composite block, a thin, uniform, and tenacious transfer film was formed on the ring surface, while XPS results show that Si 3N 4 was partly oxidized into SiO 2 during the rubbing process. Thus the improvement in the tribological behavior of nanometer Si 3N 4 filled PEEK composite is closely related to the improved characteristics of the transfer film.

A sixteen channel peak sensing ADC for singles spectra in the FERA format

To read out multi-element small X-ray detectors for X-ray fluorescence applications with synchrotron radiation one needs the capability to record multiple singles spectra for each detector element at high rates. We have developed a sixteen channel 11 bit peak sensing ADC in a CAMAC module. We use the FERA readout bus to place the data into a commercially available histogramming module developed to generate multiple histograms from FERA ADCs. The sixteen channels digitize shaped pulses from the detectors without external gating. The digitizing time is 8 /spl mu/sec, the peak acquisition time is /spl ges/2 /spl mu/sec. The module contains a LIFO to permit block transfers in order to minimize dead times associated with the readout. There is a common CAMAC controlled analog threshold for noise suppression and a 16 bit mask to enable or disable individual ADCs. Differential non linearity is less than +8%/-4%. A /spl gamma/-ray spectrum collected using this ADC is presented.

Coherent network interfaces for fine-grain communication

Historically, processor accesses to memory-mapped device registers have been marked uncachable to insure their visibility to the device. The ubiquity of snooping cache coherence, however, makes it possible for processors and devices to interact with cachable, coherent memory operations. Using coherence can improve performance by facilitating burst transfers of whole cache blocks and reducing control overheads (e.g., for polling).This paper begins an exploration of network interfaces (NIs) that use coherence---coherent network interfaces (CNIs)---to improve communication performance. We restrict this study to NI/CNIs that reside on coherent memory or I/O buses, to NI/CNIs that are much simpler than processors, and to the performance of fine-grain messaging from user process to user process.Our first contribution is to develop and optimize two mechanisms that CNIs use to communicate with processors. A cachable device register---derived from cachable control registers [39,40]---is a coherent, cachable block of memory used to transfer status, control, or data between a device and a processor. Cachable queues generalize cachable device registers from one cachable, coherent memory block to a contiguous region of cachable, coherent blocks managed as a circular queue.Our second contribution is a taxonomy and comparison of four CNIs with a more conventional NI. Microbenchmark results show that CNIs can improve the round-trip latency and achievable bandwidth of a small 64-byte message by 37% and 125% respectively on the memory bus and 74% and 123% respectively on a coherent I/O bus. Experiments with five macrobenchmarks show that CNIs can improve the performance by 17-53% on the memory bus and 30-88% on the I/O bus.

HOT BLOCK ELEVATION EFFECT ON MIXED CONVECTION IN A PARALLEL PLATE CHANNEL

Heat transfer is examined for channel flow of mixed convection between two parallel plates with two hot blocks within. The numerical method SIMPLE-C is used. The influence on flow field and heat transfer capacity with respect to elevations of two hat blocks is investigated. The elevations of and distance between hot blocks are varied in an attempt to understand their influence on mixed convection. The Reynolds, Richardson, and Prandtl numbers are also varied in order to study the influence on flow field and temperature distribution. It is observed that heat transfer capacity increases as the distance between two hot blocks increases. For different arrangements, to make heat transfer of the second hot block be independent of the first, the distance varies. However, such distances can be reduced dramatically with a staggered arrangement. The heat transfer capacity increases effectively with increasing Reynolds number. Heat transfer and flow type are greatly affected by various fluids.

Treatment with bone block transfer of coracoacromial ligment in acromioclayicular injury

Treatment with bone block transfer of coracoacromial ligment in acromioclayicular injury

Design and implementation of a scalable low-cost shared-memory multiprocessor system using IBM compatible PCs

The design and implementation of a low-cost shared-memory multiprocessor system using a number of 386 PCs connected through a common bus is presented. Throughout the design, emphasis is placed on using standard PC components, particularly for the microprocessors and the shared memory, which results in significantly lower prices, at the cost of using components not designed for this specific application. The cost of the entire add-on components to the system is only AUD $300 and this is further facilitated by the use of features already available in standard PC operating systems and programming environments. The system offers encouraging results for benchmark problems on block transfers and floating point matrix multiplication. An effort has also been made to include sufficient flexibility in the design to allow for future modifications and upgrades.

64 Mbit animation DRAM

An Animation DRAM (ARAM) is presented that meets the high bandwidth requirements of memory in computer games and animation. On-chip bit block transfer (bitBlt) units provide internal block data transfer to support scrolling background and sprite animation.

Identification and Transfer of Heterotic Chromosome Blocks for Forage Yield in Short‐Day Exotic Pearl Millet Landraces

Photoperiod sensitivity of pearl millet, Pennisetum glaucum (L.) R. Br., exotic accessions has limited their use in nontropical environmerits due to excess height and late maturity problems. Objectives of this research were (i) to describe and evaluate a modification of a direct method to screen non‐converted short‐day Burkina Faso landraces (BFL) of pearl millet for large heterosis‐creating beterotic chromosome blocks (HCBs) that can replace a small HCB in the male parent T383 of the top producing F1 hybrid Tifleaf 2 and to increase its forage yield; and (ii) to determine the variation in the size of HCBs in a single landrace. Short early T383‐1ike F2 plants in (BFL × T383) F2 populations were screened for HCBs by crossing them with T23Rp1, which carries the red marker gene, crossing those F1s on T85A {cytoplasmic male sterile (cms) green 23], growing 100 spaced plants of the cross T85 × (BFL × T383) F2, cutting and weighing 50 of the red and 50 of the green plants in each population, and analyzing the data with the SAS General Linear Model. Percent heterosis for plant forage yield in 100‐plant populations of each cross ranged from 0 to 51%. The average HCB heterosis for T383 was 4%. Sister plants within a single BFL were variable enough to make it important to cross a single BFL plant with T23Rp1 to measure HCB beterosis and with T265 (T383Rp1 to start the transfer of the top HCB to T383. The modification method requires an extra year before measuring HCBs, but requires a less variable 100‐plant screening population and should require fewer backcrosses to transfer the top HCB to T383.

Empirical evaluation of the CRAY-T3D

Most recent MPP systems employ a fast microprocessor surrounded by a shell of communication and synchronization logic. The CRAY-T3D provides an elaborate shell to support global-memory access, prefetch, atomic operations, barriers, and block transfers. We provide a detailed empirical performance characterization of these primitives using micro-benchmarks and evaluate their utility in compiling for a parallel language. We have found that the raw performance of the machine is quite impressive and the most effective forms of communication are prefetch and write. Other shell provisions, such as the bulk transfer engine and the external Annex register set, are cumbersome and of little use. By evaluating the system in the context of a language implementation, we shed light on important trade-offs and pitfalls in the machine architecture.

The performance advantages of integrating block data transfer in cache-coherent multiprocessors

Integrating support for block data transfer has become an important emphasis in recent cache-coherent shared address space multiprocessors. This paper examines the potential performance benefits of adding this support. A set of ambitious hardware mechanisms is used to study performance gains in five important scientific computations that appear to be good candidates for using block transfer. Our conclusion is that the benefits of block transfer are not substantial for hardware cache-coherent multiprocessors. The main reasons for this are (i) the relatively modest fraction of time applications spend in communication amenable to block transfer, (ii) the difficulty of finding enough independent computation to overlap with the communication latency that remains after block transfer, and (iii) long cache lines often capture many of the benefits of block transfer in efficient cache-coherent machines. In the cases where block transfer improves performance, prefetching can often provide comparable, if not superior, performance benefits. We also examine the impact of varying important communication parameters and processor speed on the effectiveness of block transfer, and comment on useful features that a block transfer facility should support for real applications.

The performance advantages of integrating block data transfer in cache-coherent multiprocessors

Integrating support for block data transfer has become an important emphasis in recent cache-coherent shared address space multiprocessors. This paper examines the potential performance benefits of adding this support. A set of ambitious hardware mechanisms is used to study performance gains in five important scientific computations that appear to be good candidates for using block transfer. Our conclusion is that the benefits of block transfer are not substantial for hardware cache-coherent multiprocessors. The main reasons for this are (i) the relatively modest fraction of time applications spend in communication amenable to block transfer, (ii) the difficulty of finding enough independent computation to overlap with the communication latency that remains after block transfer, and (iii) long cache lines often capture many of the benefits of block transfer in efficient cache-coherent machines. In the cases where block transfer improves performance, prefetching can often provide comparable, if not superior, performance benefits. We also examine the impact of varying important communication parameters and processor speed on the effectiveness of block transfer, and comment on useful features that a block transfer facility should support for real applications.

Optimal communication channel utilization for matrix transposition and related permutations on binary cubes

We present optimal schedules for permutations in which each node sends one or several unique messages to every other node. With concurrent communication on all channels of every node in binary cube networks, the number of element transfers in sequence for K elements per node is K 2 , irrespective of the number of nodes over which the data set is distributed. For a succession of s permutations within disjoint subcubes of d dimensions each, our schedules yield min ( K 2 +(s−1)d,(s+3)d, K 2 +2d) exchanges in sequence. The algorithms can be organized to avoid indirect addressing in the internode data exchanges, a property that increases the performance on some architectures. For message-passing communication libraries, we present a blocking procedure that minimizes the number of block transfers while preserving the utilization of the communication channels. For schedules with optimal channel utilization, the number of block transfers for a binary d-cube is d. The maximum block size for K elements per node is ⌈ K (2d) ⌉.

Computing with pipelined block transfer

A sequential model of computation (PBTf) with memory latency and pipelined access is described.PBTf has f(x) access time to location x. In the following time units the subsequent locations x+1, x+2, ... can be accessed, and the contents of cells x, x+1, x+2, ... moved to another block of memory. Pipelined requests to the memory are also allowed. Several problems are analysed inPBTf, and their complexities discussed.