Block Transfer Research Articles

Beyond 320 Mbyte/s With 2eSST and Bus Invert Coding on VME64x

The VME64x standard includes a double data rate block transfer cycle known as 2eSST. In order to achieve the maximum bandwidth, 64-bit words are exchanged in bursts across the backplane without handshake between master and slave. Data is clocked by both the falling and rising edges of a single strobe line driven by the data producer. Transfer rates up to 320 Mbyte/s are presently supported: the standard also foresees even faster speed grades, to be released in the future. In this paper we present our tests on 2eSST beyond the actual limit set by the protocol. Bit error rate (BER), data timing jitter and eye-diagrams have been measured for selected bus layouts and data patterns. Performance achieved with and without the bus-Invert encoding of the transmitted payloads are compared. Our results show that on a 21 slot VME64x backplane reliable transfers can be sustained with selected loads up to 800 MByte/s with a 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> BER .

Bus-Invert Coding for Low Noise, Low Power 2eSST VME64x Block Transfers

The VME64x standard defines a double edge source synchronous block transfer (2eSST) capable to sustain a data transfer rate up to 320 MByte/s on the VMEbus. This level of performance is achieved by double edge clocking a 64-bit bus with bursts of data strobe pulses. The switching activity of such a wide bus on a shared backplane challenges the signal integrity and the data transfer reliability. The Bus-invert is a well known coding technique developed to lower the peak power dissipation in I/O busses by decreasing their switching activity. It has been originally proposed for lowering the power consumption of CMOS VLSI devices and so reducing the on-chip line coupling and noise. In this paper we discuss how the Bus-Invert coding can be applied to improve the 2eSST performance. A custom designed board-set has been used to characterize jitter, noise and power consumption with different data patterns, coding schemes and bus loading conditions. The hardware overheads introduced by the encoding algorithm is discussed in the view of deployments in low-latency, real-time applications.

A NOVEL PROTECTION SCHEME FOR RING TYPE DISTRIBUTION SYSTEMS

This paper proposes a novel protection scheme for ring type distribution systems. Using an intelligent electronic device (IED) equipped with a dedicated communication channel and programmable logic controller (PLC) makes this configuration more feasible. Not only the main protections are presented, but also the backup protections are well introduced in detail whenever the system configuration is ring or radial. This investigation discusses pilot relaying systems, mainly including the permissive overreaching transfer trip (POTT), the directional comparison blocking (DCB) and direct transfer trip (DTT) schemes. Meanwhile, the hierarchical protection scheme of ring type distribution system is adopted in the primary feeder system. This work demonstrates that the proposed protection scheme is extremely well designed so that both the numbers and the durations of interruptions caused by the faults can be minimized. Especially, the most significant advantage of this system is that the service is not interrupted when a fault occurs on the feeder. Based on the above-mentioned novel protection scheme, a trade-off is also made between the dependability and the security of protection system, particularly considering the communication channel conditions. The evaluations of the performances of ring type distribution systems are also described.

Dynamic modelling of multistage feedback-control manufacturing systems

The manufacturing systems operating within today's global enterprises are invariably dynamic and complicated. To stay competitive in this 21st century global industrialisation, companies must possess a new control strategy to design manufacturing systems to rapidly respond to demand changes as well as to launch new products efficiently. In this paper, a novel method to model multistage feedback control manufacturing systems is demonstrated using the Block Diagram (BD) representation and Transfer Functions (TFs) of control theory. The task of translating causal loop diagrams and stock-and-flow diagrams from system dynamics into BD and TF mathematical descriptions will be discussed in detail. Transient-response system parameters such as undamped natural frequency and damping ratio are introduced to determine other key dynamic system characteristics of multistage feedback-control manufacturing systems.

An Optimal Cache‐Oblivious Priority Queue and Its Application to Graph Algorithms

We develop an optimal cache-oblivious priority queue data structure, supporting insertion, deletion, and delete-min operations in $O(\frac{1}{B}\log_{M/B}\frac{N}{B})$ amortized memory transfers, where $M$ and $B$ are the memory and block transfer sizes of any two consecutive levels of a multilevel memory hierarchy. In a cache-oblivious data structure, $M$ and $B$ are not used in the description of the structure. Our structure is as efficient as several previously developed external memory (cache-aware) priority queue data structures, which all rely crucially on knowledge about $M$ and $B$. Priority queues are a critical component in many of the best known external memory graph algorithms, and using our cache-oblivious priority queue we develop several cache-oblivious graph algorithms.

ROM to DSP block transfer for resource constrained synthesis

Modern field programmable gate array (FPGA) architectures are moving towards heterogeneity with the increasing inclusion of coarse grained elements such as embedded multipliers and RAMs. This has given rise to a multi-dimensioned resource-based measure of design area, very different from the traditional application-specific integrated circuit figure of silicon area. In order for a designer to use these heterogenous elements in their design, they must usually specifically instantiate them. Heterogeneous elements not used in a design remain unused on the device, consuming leakage power, silicon area and manufacturing costs. Method of transferring functionality normally implemented in embedded ROMs and 4-input look-up tables (4-LUTs) onto unused digital signal processor (DSP) blocks is proposed. The paper proceeds to include this method in a synthesis system incorporating the idea of resource constrained synthesis, where a design is mapped to an FPGA considering user and device constraints on heterogenous element usage, based on an extension to the Altera Quartus II synthesis software. Results have been obtained, showing an improvement over existing methods in 76% of the 21 ROMs examined. Further results have been obtained from applying this approach with the synthesis system to benchmark algorithms. In the designs examined, the number of possible implementations has increased by two to four times over Altera Quartus.

Queueing models of RAID systems with maxima of waiting times

A queueing model is developed that approximates the effect of synchronizations at parallel service completion instants. Exact results are first obtained for the maxima of independent exponential random variables with arbitrary parameters, and this is followed by a corresponding approximation for general random variables, which reduces to the exact result in the exponential case. This approximation is then used in a queueing model of RAID (Redundant Array of Independent Disks) systems, in which accesses to multiple disks occur concurrently and complete only when every disk involved has completed. We consider the two most common RAID variants, RAID0-1 and RAID5, as well as a multi-RAID system in which they coexist. This can be used to model adaptive multi-level RAID systems in which the RAID level appropriate to an application is selected dynamically. The random variables whose maximum has to be computed in these applications are disk response times, which are modelled by the waiting times in M / G / 1 queues. To compute the mean value of their maximum requires the second moment of queueing time and we obtain this in terms of the third moment of disk service time, itself a function of seek time, rotational latency and block transfer time. Sub-models for these quantities are investigated and calibrated individually in detail. Validation against a hardware simulator shows good agreement at all traffic intensity levels, including the threshold for practical operation above which performance deteriorates sharply.

Signal integrity and timing issues of VME64x double edge cycles

The double-edge source synchronous block transfer (2eSST) is the latest performance update to the VME64 protocol, approved as an ANSI standard in 2003. This extension has taken the VME's data transfer rate from the original 40 MByte/s to 320 MByte/s. The architectural turning at the base of such an impressive step forward is two-fold. Different from all the previous cycles, data transfers are driven synchronously by the producer, without handshaking, and data is latched on both the rising and falling edges of the strobe signal. The double edge clocking effectively doubles the bandwidth and it is normally present on PC motherboards equipped with double data rate RAM chips and high-performance graphic adapters. In these applications, a careful approach to signal integrity has shown to be critical in order to avoid timing violations. In parallel, multidrop bus architecture with long lines and up to 21 slots, these concerns become imperative for successful operations. In this paper we present the tests performed on 2eSST. The Motorola MVME6100 and a custom designed board have been used to characterize the timing with different bus loading conditions and to evaluate the impact of different layout choices. Driving capability and crosstalk immunity of enhanced transceivers specifically developed for 2eSST and traditional components are eventually compared

Biosynthesis of the N-Linked Glycan inCampylobacter jejuniand Addition onto Protein through Block Transfer

In eukaryotes, N-linked protein glycosylation is a universal modification involving addition of preformed oligosaccharides to select Asn-Xaa-Ser/Thr motifs and influencing multiple biological events. We recently demonstrated that Campylobacter jejuni is the first member of the Bacteria to possess an N-linked glycan pathway. In this study, high-resolution magic angle spinning nuclear magnetic resonance (HR-MAS NMR) was applied to probe and quantitate C. jejuni N-glycan biosynthesis in vivo. To confirm HR-MAS NMR findings, glycosylation mutants were screened for chicken colonization potential, and glycoproteins were examined by mass spectrometry and lectin blotting. Consistent with the mechanism in eukaryotes, the combined data indicate that bacterial glycans are assembled en bloc, emphasizing the evolutionary conservation of protein N glycosylation. We also show that under the conditions examined, PglG plays no role in glycan biosynthesis, PglI is the glucosyltransferase and the putative ABC transporter, and WlaB (renamed PglK) is required for glycan assembly. These studies underpin the mechanism of N-linked protein glycosylation in Bacteria and provide a simple model system for investigating protein glycosylation and for exploitation in glycoengineering.

Iliac Graft Vascularization for Femoral Head Osteonecrosis

We determined the long-term clinical and radiologic outcomes of patients with osteonecrosis treated with a combination of autologous cancellous bone impaction and pedicled iliac bone block transfer perfused by the ascending branch of the lateral femoral circumflex artery. We retrospectively reviewed 197 patients (226 hips) operated on from 1985-1998 who had a mean age of 38 years (range, 19-65 years) and an average followup of 12.5 years (range, 6-19 years). Fourteen hips (13 patients) (6%) had conversion to a total hip arthroplasty because of progressive collapse, severe pain, or both. Of the remaining 212 reconstructions, 195 hips were clinically successful (92%), and 76% were radiographically successful. The postoperative Harris hip score substantially improved in the patients without hip failure. Successful results were achieved in 96% of the patients with Ficat and Arlet Stage II osteonecrosis, 90% with Stage III osteonecrosis, and 57% with Stage IV osteonecrosis. Good results were obtained in 94% of the patients younger than 45 years. Our data suggest the method is useful for treating osteonecrosis of the femoral head only in active symptomatic patients with good integrity of hip cartilage and Stages II or III osteonecrosis. Therapeutic study, Level IV (case series). See the Guidelines for Authors for a complete description of levels of evidence.

The design of VMEbus bridge controller with SHARC bus

Targeting at the high expense and inflexibility to realize VMEbus bridge controller by professional Integrated Circuit (IC), this paper presents a scheme of adopting CPLD/FPGA (Complicated Programmable Logic Device/Field Programmable Gate Array) to design bridge controller between VMEbus and local bus. SHARC DSP (Digital Signal Processor) bus is an example. It has functions of nearly entire master/slave interface of VMEbus, and can act as DMA (Direct Memory Access) controller and perform block transfer in DMA or master processor initiative way without length limit. External circuit of the design is very simple. In comparison with special ICs, it has high performance to price ratio and can be easily applied to local buses of other processors with quite a little modification.

A 96-channel FPGA-based Time-to-Digital Converter (TDC) and fast trigger processor module with multi-hit capability and pipeline

We describe an field-programmable gate arrays based (FPGA), 96-channel, Time-to-Digital converter (TDC) and trigger logic board intended for use with the Central Outer Tracker (COT) [T. Affolder et al., Nucl. Instr. and Meth. A 526 (2004) 249] in the CDF Experiment [The CDF-II detector is described in the CDF Technical Design Report (TDR), FERMILAB-Pub-96/390-E. The TDC described here is intended as a further upgrade beyond that described in the TDR] at the Fermilab Tevatron. The COT system is digitized and read out by 315 TDC cards, each serving 96 wires of the chamber. The TDC is physically configured as a 9U VME card. The functionality is almost entirely programmed in firmware in two Altera Stratix FPGAs. The special capabilities of this device are the availability of 840 MHz LVDS inputs, multiple phase-locked clock modules, and abundant memory. The TDC system operates with an input resolution of 1.2 ns, a minimum input pulse width of 4.8 ns and a minimum separation of 4.8 ns between pulses. Each input can accept up to 7 hits per collision. The time-to-digital conversion is done by first sampling each of the 96 inputs in 1.2-ns bins and filling a circular memory; the memory addresses of logical transitions (edges) in the input data are then translated into the time of arrival and width of the COT pulses. Memory pipelines with a depth of 5.5 μ s allow deadtime-less operation in the first-level trigger; the data are multiple-buffered to diminish deadtime in the second-level trigger. The complete process of edge-detection and filling of buffers for readout takes 12 μ s . The TDC VME interface allows a 64-bit Chain Block Transfer of multiple boards in a crate with transfer-rates up to 47 Mbytes/s. The TDC module also produces prompt trigger data every Tevatron crossing via a deadtimeless fast logic path that can be easily reprogrammed. The trigger bits are clocked onto the P3 VME backplane connector with a 22-ns clock for transmission to the trigger. The full TDC design and multi-card test results are described. There is no measurable cross-talk between channels; linearity is limited by the least-count time bin. The physical simplicity ensures low-maintenance; the functionality being in firmware allows reprogramming for other applications.

Translating submachine locality into locality of reference

In this work, we show that the submachine locality exposed by hierarchical bulk-synchronous computations can be efficiently turned into locality of reference on arbitrarily deep hierarchies. Specifically, we develop efficient schemes to simulate parallel programs written for the Decomposable BSP (a BSP variant which features a hierarchical decomposition into submachines) on the sequential Hierarchical Memory Model (HMM), which rewards the exploitation of temporal locality, and on its extension with block transfer, the BT model, which also rewards the exploitation of spatial locality. The simulations yield good hierarchy-conscious sequential algorithms from parallel ones, and provide evidence of the strict relation between submachine locality in parallel computation and locality of reference in the hierarchical memory setting. We also devise a generalization of the HMM result to the self-simulation of D-BSP augmented with hierarchical memory modules, which yields an interesting analog of Brent's lemma, thus proving that the enhanced model features a seamless integration of memory and network hierarchies.

Calibration of a Queueing Model of RAID Systems

A recent queueing-based modelling methodology of RAID systems compared the mean disk access times of the two most common variants, RAID0-1 and RAID5, as well as a multi-RAID system in which they coexist. Accesses to multiple disks occur concurrently for each logical (user) request and complete only when every disk involved has completed. The models therefore needed to estimate the mean value of the maximum of the individual disk response times, each of which is modelled by the waiting time of an M/G/1 queue. This mean-max value was approximated in terms of the second moment of queueing time which in turn required the third moment of disk service time, itself a function of seek time, rotational latency and block transfer time. To achieve consistently good agreement with an event-driven simulator of the physical hardware and system software requires careful calibration of the resulting model's parameters and validation of its assumptions. This calibration and validation process involves detailed analysis of sub-models to reveal the restrictions necessary on the domain of real-world operating parameters that facilitate a viable predictive model. The process yields significant insight into several of the abstract subsystems involved that may be utilised in a range of practical modelling studies; for example, the effect of approximating a bank of parallel queues with synchronised arrivals by a bank of identical, independent queues. The final comparison against the hardware simulator shows excellent agreement, far surpassing that of the original model.

Ultrasound-Microbubble-Mediated Gene Transfer of Inducible Smad7 Blocks Transforming Growth Factor-β Signaling and Fibrosis in Rat Remnant Kidney

Transforming growth factor (TGF)-beta1 has been shown to play a critical role in hypertensive nephropathy. We hypothesized that blocking TGF-beta1 signaling could attenuate renal fibrosis in a rat model of remnant kidney disease. Groups of six rats were subjected to 5/6 nephrectomy and received renal arterial injection of a doxycycline-regulated Smad7 gene or control empty vector using an ultrasound-microbubble-mediated system. Smad7 transgene expression within the kidney was tightly controlled by the addition of doxycycline in the daily drinking water. All animals were euthanized at week 4 for renal functional and histological examination. Hypertension of equivalent magnitude (190 to 200 mmHg) developed in both Smad7- and empty vector-treated rats. However, treatment with Smad7 substantially inhibited Smad2/3 activation and prevented progressive renal injury by inhibiting the rise of 24-hour proteinuria (P < 0.001) and serum creatinine (P < 0.001), preserving creatinine clearance (P < 0.05), and attenuating renal fibrosis and vascular sclerosis such as collagen I and III expression (P < 0.01) and myofibroblast accumulation (P < 0.001). In conclusion, TGF-beta/Smad signaling plays a critical role in renal fibrosis in a rat remnant kidney model. The ability of Smad7 to block Smad2/3 activation and attenuate renal and vascular sclerosis demonstrates that ultrasound-mediated Smad7 gene therapy may be a useful therapeutic strategy for the prevention of renal fibrosis in association with hypertension.

Pressure Drop and Heat Transfer of a Rectangular Block on the Wall of Parallel Plates Channel (Effect of the Opening Ratio)

Pressure Drop and Heat Transfer of a Rectangular Block on the Wall of Parallel Plates Channel (Effect of the Opening Ratio)

0692 Passive transfer of conduction block and demyelination by sera from chronic inflammatory demyelinating polyradiculoneuropathy patients

0692 Passive transfer of conduction block and demyelination by sera from chronic inflammatory demyelinating polyradiculoneuropathy patients

Mixed Convection Cooling of Heat Sources Mounted with Porous Blocks

A numerical study is performed to analyze laminar mixed convection in a parallel-plate vertical channel with discrete strip heat sources on one channel wall. The effect on heat transfer of a porous block mounted above each heat source is considered. The Brinkman‐Forchheimer‐Extended Darcy model with the Boussinesq approximation is used to characterize the flowfield inside the porous region. Solution of the coupled governing equations for the porous/fluid composite system is obtained by utilizing a control volume method through the use of a stream function‐ vorticity approach. The characteristics of fluid flow and mixed convection heat transfer have been obtained by the examination of various governing parameters such as the Darcy number, Reynolds number, inertia parameter, Grashof number, conductivity ratio, and geometric parameter. The results indicate that the size and strength of recirculating flow induced by the porous block make significant changes in the cooling of strip heater, especially at both trailing and leading edges of heaters. In addition, it is shown that specific choices in porous block shape, permeability, and thermal conductivity can produce profound effects on the flow and heat transfer characteristics.

Performance evaluation of new scheduling methods for the RR/RR CICQ switch

Increasing link speeds and port counts in packet switches demand that methods for minimizing internal speed-up and implementing fast scheduling be developed. Combined input and cross point queued (CICQ) switches with round-robin (RR) polling of virtual output queues (VOQ) and of cross point buffers can natively forward variable-length packets without a required internal segmentation into cells. However, native switching of variable-length packets results in unfairness between ports. To eliminate this unfairness, we propose a block transfer mechanism that transfers up to a predefined number of bytes of packet data from a selected VOQ. This mechanism does not require internal speed-up. We also propose an overlapped RR (ORR) arbiter design that fully overlaps RR polling and scheduling. Using simulation and both synthetic and traced packet traffic as input, we show that the RR/RR CICQ switch with the block transfer mechanism has a lower delay than an input queued (IQ) switch that internally uses cells. We also show that the ORR arbiter is scalable, work conserving, and fair.

A locality-preserving cache-oblivious dynamic dictionary

This paper presents a simple dictionary structure designed for a hierarchical memory. The proposed data structure is cache-oblivious and locality-preserving. A cache-oblivious data structure has memory performance optimized for all levels of the memory hierarchy even though it has no memory-hierarchy-specific parameterization. A locality-preserving dictionary maintains elements of similar key values stored close together for fast access to ranges of data with consecutive keys. The data structure presented here is a simplification of the cache-oblivious B-tree of Bender, Demaine, and Farach-Colton. The structure supports search operations on N data items using O(log B N+1) block transfers at a level of the memory hierarchy with block size B. Insertion and deletion operations use O(log B N+log 2 N/ B+1) amortized block transfers. Finally, the data structure returns all k data items in a given search range using O(log B N+ k/ B+1) block transfers. This data structure was implemented and its performance was evaluated on a simulated memory hierarchy. This paper presents the results of this simulation for various combinations of block and memory sizes.