Block Floating-point Arithmetic Research Articles

Limit cycles elimination in delta-operator systems

The existence of nonzero equilibria in /spl delta/-operator fixed point and block floating point (BFP) systems is investigated and methods for avoiding such equilibria are proposed. In the fixed point case these methods work by mapping the region in which nonzero equilibria may appear to zero. This is possible if the region is small. It is also shown that nonzero equilibria and limit cycles of any period can always be avoided by using BFP arithmetic with a sufficiently large mantissa wordlength.

Realization of block floating-point digital filters and application to block implementations

Realization issues of block floating-point (BFP) filters such as complexity, roundoff noise, and absence of limit cycles are analyzed. Several new results are established. Under certain conditions, BFP filters perform better than fixed-point filters at the expense of a slight increase in complexity; convex programming can be used to minimize the roundoff noise; limit cycles will not be present if the underlying fixed-point system is free of quantization limit cycles. It is shown that BFP arithmetic can be efficiently combined with block implementations to further improve the roundoff noise and stability of the implementation and reduce the complexity of processing BFP data.

A limit cycle suppressing arithmetic format for digital filters

In this paper it is be shown that any digital filter with a stable transfer function can be implemented free of limit cycles, if block floating point arithmetic is used in conjunction with the so-called exponent saturation and flush-to-zero option. A certain system dependent minimum block mantissa length is required. Limit cycle suppression is achievable regardless of the structure and the quantization format. This format is simple to implement even on fixed point processors and offers high dynamic range.

An accurate error analysis model for fast Fourier transform

An error propagation model is proposed for the in-place decimation-in-time version of the radix-2 FFT algorithm. With the model, an accurate error expression and error variance for the computation of FFT are derived. This correspondence deals with fixed-point and block floating-point arithmetic. Simulation results agree closely with the theoretical predicted ones. We find that some roundoff errors at different stages correlate with each other. The density of correlations is closely associated with the round-off approach used in butterfly calculations.

Block floating-point implementation of digital filters using the DSP56000

The advantage of using block floating-point arithmetic as an alternative to fixed and floating-point arithmetic in the implementation of digital filters is considered. The block floating-point implementation of a second-order biquad digital filter structure using the Motorola DSP56000 fixed-point digital signal processor is described.

A new approach for block floating-point arithmetic in recursive filters

An approach to block floating-point arithmetic in recursive second-order direct form digital filters is proposed. Used in conjunction with residue (or error) feedback, the method gives improved scaling and roundoff noise properties compared to an earlier approach [2]. It is conjectured from extensive simulation studies that the proposed secondorder structure is free from finite wordlength oscillations of all types.

Block floating-point distributed filters

Distributed filters have been shown to offer an impressive complexity-throughput tradeoff. In this correspondence, a precision improvement is made in distributed filtering using block floating-point arithmetic. Performance improvement is predicted and verified using numerical experimentation. Using this scheme, additional distributed filter precision can be obtained.