Tag Bits Research Articles

Modeling of functional language interpreter with metaprogramming

The purpose of the research consists of modeling an interpreter for a functional programming language with metaprogramming capabilities and analyzing ways to implement primitive operators based on macros.Methods. A formal model of a functional language interpreter, which is a subset of Common Lisp, was developed with denotational semantics, which allows you to accurately describe the behavior of the interpreter when calculating language elements such as quoting, accessing variables, sequence of actions, branching, assignment, abstraction, application.Results. Based on denotational semantics, the architecture of a functional language interpreter with metaprogramming capabilities was developed. Numbers, symbols, pairs, strings and arrays were chosen as the basic types of objects. To store objects, a tag architecture was used, where the low-order bits of the object address are always zero, so they can store the object type code and the tag bit. Objects are allocated and freed automatically: a mark and cleanup algorithm is used for garbage collection. Using macros, branching operators, complete and incomplete, selection operator, and block operators of related variables were implemented. Conclusion. As a result of the work, a functional language interpreter with metaprogramming capabilities was implemented. Using macros, primitive operators of condition, selection, and a block of related variables were implemented. Using these operators as an example, it is shown that using metaprogramming, only basic forms and primitives can be built into the interpreter, and the other operators can be implemented using metaprogramming, which makes it possible to simplify and reduce the amount of interpreter code.

Enhancing Power Efficiency in Branch Target Buffer Design with a Two-Level Prediction Mechanism

Modern processors often face challenges when handling instructions that overwhelm the branch target buffer (BTB), leading to front-end bottlenecks. As the BTB’s capacity increases, its prediction module can become slower and power-hungry. In this paper, we introduce a straightforward yet highly effective two-level prediction mechanism to mitigate the escalating power consumption in the BTB structure, achieved by reducing the number of accesses. Our approach incorporates two main elements: M-BTB and V-BTB. M-BTB encompasses the first-level prediction mechanism and a fully associative BTB, while V-BTB houses the second-level prediction mechanism and a set-associative BTB. To implement our prediction mechanism, we optimize the traditional two-level BTB structure. The first level employs the skew mechanism, and the second level dissects the tag bits to create the Partial tag. These two levels of prediction mechanism correspond to the bank/way prediction for the two-level BTB structure. Our experimental results show that the first-stage prediction mechanism reduces M-BTB accesses by 75%, while the second-stage prediction mechanism ensures that over 98% of addresses require just zero or one way of the V-BTB to achieve a hit result. Our proposed approach achieves a remarkable 86–97% reduction in power consumption, with a minimal impact on performance and an increase in overall area efficiency.

A Methodology to Capture Fine-Grained Internal Visibility During Multisession Silicon Debug

Silicon debugging is carried out in multiple sessions which are characterized by run-and-halt intervals. One of the important criteria for the success of this method is that the debugging infrastructure should capture only the erroneous data which can add important insights to the debugging process. However, identification of such suspect clock cycles is not a trivial exercise and requires an systematic approach. We propose a debugging architecture for enhancing the multisession procedure using the technique of on-chip debug data compression. The first session assists in identifying those erroneous clock cycles, and the useful debug data are collected in the second session with the help of markers called tag bits. At the cost of a minimal increase in area overhead, the proposed architecture achieves finer temporal visibility expansion because of the debug data collection in a segregated manner. During the offline analysis of the collected debug data, error localization can be achieved to a finer resolution. We evaluate our methodology on several designs for different kinds of error configurations. Experimental results show that the proposed methodology can achieve better on-chip storage utilization and the expansion in the temporal observation window compared to similar techniques in the literature.

A Low-Overhead Encoding Scheme to Extend the Lifetime of Nonvolatile Memories

Emerging nonvolatile memories (NVMs) are promising to replace DRAM as main memory. However, NVMs suffer from limited write endurance and high write energy. Encoding method reduces the bit flips of NVMs by exploiting additional tag bits to encode the data. The effect of the encoding method is limited by the capacity overhead of the tag bits. In this article, we propose to exploit the space saved by compression to store the tag bits of the encoding method. We observe that the saved space size of each compressed cache line varies, and different encoding methods have different tradeoffs between capacity overhead and effect. To fully exploit the space saved by compression for improving lifetime, we select the proper encoding method according to the saved space size. To improve the compression coverage and compression ratio, we select an efficient compression scheme from two compression algorithms and provide more space for data encoding. Still, some data patterns cannot be compressed by any compression technique. We use the Flip-N-Write with 3.1% capacity overhead to encode uncompressible cache lines. The experimental results show that our scheme reduces the bit flips by 32.5%, decreases the energy consumption by 22.6% and improves the lifetime by 69.9% with 3.5% capacity overhead.

Scrabble: A Fine-Grained Cache with Adaptive Merged Block

A large fraction of the microprocessor energy is consumed by the data movement in the system. One of the reasons is the inefficiency in the conventional cache design. Cache blocks larger than a word are used in conventional caches to exploit spatial locality. However, many applications only use a small part of a cache block before its eviction. Transferring and storing unused data wastes bandwidth, energy, and limited cache space. Prior work on fine-grained caches can reduce data access and storage granularity to reduce the amount of unused data. However, small data blocks typically require greater metadata and control overhead. Sharing the common bits among tags of fine-grained blocks can reduce the metadata overhead but the constraints on which fine-grained blocks can share tag bits can cause fragmentation. This work proposes scrabble, a fine-grained cache that can merge multiple non-contiguous fine-grained blocks into a variable size merged block. The length of the shared tag is maximized to reduce the metadata overhead. The space utilization is improved by supporting merged blocks with variable size. The control overhead can be reduced by moving the merged block together from memory to the last level cache. For applications with poor spatial locality, Scrabble cache can achieve more than 40 percent of performance improvement. Even for application with good spatial locality, the speedup is still more than 7 percent. In general, for an evaluated set of benchmarks, Scrabble cache achieves an average of 2.41× effective capacity over the baseline cache with the same cache capacity which leads to a 16.7 percent performance improvement and an 11 percent on-chip energy reduction. As compared to a state-of-the-art fine-grained cache, Scrabble cache achieves a 1.25× effective capacity, a 7.9 percent speedup, and a 5.8 percent on-chip energy reduction.

Scalable Intelligent Systems by 2025

Reusable Scalable Intelligent Systems (RSIS) have the following characteristics: • Interactively acquire information from video, Web pages, hologlasses (electronic glasses with holographic-like overlays), online data bases, sensors, articles, human speech and gestures, etc. • Real-time integration of massive pervasively inconsistent information • Self-informative in the sense of knowing its own goals, plans, history, provenance of its information and having some information about its own strengths and weaknesses. • Close human interaction using hologlasses (electronic glasses with holographic-like overlays) for secure mobile communication. Computers alone cannot implement the above capabilities. • No closed-form algorithmic solution is possible to implement the above capabilities • Reusability so that advances in one area can readily be used elsewhere without having to start over from scratch • Scalability in all important dimensions meaning that there are no hard barriers to continual improvement in the above areas, i.e., system performance continually significantly improves. A large project (analogous to Manhattan and Apollo) is required to meet strategic challenges for Intelligent Systems and S5G (Secure 5G). Inconsistent and incoherence are the natural result of the enormous amount of information necessary for the operation of a Reusable Scalable Intelligent System. For any empirical proposition, there typically can be inconsistent information. Consequently, possibly inconsistent information is the default. Hologlasses are electronic glasses that provide holographic-like overlays, which will be used for just about everything including the following: driving (vehicle detection, traffic sign recognition, obstacle avoidance, navigation), warfare (navigation, reconnaissance, hazard avoidance, command and control), exercising ( navigation, timing, goals, repetition counting, advice), walking (obstacle avoidance, navigation, oncoming vehicle detection), reading (privacy, hyperlinks, synonyms and antonyms, annotations), cooking (menus, demonstrations, suggestions), shopping (price comparison, videos of product use, navigation), construction (placement, coordination, scheduling), maintenance (diagnosis, placement, verification), teamwork (shared presentations, agenda, meeting notes), entertainment (privacy, interactive movies, music, games), medical (medication management, diagnosis, pain management, physical therapy, dementia management, record keeping, meditation, visualizations), conversation (facial movements, eye tracking, pupil contraction and dilation), education (tutoring, demonstrating, collaborating) According to [Shamir, et. al 2019] “given any two classes C1 and C2, along with any point x∈C1, and our goal is to find some nearby y which is inside C2. Our ability to do so suggests that all the classes defined by neural networks are intertwined in a fractal-like way so that any point in any class is simultaneously close to all the boundaries with all the other classes.” The results show gradient classifier can be used against itself to find nearby inputs that are classified differently that one classified by a given input. [Shamir, et. al 2019] results suggests that gradient classifiers (aka "Deep Learning") could remain forever fragile in ways that cannot be remedied by larger training sets. Consequently, a gradient classifier can be useful for heuristic rule-of-thumb guidance but should not be relied upon as the exclusive basis of consequential judgments especially ones involving life and/or death. A gradient classifier (regardless of size) is not scalable to Reusable Scalable Intelligent Systems, e.g., for pain management and dementia management because data available for gradient training is very sparse since operation of a Reusable Scalable Intelligent System depends heavily on history of the case at hand, e.g., what worked previously, progression of ailments, recent interactions, etc. Also, multiplicity of potential actions (e.g. in pain management and dementia management) is very large because at any point interaction can take many different directions, e.g., social interaction, physical therapy, medication management, etc. A large gradient classifier is not modular. For example, a pain management gradient classifier cannot be incorporated into a dementia management gradient classifier because the pain management classifier does not provide sensory inputs that are usable by the dementia management gradient classifier. Furthermore, in order to incorporate additional knowledge into the dementia management gradient classifier, the knowledge must be illustrated in operation using sensory input to create input-output training data. Creating an input-output training data to incorporate additional general knowledge can be extremely difficult because of unknowable interactions with previous input-output training data including history dependence and multiplicity of potential actions. According to [Jordan 2018, Davis and Marcus 2019], overinvestment in gradient classifiers (aka “Deep Learning”) is crowding out necessary investment in other technologies for Intelligent Systems Multitudinous different kinds of classifiers need to be created and operated in an architecture that provides services for their training, optimizing, debugging, refactoring, testing, and monitoring.

A debug scheme to improve the error identification in post-silicon validation

While developing semiconductors, post-silicon validation is an important step to identify the errors that are not detected during the pre-silicon verification and manufacturing testing phases. When the design complexity increases, the required debug time also increases because additional debug data are required to identify the errors. In this study, we present a debug scheme that improves the error identification capability. The proposed debug approach concurrently generates three types of signatures using hierarchical multiple-input signature registers (MISRs). The error-suspect debug cycles are determined by analyzing the debug cycles that are commonly contained in the erroneous signatures of the three MISRs. To reduce the amount of debug data, we compare the high-level MISR signatures in real time with the golden signatures; further, we handle the remaining two MISRs based on the tag bits that are obtained from the results of the high-level MISR. The experimental results prove that the proposed debug structure can significantly improve the error identification capability using less debug data than that used in previous debug structure.

TLB Index-Based Tagging for Reducing Data Cache and TLB Energy Consumption

Conventional cache tag matching identifies the requested data based on a memory address. However, this address-based tag matching is inefficient because it requires unnecessarily many tag bits. Previous studies show that translation look-aside buffer (TLB) index-based tagging (TLBIT) can be adopted in instruction caches because there are not many different tags at a given moment due to spatial locality, and those tags can be captured by TLBs. For the TLBIT scheme, extra TLB indices are added to each TLB entry and conventional cache tags are replaced with TLB indices to identify the requested data in the cache. TLBIT reduces the number of required tag bits in tag arrays; therefore, the cache energy consumption and area are decreased. In this paper, we show that naively adopting TLBIT for data caches is inefficient, in terms of performance and energy consumption, because of cache line searches and invalidations on TLB misses. To achieve the true potential of TLBIT, we propose four novel techniques: search zone, c-LRU, TLB buffer and demand address fetching. The search zone reduces unnecessary cache line searching and c-LRU reduces the cache line invalidations. The TLB buffer prevents immediate cache line invalidations on TLB misses. Furthermore, we present demand address fetching to reduce energy consumption in the TLB. From our experiments, we observed that the proposed techniques reduce the overall dynamic energy consumption of the data cache by 14.3 percent on average. The overall tag array area and leackage power of the data cache are also reduced by 54 and 45 percent, respectively. The TLB energy consumption is reduced by 22.7 percent. The performance impact is small, less than 0.4 percent on average. We also demonstrate that TLBIT can be applied to large caches, and set-associative TLBs.

Embedded physical‐layer authentication in cognitive radio requires efficient low‐rate channel coding schemes

In this study, the author investigates the practical limitation of the recently proposed embedded cryptographic signature authentication scheme at the physical layer. By employing the log-likelihood ratio of a tag bit and its approximation, the author shows that the equivalent authentication channel observed by the secondary receiver can be viewed as a binary-input additive white Gaussian noise channel. Then, the sphere-packing lower bound can be employed to show the transmission capability for practical finite-length authentication tags. To achieve the same effective coverage area for both the primary and secondary receivers, it essentially requires efficient low-rate channel coding schemes with near sphere-packing-bound performance at the secondary receiver, which contrasts sharply with the pessimistic conclusion of Jiang et al.

Improving the Reliability of Cache Memories using Identical Tag Bits

Cache memories are revealed to transitory error in tag bits and some of the efforts have been taken to decrease their susceptibility. In the advanced mechanisms of cache memories are most applicable components, because the soft errors are protected. The identical tag bit data is used to regain from the error in the tag bits. In this paper, to improve error protection capacity of the tag bits in caches, power efficient cache design is proposed by using Superlative Standard Techniques (SST) architecture to achieve power. To utilize the identical tag bits for transitory error protection, the proposed scheme is discussed by selecting the energy superlative standard techniques that decrease unwanted interior activities by reducing the dynamic switching power. In experimental method, results show that our proposed multilevel cache architecture sustains a performance of achieving dynamic power and reduces the power consumption up to 85% when applied to energy optimal technique.

Hybrid approach based on partial tag comparison technique and search methods to improve cache performance

An effective design of cache memory is an important aspect in computer architecture to improve the system performance. In this work, we study the effect of reducing the cache comparisons to map the cache address on the performance experimentally and analytically. Cache miss penalties have drastic impact on the systems’ performance. To overcome this, we propose a novel tag access scheme, which uses a partial comparison unit called n-bit comparator and use multiple search methods inside the data cache to improve the cache performance by reducing cache access time. Partial tag comparison (PTC) enables the cache to compare the tag in multi-stage techniques starting with the least significant bits (LSBs). Thus, useless tag comparison and number of tag bits being compared can be effectively reduced, hence reaching the requested tag is faster and the cache hit time is reduced. Simulation results show that the proposed approach outperforms conventional mapping techniques. The PTC technique improves the hit time in 2-bank and 4-bank fully associative caches by 70–96% and 67–88% over a cache with full tag comparison. Moreover, the proposed technique provides the minimum hit time when using a hash searching method rather than other searching methods: linear and binary.

Exploiting Same Tag Bits to Improve the Reliability of the Cache Memories

With the trend of increasing transient error rate, it is becoming important to prevent transient errors and provide a correction mechanism for hardware circuits, especially for SRAM cache memories. Caches are the largest structures in current microprocessors and, hence, are most vulnerable to the transient errors. Tag bits in cache memories are also exposed to transient errors but a few efforts have been made to reduce their vulnerability. In this paper, we propose to exploit prevalent same tag bits to improve error protection capability of the tag bits in the caches. When data are fetched from the main memory, it is checked if adjacent cache lines have the same tag bits as those of the data fetched. This same tag bit information is stored in the caches as extra bits to be used later. When an error is detected in the tag bits, the same tag bit information is used to recover from the error in the tag bits. The proposed scheme has small area, energy, and performance overheads with error protection coverage of 97.9% on average. Even with large working sets and various cache sizes, our scheme shows protection coverage of higher than 95% on average.

Performance Comparison of RFID Tag at UHF Band and Millimeter-Wave Band

The ultra high frequency (UHF) band spectrum will likely be congested in near future since the next generation wireless as well as Radio Frequency Identification (RFID) system users will witness the use of UHF band technology with increased demand of bandwidth, bit rate, frequency spectrum and power consumption. The alternate solution is the use of millimeter-wave band technology. It is possible to improve data throughput, range resolution and multi-user capability in mm-wave band RFID system. ‘Higher power reception efficiency and lower side lobe level (SLL) of radiation pattern’ is required for RFID system that will increase the tag range and transmission bit rate. At the same time lower SLL will minimize the interference level. Beam pointing error is another problem of UHF band antenna which reduces the tag range and bit rate. These problems can be minimized by using large number of antenna elements. But with UHF band signal it is practically difficult to construct large array antenna; since the array size becomes tremendously larger with the increase of antenna elements. ‘Higher power reception efficiency and lower SLL’ can practically be obtained by using non-uniform power distribution of large number of antenna elements in millimeter wave band. A new and technically better method of beam forming by implementing the concept of staircase power distribution (SPD) of antenna elements at 60 GHz has been investigated and presented in the paper. The SPD method is compared with Gaussian edge tapering method. It was found that the maximum SLL (MSLL) is the lowest in case of SPD. The beam efficiency of SPD is also equivalent to that of Gaussian edge tapering method. It is easier to fabricate a larger number of antenna elements within smaller area with SPD at 60 GHz system; since the antenna size is smaller and the number of different power distribution in SPD case is less and stepwise uniform. Uniform and less number of different power distribution of SPD also minimizes other technical errors.

AWARE (Asymmetric Write Architecture With REdundant Blocks): A High Write Speed STT-MRAM Cache Architecture

Spin-transfer torque magnetic RAM (STT-MRAM) is a promising memory technology for lower level caches because of its high density and nonvolatile nature. However, the high write latency is a bottleneck to its widespread adoption as the future on-chip memory. In this paper, we propose a new cache architecture-asymmetric write architecture with redundant blocks (AWARE)-that can improve the write latency by taking advantage of the asymmetric write characteristics of 1T-1MTJ STT-MRAM bit-cells. Due to the nature of the storage element in STT-MRAM, the time required for the two-state transitions ( 1→ 0 and 0→ 1) is not identical. In other words, one of the state transitions is slower than the other direction. In conventional cache architecture, the overall write latency is limited by the slower transition. However, the AWARE cache design introduces redundant blocks in each row, and they are preset to the initial state that enables the faster transition. Hence the write operations performed in these redundant blocks are much faster than the conventional write scheme. The write latency in AWARE is improved by 30% over conventional cache architecture with no area penalty in the data array. Moreover, the additional tag bits introduced in this technique result in penalty on the total cache area. In addition, the write energy increases modestly by 7% in the proposed cache design. However, this write-energy increase can be mitigated by sacrificing the cache capacity.

소프트 에러에 대한 캐쉬 메모리의 태그 비트 신뢰성 향상 기법

소프트 에러에 대한 캐쉬 메모리의 태그 비트 신뢰성 향상 기법

Different access mechanisms for set-associative cache architecture for reduced power consumption

In recent years, power consumption has become one of the most critical design concern. Due to lower miss rate, set-associative caches are usually employed to improve embedded system's performance. However, a conventional set-associative cache implementation is not power efficient. Thus, in order to achieve low-power consumption, novel set-associative cache architectures have been proposed in which efficient accessing of tag bits and the data bits takes place in two phases unlike the conventional set-associative cache architectures. The behavioural modelling of the cache architectures was done using Verilog Hardware Description Language (HDL). The synthesis results illustrate that the proposed parallel and sequential set-associative cache architectures showed significant power reduction of 34.92% and 35.36% on an average as compared to conventional parallel and conventional sequential set-associative cache architectures, respectively.

Influence of Managing the Number of Tag Bits Transmitted on the Query Tree RFID Collision Resolution Protocol

Radio Frequency Identification (RFID) technology is increasingly becoming popular, for its widespread use and more sophisticated applications. The coexistence of tags sharing the communication channel requires solutions to message collisions, which degrade bandwidth, and increase the number of transmitted bits. A new methodology called ‘window’ is presented to manage the number of bits transmitted by a tag. The aim is show how the query tree (QT) protocol is influenced by this feature, and how the performance of the novel protocol, query window tree (QwT), improves when the tag ID distribution is correlated. Therefore, we have performed a fair comparison of the Query Tree and the new proposed QwT protocol for various tag ID distributions. Simulations show that the QwT positively decreases the total number of bits that are transmitted by tags.

Tag Overflow Buffering: Reducing Total Memory Energy by Reduced-Tag Matching

We propose a novel energy-efficient cache architecture based on a matching mechanism that uses a reduced number of tag bits. The idea behind the proposed architecture is based on moving a large subset of the tag bits from the cache into an external register (called the Tag Overflow Buffer) that serves as an identifier of the current locality of the memory references. Dynamic energy efficiency is achieved by accessing, for most of the memory references, a reduced-tag cache; furthermore, because of the reduced number of tag bits, leakage energy is also reduced as a by-product. We achieve average energy savings ranging from 16% to 40% (depending on different cache structural parameters) on total (i.e., static and dynamic) cache energy, and measured on a standard suite of embedded applications.

RFID 시스템을 위한 하이브리드 하이퍼 쿼리 트리 알고리즘

A tag collision arbitration algorithm for RFID passive tags is one of the important issues for fast tag identification, since reader and tag have a shared wireless channel in RFID system. This paper suggests Hyper-Hybrid Query Tree algorithm to prevent the tag-collisions. The suggested algorithms determine the specified point in time for tag to transfer ID to reader by using value 1 of the upper 3 bit based on Query Tree. Also, because the transferred upper 3 bits of tag is different depending on the time of transfer, it is possible to predict in the suggested Algorithm. In the performance evaluation through simulation, it shows the suggested algorithm has higher performance in the number of queries compared to other Tree-based protocols.

Dynamic Tag Reduction for Low-Power Caches in Embedded Systems with Virtual Memory

This paper presents a low-power tag organization for physically tagged caches in embedded processors with virtual memory support. An exceedingly small subset of tag bits is identified for each appl...