Bit-serial Multiplier Research Articles

Enhancing Field Multiplication in IoT Nodes with Limited Resources: A Low-Complexity Systolic Array Solution

Enhancing Field Multiplication in IoT Nodes with Limited Resources: A Low-Complexity Systolic Array Solution

An efficient implementation of Hybrid Signcryption Processor using Flexible Encryption and Signature Techniques

In today’s digital era, with the enormous growth in the Internet of Things, everyday humans utilize IoT in various applications such as banking, online transactions, purchasing data forwarding, etc. Cryptography is all about the design and implementation of protocols that keep the data safe and secure from third parties. The design of the cryptographic processor present in the Field Programmable Gate Array (FPGA) incurs more power, area, and throughput. In this article, an Efficient Hybrid Signcryption Processor (EHSP) which operates based on the principle of encryption and signature is proposed. Generally, a hybrid signcryption operation comprises of Data Encapsulation Method (DEM) and Key Encapsulation Method (KEM). and in EHSP, we utilize the improved form of the Modified Kurosawa and Desmedt (MKD) hash scheme to encapsulate the key; the Elliptic Curve Cryptography (ECC) processor is used to encapsulate the message. The ECC processor is designed in a flexible manner and the flexibility is achieved by the flexible bit-serial multiplier, which reduces the power, and area consumption and maximizes the throughput. The proposed EHSP architecture is designed and simulated in Xilinx tool with various field programmable gate array families such as Virtex4 (XC4VLX60), Virtex5 (XC5VLX50), and Virtex7 (XC7V330T). The simulation result depicts the efficiency of the proposed EHSP design with respect to total power consumption, utilization of hardware, and throughput.

A Heterogeneous Microprocessor Based on All-Digital Compute-in-Memory for End-to-End AIoT Inference

Deploying neural network (NN) models on Internet-of-Things (IoT) devices is important to enable artificial intelligence (AI) on the edge realizing AI-of-Things (AIoT). However, high energy consumption and bandwidth requirement of NN models restricts AI applications on battery-limited equipments. Compute-In-Memory (CIM), featured with high energy efficiency, provides new opportunities for the IoT deployment of NN. However, the design of CIM-based full system is still at the early stage, lacking system-level demonstration and vertical optimization for running end-to-end AI applications. In this paper, we demonstrate a low-power heterogeneous microprocessor System-on-Chip (SoC) with an all-digital SRAM CIM accelerator and rich data acquisition interfaces for end-to-end AIoT NN inference. A dedicated reconfigurable dataflow controller for CIM computation greatly lowers bandwidth requirement on the system bus and improves execution efficiency. The all-digital SRAM CIM array embeds NAND-based bit-serial multiplication within the readout sense amplifier balancing the storage density and system-level throughput. Our chip achieves a throughput of 12.8 GOPS, with 10 TOPS/W energy efficiency. Benchmarked by the four tasks in MLPerf Tiny, experimental results show 1.8x to 2.9x inference speedup over a baseline CIM processor.

A Bit-Serial, Compute-in-SRAM Design Featuring Hybrid-Integrating ADCs and Input Dependent Binary Scaled Precharge Eliminating DACs for Energy-Efficient DNN Inference

The major challenge faced by modern compute-in-memory (CIM) designs is that they rely heavily on mixed-signal data converters such as digital-to-analog converters (DACs) and analog-to-digital converters (ADCs) that contribute to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim$</tex-math> </inline-formula> 15% area and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim$</tex-math> </inline-formula> 50% energy of the overall macro and are susceptible to non-linearities, leakage, and process variations, which causes deep neural network (DNN) inference/training accuracy loss. As DNN models increase in size, the number of DACs steps required per inference increases exponentially. This work proposes a four-pronged approach to address the challenges in CIM designs: 1) binary-weighted-bitline-precharge scheme utilizing dedicated reference voltages to perform input bit-serial multiplication in the charge domain, eliminating the need for dedicated DAC circuits; 2) leakage-tolerant, input-dependent-bitline-keeper circuits that maintain the local-bitline voltages; 3) hybrid-charge-sharing-based integrating-ADCs to improve the ADC conversion time by leveraging the reference voltages, thereby improving ADC latency while achieving a compact ADC design; and 4) efficient data movement and utilization of analog-to-digital co-computation. Fabricated in TSMC 65 nm, the experimental results for the compute-in-static-RAM (CISRAM) silicon prototype show an average macro energy efficiency of 153–2453.76 TOPs/W. The average macro energy efficiency is 2.3 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> more than the latest state of the art mentioned in the comparison table.

Squeezing Area of the Versatile GF (2 m ) GNB Arithmetic Operators

Cryptography primitives have a prominent role in securing applications that may require low-area realizations, for example portable devices and other resource constrained devices. A given system may require support for different cryptography based protocols/ primitives. Many standardized and/or published primitives rely on arithmetic operations over <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$GF\left(2^m\right)$</tex-math> </inline-formula> that occupy major area footprint. Therefore, versatile operators have been of interest to reduce the area penalty, in particular bit-serial multipliers. This paper introduces a novel scheme for versatile multiplication by the normal element in the Gaussian Normal Basis (GNB) leading to new low-area versatile GNB multiplier and inverter architectures that are presented for the first time, as far as we know. Specifically, the proposed inverters are the first versatile GNB inversion in open literature, to the best of our knowledge. Field Programmable Gate Arrays (FPGA) implementation results demonstrate that the proposed versatile multiplication and inversion techniques save almost 30% and 46%, and for Application Specific Integrated Circuits (ASIC) implementation the savings are up-to 29% and 35% respectively, in terms of area when compared to other counterparts.

Booth Encoded Bit-Serial Multiply-Accumulate Units with Improved Area and Energy Efficiencies

Bit-serial multiply-accumulate units (MACs) play a crucial role in various hardware accelerator applications, including deep learning, image processing, and signal processing. Despite the advantages of bit-serial MACs, such as a small footprint, full hardware utilization, and high frequency, their serial nature can lead to high latency and potentially compromised performance. This study investigates the potential of bit-serial solutions by applying Booth encoding to bit-serial multipliers within MACs to enhance area and power efficiencies. We present two types of bit-serial MACs based on radix-2 and radix-4 Booth encoding multipliers, respectively. Their performance is assessed through simulations and synthesis results, demonstrating the benefits of the proposed approach. The radix-4 Booth bit-serial MAC improves power and area efficiencies compared to the original bit-serial MAC. Operating at TSMC 90 nm and 150 MHz, our design exhibits a remarkable 96.39% reduction in area-power-product (APP). Moreover, the prototype verification on a Xilinx Kintex-7 FPGA proved successful. The proposed solution offers significant advantages in energy efficiency, area reduction, and APP, making it a promising candidate for next-generation hardware accelerators in offline inference, low-power devices, and other applications.

A Digital Bit-Reconfigurable Versatile Compute-In-Memory Macro for Machine Learning Acceleration

This work proposes a digital versatile SRAM-based computing-in-memory (CIM) macro with reconfigurable precision from 1-bit to 16-bit and programmable mathematical functions, including addition and multiplication. The proposed CIM macro supports 1 16-bit weight-stationary addition (WSA) and operands-stationary addition (OSA), and 1 8-bit bit-serial multiplication (BSM). The proposed versatile CIM macro accelerates various machine learning algorithms such as convolutional neural networks (CNNs) and self-organizing maps (SOMs). A test chip was fabricated in 65nm CMOS technology and achieved an energy efficiency of up to 40.7 TOPS/W for WSA (1-bit), 39.4TOPS/W for OSA (1-bit), and 84.1 TOPS/W for BSM (1-bit).

Design of Low Power Versatile Bit-Serial Multiplier in Finite Field GF (2m)

Finite field arithmetic is the most important component in applications like cryptography, computer algebra and error correcting codes. Versatility is an important property the hardware industry lacks and trying to establish as much as possible. To survive in this booming technological word, the new designs should be of an adjustable one, which processes the versatile property. In this we have proposed an efficient VLSI design for versatile bit-serial multiplier in finite fields GF (2m). The versatile multiplier designed here modifications done by reducing the unwanted switching activity removed by clock gating scheme. Our design provides a solution to the power reduction. The introduced multiplier operates over a variety of binary fields up to an order of 2m. The value of m can vary up to 264 bits. Multiplier is designed using Verilog HDL.

A Novel Low-Area Point Multiplication Architecture for Elliptic-Curve Cryptography

This paper presents a Point Multiplication (PM) architecture of Elliptic-Curve Cryptography (ECC) over GF(2163) with a focus on the optimization of hardware resources and latency at the same time. The hardware resources are reduced with the use of a bit-serial (traditional schoolbook) multiplication method. Similarly, the latency is optimized with the reduction in a critical path using pipeline registers. To cope with the pipelining, we propose to reschedule point addition and double instructions, required for the computation of a PM operation in ECC. Subsequently, the proposed architecture over GF(2163) is modeled in Verilog Hardware Description Language (HDL) using Vivado Design Suite. To provide a fair performance evaluation, we synthesize our design on various FPGA (field-programmable gate array) devices. These FPGA devices are Virtex-4, Virtex-5, Virtex-6, Virtex-7, Spartan-7, Artix-7, and Kintex-7. The lowest area (433 FPGA slices) is achieved on Spartan-7. The highest speed is realized on Virtex-7, where our design achieves 391 MHz clock frequency and requires 416 μs for one PM computation (latency). For power, the lowest values are achieved on the Artix-7 (56 μW) and Kintex-7 (61 μW) devices. A ratio of throughput over area value of 4.89 is reached for Virtex-7. Our design outperforms most recent state-of-the-art solutions (in terms of area) with an overhead of latency.

Low‐space bit‐serial systolic array architecture for interleaved multiplication over GF(2 m )

This article offers a new bit-serial systolic array architecture to implement the interleaved multiplication algorithm in the binary-extended field. The exhibited multiplier structure is more proper for VLSI implementation as it has regular cell structures as well as local communication wires between the cells. The ASIC implementation results of the suggested bit-serial multiplier structure and the existing competitive bit-serial multiplier structures previously described in the literature indicate that the recommended design achieves a notable reduction in area and significant improvement of area-time complexities by at least 28.4% and 35.7%, respectively. Therefore, it is more proper for cryptographic applications forcing more restrictions on the space.

Low-power and high-speed design of a versatile bit-serial multiplier in finite fields GF(2m)

In this paper, a novel architecture for a versatile polynomial basis multiplier over GF(2m) is presented. The proposed architecture provides an efficient execution of the Most Significant Bit (MSB)-First, bit-serial multiplication for different operand lengths. The main advantages of the proposed architecture are (a) its flexibility on arbitrary Galois field sizes, (b) its hardware simplicity which results in small area implementation, (c) low power consumption by employing the gated clock technique (d) improvement of maximum clock frequency due to the lessening of critical path delay. These abilities are achieved by means of utilizing a row of tri-state buffers and some control signals along with the (MSB)-first multiplier in a particular architecture. The efficiency of the proposed architecture is evaluated based on criteria such as time (latency, critical path) and space (gate-latch number) complexity.

Bit-Serial and Bit-Parallel Montgomery Multiplication and Squaring over GF(2^m)

Multiplication and squaring are main finite field operations in cryptographic computations and designing efficient multipliers and squarers affect the performance of cryptosystems. In this paper, we consider the Montgomery multiplication in the binary extension fields and study different structures of bit-serial and bit-parallel multipliers. For each of these structures, we study the role of the Montgomery factor, and then by using appropriate factors, propose new architectures. Specifically, we propose two bit-serial multipliers for general irreducible polynomials, and then derive bit-parallel Montgomery multipliers for two important classes of irreducible polynomials. In this regard, first we consider trinomials and provide a way for finding efficient Montgomery factors which results in a low time complexity. Then, we consider type-II irreducible pentanomials and design two bit-parallel multipliers which are comparable to the best finite field multipliers reported in the literature. Moreover, we consider squaring using this family of irreducible polynomials and show that this operation can be performed very fast with the time complexity of two XOR gates.

The art of numbers

Programmable logic and high-resolution maths do not mix that well. Field programmable gate arrays (FPGAs) did not start out as high-speed maths engines. Initially, they were very slow at multiplies because the only efficient architecture they could use was the bit-serial multiplier. Although efficient on a conventional FPGA, the bit-serial multiplier is very, very slow. As FPGAs grew, they added hardwired multipliers that could be combined to build much faster maths engines. However, there are still restrictions on how much you can squeeze into an FPGA cost-effectively. This paper discuss ways to squeeze more efficiency out of the devices.

Low-Power, Low-Complexity Bit-Serial VLSI Architecture for 1D Discrete Wavelet Transform

The discrete wavelet transform (DWT) is an upcoming compression technique that has been selected for MPEG-4 and JEPG 2000, because it has no blocking effects and it efficiently determines the frequency property of the temporary signals. In this paper, we propose a low-complexity, low-power bit-serial DWT architecture, employing a two-channel lattice-based quadrature mirror filter (QMF). The filter consists of four lattices (filter length = 8), and we determine the quantization bit for the coefficients using a fixed-length peak signal-to-noise ratio analysis and propose the architecture of the bit-serial multiplier with a fixed coefficient. The canonical signed digit encoding for the coefficients is applied to minimize the number of nonzero bits, thus reducing the hardware complexity. The proposed folded one-dimensional DWT architecture processes the other resolution levels during idle periods by decimations, and it provides efficient scheduling. The proposed architecture requires only flip-flops and full adders. This architecture has been designed and verified by the Verilog HDL and synthesized using the Synopsys Design Compiler with the DongbuAnam 0.18 μm Standard Cell Library. The maximum throughput is 393 Mbps at 450 MHz with a latency of 16 clocks, and the gate count is about 5K in equivalent two-input NAND gates. The dynamic power is 7.02 mW at 1.8 V. The data scheduling using a data dependency graph, and the performance, power, and required hardware cost are discussed.

A novel approach for bit-serial AB2 multiplication in finite fields GF(2 m)

This paper presents a new inner product AB 2 multiplication algorithm and effective hardware architecture for exponentiation in finite fields GF(2 m ). Exponentiation is more efficiently implemented by applying AB 2 multiplication repeatedly rather than AB multiplication. Thus, efficient AB 2 multiplication algorithms and simple architectures are the key to implementing exponentiation. Accordingly, this paper proposes an efficient inner product multiplication algorithm based on an irreducible all one polynomial (AOP) and simple architecture, which has the same hardware equipment as Fenn's AB multiplier. The proposed bit-serial multiplication algorithm and architecture are highly regular and simpler than those of previous works.

Low-power exponent architecture in finite fields

The paper presents an efficient exponent architecture for public-key cryptosystems in the finite field GF(2m). Multiplication is the key operation in implementing circuits for cryptosystems, as the process of encrypting and decrypting a message requires modular exponentiation, which can be decomposed into repeated multiplications. Exponentiation is implemented more efficiently by repeatedly applying AB2 multiplications rather than AB multiplications. Thus, effective AB2 multiplication algorithms and simple architectures are the key for implementing exponentiations. Accordingly, the paper proposes an efficient inner product multiplication algorithm using an irreducible all one polynomial (AOP) and simple architecture. Furthermore, the proposed bit-serial multiplication algorithm and architecture are highly regular and simpler than those in previous studies.

Computation of AB2 multiplication in GF(2m) using low-complexity systolic architecture

An AB2 operation is known as an efficient basic operation for public key cryptosystems over GF(2m), and various systolic arrays for performing AB2 operations have already been proposed using a standard basis representation. However, these circuits have certain shortcomings for cryptographic application due to their high circuit complexity and long latency. Therefore, further research on an efficient AB2 multiplication circuit is still needed. Accordingly, the authors present a new AB2 algorithm and its systolic realisations in GF(2m). First, a new algorithm is proposed based on the MSB-first scheme using a standard basis representation. Thereafter, bit-parallel and bit-serial systolic power multipliers are derived that exhibit a lower hardware complexity and smaller latency than conventional approaches. In addition, since the proposed architectures incorporate simplicity, regularity, modularity, and pipelinability, they are well suited to VLSI implementation and can be easily applied as a basic architecture for computing an inverse/division operation and in crypto-processor chip design.

Dual bases and bit-serial multiplication in [formula omitted

We present the case for using trace function and dual bases in explaining bit-serial multiplication in F q n . This approach leads to a better insight into the structure of bit-serial multiplication and considerably simplifies the proofs of the efficiacy of some designs proposed in the past.

Built-in self-test of bit-serial arithmetic units for digital signal processing

Bit-serial multipliers with fixed coefficients are commonly exploited in area efficient DSP applications. Built-In Self-Test is a viable technique for high quality testing. We present and analyze a very area efficient BIST technique based on normal or inverted output-to-input feedback. Testing is employed at system speed.

The asynchronous counterflow pipeline bit-serial multiplier

Abstract We propose a novel architecture of an asynchronous bit-serial multiplier with counterflow data streams. The crucial idea of the proposed design is that data transfer between basic cells is acknowledged by another data transfer in the opposite direction. This design solution has resulted in lower hardware complexity because there is no extra acknowledged circuitry. For the multiplier design, a mixed-mode delay model is adopted. First, the control circuit of the multiplier's basic cell is designed as a speed-independent circuit. Then the method for interconnecting basic cells into a 1D array is presented. Finally, we incorporate data-path function into the basic cell under the bounded-delay model.