Control Bits Research Articles

ЗАВАДОСТІЙКІСТЬ ОДИНИЧНОГО КОДУВАННЯ ДЛЯ ПРИСТРОЇВ КЕРУВАННЯ

The method of encoding numerical information plays a significant role in the synthesis of the control device in the process of encoding its states. This is due not only to the complexity of the combination of control devices, but also to the need to control their noise stability. In most cases, the controllability of code combinations is achieved by introducing additional (control) bits, i.e. by increasing the dimension of codes and the introduction of means of generating control bits. However, there are coding methods that have a "built-in" in the structure of codes the ability to noise stability. Such codes include one of the types of unit codes, namely the unit position (marking) code. This article considers the property of noise stability of a unit position code with an orientation to the applying the control device based on the R-automaton for coding its states. Increasing the bits of such code and a specific way of forming neighboring code combinations provide such a property as equidistance. And this, in turn, allows you to organize simple combinational schemes of nodes for detection and correction of errors such as "race" signals. Also, the functional schemes for error detection and correction units and their connection to the shift register, which is a storage part of the control device based on the R-automaton, are shown.

Adaptive Beamforming With Continuous/Discrete Phase Shifters via Convex Relaxation

Adaptive antenna array employing phase shifters only can reduce the hardware cost and power consumption, but the related optimization is well understood to be difficult to solve. In this paper, we examine the use of both continuous phase shifters (CPS) and discrete phase shifters (DPS) in antenna array for adaptive interference suppression. First, we formulate the phase-only tuning problem with CPS via quadratically constrained quadratic program (QCQP), which can be approximated through semidefinite relaxation (SDR) and solved by convex-optimization solvers efficiently. We also demonstrate that quantizing such results directly may not necessarily give acceptable performance. Then, we propose to use binary quadratic program (BQP) for the optimization of the adaptive beamformer utilizing DPS with an arbitrary number of control bits to specify the phase-shift levels. The resultant BQP can be relaxed and solved efficiently too. Moreover, due to the similarity between the CPS and DPS formulation, we can mix them in a single beamforming scheme to provide additional compromises between the output signal-to-interference and noise ratio (SINR) performance and implementation cost. Simulations show that in the considered interference-limited environment, our proposed beamformers with CPS, DPS, and hybrid phase shifters (HPS) give desirable results as expected.

Bluetooth Low Energy Error Correction Based on Convolutional Coding

Contemporarily, the Internet of Things (IoT) is recently a newly emerging technology for connecting small devices into a platform; the IoT has been an increasingly demanded front-edge technology in terms of connecting different devices using information transmission and storage technology. To adapt to the small capacities of device batteries, Bluetooth Low Energy is adopted as the protocol of communication. However, the existing standards do not have a suitable and specific error correction method. As there is no ideal information transmission channel, there must be errors that occurred during message transmission. The performance and capacity of error correction become decisive factors in evaluating how efficient the IoT communication system performs. This article uses convolutional coding—a better-performing coding scheme than block coding—to correct errors in information transmission and reception on Internet of Things devices. It is better competent to control and correct bit errors in information transmission. To achieve this goal, convolutional coding algorithms devised by Dr Justin Coon at the University of Oxford have been referred to. By simulation using MATLAB, it has been found that the error rate is enhanced significantly for high Signal-to-Noise Ratio (SNR) in convolutional codes compared to uncoded messages.

A Yang–Baxter integrable cellular automaton with a four site update rule

We present a one dimensional reversible block cellular automaton, where the time evolution is dictated by a period 3 cycle of update rules. At each time step a subset of the cells is updated using a four site rule with two control bits and two action bits. The model displays rich dynamics. There are three types of stable particles, left movers, right movers and ‘frozen’ bound states that only move as an effect of scattering with the left and right movers. Multi-particle scattering in the system is factorized. We embed the model into the canonical framework of Yang–Baxter integrability by rigorously proving the existence of a commuting set of diagonal-to-diagonal transfer matrices. The construction involves a new type of Lax operator.

40 GHz VCO and Frequency Divider in 28 nm FD-SOI CMOS Technology for Automotive Radar Sensors

This paper presents a 40 GHz voltage-controlled oscillator (VCO) and frequency divider chain fabricated in STMicroelectronics 28 nm ultrathin body and box (UTBB) fully depleted silicon-on-insulator (FD-SOI) complementary metal-oxide–semiconductor (CMOS) process with eight metal layers back-end-of-line (BEOL) option. VCOs architecture is based on an LC-tank with p-type metal-oxide–semiconductor (PMOS) cross-coupled transistors. VCOs exhibit a tuning range (TR) of 3.5 GHz by exploiting two continuous frequency tuning bands selectable via a single control bit. The measured phase noise (PN) at 38 GHz carrier frequency is −94.3 and −118 dBc/Hz at 1 and 10 MHz frequency offset, respectively. The high-frequency dividers, from 40 to 5 GHz, are made using three static CMOS current-mode logic (CML) Master-Slave D-type Flip-Flop stages. The whole divider factor is 2048. A CMOS toggle flip-flop architecture working at 5 GHz was adopted for low frequency dividers. The power dissipation of the VCO core and frequency divider chain are 18 and 27.8 mW from 1.8 and 1 V supply voltages, respectively. Circuit functionality and performance were proved at three junction temperatures (i.e., −40, 25, and 125 °C) using a thermal chamber.

АТТЕНЮАТОР С ЦИФРОВЫМ УПРАВЛЕНИЕМ НА БАЗЕ МОДУЛЯ М44752

Attenuators are often used in radio receivers to expand the dynamic range of input signals,as well as to control the output power of radio transmitters. Recently, attenuators are used intransceiver modules of active antenna arrays. Attenuators differ in operating frequency range,base of elements, control method, operating power. An urgent task is the creation and research ofnew microcircuits of attenuators with digital control of domestic production. The purpose of thiswork is an experimental research of the main parameters and characteristics of a digital attenuatorof the decimeter wave range. The object of the study is an attenuator of the M44752 type installedon the test board. It is manufactured by JSC "SPE "Istok" named after A.I. Shokin". Theresults of the experimental research are given in the operating frequency range from 0.1 to 2 GHz.There are a switching circuit, a photo of a model and six amplitude-frequency characteristics fordifferent control codes. The following electrical parameters have been achieved: – operating frequencyrange is from 0.1 to 2 GHz; – attenuation range is from 1 to 50 dB; – permissible inputpower is not more than 23 dBm; – the number of control bits is 6; – switching time is not morethan 50 ns;– VSWR of input and output is not more than 2. The obtained results of the study of theM44752 module can be used in ultra-wideband transceiver communication equipment for variouspurposes, navigation and radiolocation. The relevance of the research is confirmed by two currenttrends – microminiaturization of electronic equipment and import substitution.

A Cascaded Multicasting Architecture for Test Data Compression

This paper proposes a cascaded multicasting scan (CMS) architecture with simple control logic and low hardware overhead for test data compression. Instead of specifying all the addresses of the scan chains that will receive the test data in each broadcast, CMS specifies only the address of the first scan chain using log2(n) control bits in each broadcast on an n-scan chain architecture. CMS relies on test pattern compatibility analysis to determine the scan chain order to minimize the number of broadcasts. Experimental results show that with a much smaller hardware overhead CMS achieves a compression effect comparable to that attained by previous work on multicasting scan. The runtime for synthesizing a CMS architecture is also much smaller than that used by previous work.

Design of an auto adaption unit for reconfigurable analog to digital converters

This paper shows an auto adaption unit for reconfigurable ADC that is designed for low power operation with the transistor being operated in weak inversion region. The presented adaptation unit separates high frequency bio-signals from low frequency bio-signals and configures the ADC in the correct mode of operation. The adaptive mechanism provides technological flexibility in order to reconfigure the analog to digital converter (ADC) resolution and sampling rate regardless of the direction of the converter. It produces control bits toconfigure the ADC, based on the frequency and amplitude of the input signal. The reconfigurable ADC along with a auto adaptation circuitis designed for bio-mpedance monitoring systems. The paper consists of pre-amplifier and utilized models of FVC and Schmitt trigger concepts to design auto adaptation unit. The adaption unit consumes 89 $$\upmu$$ W with a supply voltage of 0.8 V. Simulation results found the frequency of input signals 1 to 10 MHz for the 10 KHz input signal, the DC voltage produced by the frequency-to-voltage converter is − 691 mV.The entire circuitry is designed, simulated and analyzed by using Cadence EDA tool with 18nm Fin-FET technology.

A K-Band Variable-Gain Phase Shifter Based on Gilbert-Cell Vector Synthesizer With RC–RL Poly-Phase Filter

A K-band variable-gain phase shifter using a Gilbert-cell vector synthesizer with a current digital-to-analog converter (DAC) and an RC-RL poly-phase filter (PPF) is presented, which is fabricated with a 65-nm RF CMOS process. It controls both gain and phase with low phase and gain variations as well as a low insertion loss. The Gilbert cell synthesizes a vector by summing in-phase (I) and quadrature (Q) phase signals of which the amplitudes are decided by the tail currents of the summing cells, respectively. The tail currents are given by current DACs, which are particularly designed to make the synthesizer have a constant output impedance in all phase and gain states. Because the gain and phase control resolutions depend on those of the current DACs, the size and insertion loss of the variable-gain phase shifter are not dependent on the control resolutions. The total root-mean-square (rms) phase and gain errors are measured to be 0.488° and 0.098 dB for 4096 states of the 7-bit 360° phase and 5-bit 17.8-dB gain controls, respectively, which are calibrated with extra 2-phase and 1-gain control bits. It shows -3.5 dB maximum gain including ON-chip balun losses with 6.6-mW dc power consumption.

A low power 102 dB Reconfigurable Variable Gain Amplifier for Multistandard Receivers

This paper proposes a low power single-stage variable gain amplifier (VGA) with a novel structure that is digitally reconfigured through a control bit to provide suitable performance in all modes. The presented structure employs a novel technique to further expand gain range as well as improve input-referred noise while occupying a much smaller area. To ralex the noise requirements, the VGA has been designed based on an open-looped architecture. Also, the source degeneration and gm-boosting techniques have been used to achieve good linearity. The proposed VGA has been realized to support WLAN/WiMAX/LTE standards. The VGA has been designed and simulated in TSMC 130 nm CMOS technology via Cadence Analog Virtuoso. Post Layout Simulation results show that the proposed VGA presents an excellent gain range from −25.2 to 76.8 dB, a noise figure of 17.5 dB at maximum gain and an input 3rd order intercept of 10 dBm at −4 dB gain. The VGA consumes 2.23 mA from a 1.3 V power supply and occupies a less area equal to 0.0019 mm2. Moreover, the robustness of the proposed VGA is verified by means of PVT and Monte Carlo simulations.

Intrusion detection of hierarchical distribution network system based on machine computation

In order to solve the problems of low detection accuracy and long detection time of traditional hierarchical distributed system intrusion detection method, a hierarchical distributed system intrusion detection method based on machine computing is proposed. By judging the Chinese protocol type of IP message and the control bit value of TCP, the network traffic is transformed into different sub-flows, and the characteristic parameters of traffic behaviour are extracted from the sub-flows. Based on the invasion behaviour characteristics obtained, the vector with six-dimensional characteristics is selected as the important symbol of invasion. By combining rule detection method, support vector machine and machine learning classification, the intrusion detection of hierarchical distribution network system is realised by embedding detection modules at different levels. Experimental results show that this method can effectively reduce intrusion detection time and improve detection accuracy.

A high-speed programmable and scalable terahertz holographic metasurface based on tiled CMOS chips

Metasurfaces, which consist of arrays of subwavelength scatterers, can be used to precisely control incident electromagnetic fields, but are typically static once fabricated. A dynamically programmable array of terahertz meta-elements, in which each element can be individually reconfigured to allow controlled wavefront shaping, could be of value in terahertz applications such as wireless communication, sensing and imaging. Here, we show that large-scale programmable metasurfaces can be created using arrays of complementary metal–oxide–semiconductor (CMOS)-based chip tiles. We developed an aperture with a 2 × 2 array of tiled chips consisting of 576 meta-elements, each individually addressable and digitally programmable with 8 bits of control at GHz speed, and fabricated in a 65 nm industry-standard CMOS process. The active-circuit-coupled terahertz meta-element structure can be reconfigured, providing digitally programmable metasurfaces with amplitude and phase control, around 25 dB of amplitude modulation depth, dynamic beamforming across ±30°, multibeam formation and programmable holographic projections at 0.3 THz. The integration of active electronic systems and meta-elements using commercial silicon fabrication techniques can be used to create scalable and dynamically programmable terahertz metasurfaces.

Robust Distributed Monitoring of Traffic Flows

Unrelenting traffic growth, device heterogeneity, and load unevenness create scalability challenges for traffic monitoring. In this paper, we propose Robust Distributed Computation (RoDiC), a new approach that addresses these challenges by shifting a portion of the monitoring-task execution from an overloaded network element to another element that has spare resources. Moving the entire execution of the task away from the overloaded element might be infeasible because execution on multiple elements is inherent in the task or requires at least partial participation by the designated overloaded element. Furthermore, distributed execution of a stateful task has to be resilient to network noise in the form of packet reordering and loss. The RoDiC approach relies on two main principles of packet grouping and state overlap to support exact robust distributed monitoring of traffic flows under network noise. RoDiC uses an open-loop paradigm that does not add any control packets, communicates flow state in-band by appending few control bits to packets of monitored flows, and keeps measurement latency low. We apply RoDiC to the problem of flow-size computation and discuss how to instantiate our general technique for real-time packet-loss telemetry. The paper develops robust algorithms, proves their correctness and performance properties, and reports an evaluation driven by realistic traffic traces. The RoDiC algorithms successfully distribute the monitoring-task load while keeping the memory and computation overhead low.

Wideband 23.5–29.5-GHz Phased Arrays for Multistandard 5G Applications and Carrier Aggregation

This article presents a 23.5–29.5-GHz $8\times 8$ phased array for wideband multistandard applications. The array is based on wideband high-performance $2\times 2$ transmit/receive (TRX) quad-beamformer chips with 6 bit of phase control and 8 bit of gain control. The antenna is designed using a stacked-patch structure combined with a two-stage impedance matching network to enhance its bandwidth. The $8\times 8$ phased array achieves an effective isotropic radiated power (EIRP) of 54.8 dBm at P1dB with a 3-dB bandwidth of 23.5–30.5 GHz and can scan to ±60° in the azimuth plane and +/40° in the elevation plane with excellent patterns with a single-point calibration at 27 GHz. Measured error vector magnitude (EVM) for a 64-QAM 200 and 800-Mbaud waveforms result in a system EVM of 5% (−26 dB) in the TX mode at an average EIRP of 46–47 dBm at 24.5–29.5 GHz. Also, the wideband array is capable of 16-QAM 24-Gb/s links with an EVM <16% over all scan angles. An interband carrier aggregation (CA) system is also demonstrated with the wideband array using 200-Mbaud 64-QAM waveforms with 25- and 29-GHz carriers. The phased-array phase and amplitude settings are chosen such that the 25- and 29-GHz waveforms are radiating simultaneously at the same angle with low scan loss, resulting in an efficient system. Also, the out-of-band third-order intermodulation products generated by the power amplifier on each element are filtered out by the antenna. CA measurements with up to 50° scan angles are demonstrated with low EVM. To the best of our knowledge, this is the first demonstration of CA in millimeter-wave fifth-generation (5G) systems.

Residue monitor enabled charge-mode adaptive echo-cancellation for simultaneous bidirectional signaling over on-chip interconnects

The full-duplex data communication over on-chip global interconnects suffers from large amounts of amplitude residue echo, leading to the closure of the vertical eye. This work proposes, a residue monitor enabled adaptive echo-cancellation scheme for full-duplex communication with power efficient charge-mode circuits. The proposed architecture employs charge-domain echo cancellation scheme for separating the outbound signal from the inbound signal by precisely controlling the capacitor bank output, thanks to the availability of residue monitor and high precision MOS switches and capacitors at sub-100 nm technology nodes. The residue monitor in the loop tracks the amount of amplitude residue and then sets the control bits, when the loop is locked. Further, this work proposes power efficient charge-mode circuits based replica generation stage, which does not contribute to additional power consumption like in the conventional echo-cancellation schemes. The proposed scheme is implemented at the architectural level with behavioural modeling in Verilog-AMS and also at the circuit level in 1.2 ​V, 65-nm CMOS Technology. The behavioural simulations shows that the residue monitor loop is getting locked while tracking the control voltage generated by the charge regulator for the target near-zero amplitude residue and accordingly control bits to the capacitor bank are set. Circuit level performance shows the functioning at a bidirectional data rate of 20 Gbps over a 1-mm on-chip global interconnect and the extracted received signal has 149 ​mV differential swing at a power consumption of 9.64 ​mW.

A 37–42-GHz 8 × 8 Phased-Array With 48–51-dBm EIRP, 64–QAM 30-Gb/s Data Rates, and EVM Analysis Versus Channel RMS Errors

This article presents a 5G 37–42-GHz $8\times 8$ phased array. The array is based on $2\times 2$ SiGe transmit/receive (TRX) beamformer chips in the SiGe technology with 6 bits of phase control and 8 bits of gain control. A detailed study is presented, showing the effects of array-level amplitude and phase errors on the radiated error vector magnitude (EVM) of 64-element arrays. The array scans to ±60° in the azimuth plane and ±50° in the elevation plane with low sidelobes. The measured peak effective isotropic radiated power (EIRP) is 51 dBm at Psat with a 3-dB bandwidth of 36–41.5 GHz. A 39-GHz communication system is also demonstrated along with a high-pass filter and an integrated upconverter/downconverter and achieves a local oscillator (LO) and image rejection level of 50 dBc, meeting FCC requirements of <−13 dBm/MHz of total leakage power. The array achieves < 5% EVM (−26 dB) using a 64-QAM 200-MHz waveform at an average EIRP of 44 dBm over all scan angles, including the LO and upconverter/downconverter contributions. A 30-Gb/s communication link with 64-QAM modulation is also shown. To our knowledge, this is the first demonstration of a 39-GHz phased-array communication system for 5G applications.

Physically Unclonable and Reconfigurable Computing System (PURCS) for Hardware Security Applications

A physically unclonable and reconfigurable computing system is introduced which provides both logic locking and authentication of devices. A chaotic oscillator is required to generate the chaotic signals and can produce different Boolean functions using different tuning parameters, including a control bit, iteration number, threshold voltage, and bifurcation parameter. The aim of this article is to build a hybrid computing system with the mixed implementation of standard logic gates and reconfigurable chaos-based logic gates. The tuning parameters of the oscillator make up the secret key for logic locking. Process variation due to fabrication can be leveraged to generate unique keys for each chip. The whole computing system exhibits physical unclonable function (PUF) characteristics and can be used to generate challenge–response pairs (CRPs) for authenticating devices. We have used ISCAS’85 combinational benchmark circuits to demonstrate the results. The Hamming distance between correct and wrong outputs is calculated to ensure that 50% of the output bits are flipped when the wrong key is applied. A Boolean SAT attack has been carried out on the system and it displays exponential complexity with an increase in the total number of chaos gates and key size of each chaos gate. The hybrid system demonstrates near-ideal PUF metrics, including uniqueness, uniformity, and bit aliasing. Common machine learning attacks have been executed on the CRPs generated from the whole system and results show that the proposed chaos-based PUF is robust against modeling attacks. The hybrid system has significantly less overhead compared to traditional systems containing both logic locking and PUF circuitry.

Replica wormhole and information retrieval in the SYK model coupled to Majorana chains

Motivated by recent studies of the information paradox in (1+1)-D anti-de Sitter spacetime with a bath described by a (1+1)-D conformal field theory, we study the dynamics of second Ŕenyi entropy of the Sachdev-Ye-Kitaev (SYK) model (χ) coupled to a Majorana chain bath (ψ). The system is prepared in the thermofield double (TFD) state and then evolved by HL + HR. For small system-bath coupling, we find that the second Rényi entropy {S}_{upchi L,upchi R}^{(2)} of the SYK model undergoes a first order transition during the evolution. In the sense of holographic duality, the long-time solution corresponds to a “replica wormhole”. The transition time corresponds to the Page time of a black hole coupled to a thermal bath. We further study the information scrambling and retrieval by introducing a classical control bit, which controls whether or not we add a perturbation in the SYK system. The mutual information between the bath and the control bit shows a positive jump at the Page time, indicating that the entanglement wedge of the bath includes an island in the holographic bulk.

Error correction schemes for fully correlated quantum channels protecting both quantum and classical information

We study efficient quantum error correction schemes for the fully correlated channel on an n-qubit system with error operators that assume the form \(\sigma _x^{\otimes n}\), \(\sigma _y^{\otimes n}\), \(\sigma _z^{\otimes n}\). Previous schemes are improved to facilitate implementation. In particular, when n is odd and equals \(2k+1\), we describe a quantum error correction scheme using one arbitrary qubit \(\sigma \) to protect the data state \(\rho \) in a 2k-qubit system. The encoding operation \(\sigma \otimes \rho \mapsto \Phi (\sigma \otimes \rho )\) only requires 3k CNOT gates (each with one control bit and one target bit). After the encoded state \(\Phi (\sigma \otimes \rho )\) goes through the channel, we can apply the inverse operation \(\Phi ^{-1}\) to produce \({\tilde{\sigma }} \otimes \rho \) so that a partial trace operation can recover \(\rho \). When n is even and equals \(2k+2\), we describe a hybrid quantum error correction scheme using any one of the two classical bits \(\sigma \in \{|ij{\rangle }{\langle }ij|: i, j \in \{0,1\}\}\) to protect a 2k-qubit state \(\rho \) and two classical bits. The encoding operation \(\sigma \otimes \rho \mapsto \Phi (\sigma \otimes \rho )\) can be done by \(3k+2\) CNOT gates and a single-qubit Hadamard gate. After the encoded state \(\Phi (\sigma \otimes \rho )\) goes through the channel, we can apply the inverse operation \(\Phi ^{-1}\) to produce \(\sigma \otimes \rho \) so that a perfect protection of the two classical bits \(\sigma \) and the 2k-qubit state is achieved. If one uses an arbitrary two-qubit state \(\sigma \), the same scheme will protect 2k-qubit states. The scheme was implemented using MATLAB, Mathematica, Python and the IBM’s quantum computing framework qiskit.

A Low Power Auto Adaption Unit for Reconfigurable Data Converter

This paper substantiates a simple auto adaption unit that is used for Reconfigurable ADC which is suitable for biomedical and mixed signal circuit test applications. The adaption unit make available in order to configure the analog to digital converter (ADC) resolution and the sampling rate regardless of the converter circuit. It generates control bits which controls reconfigurable ADC to operate on various modes based on the frequency of the input signal and the amplitude. The paper utilized models of FVC and Schmitt trigger concepts to design auto adaptation unit. The adaption unit consumes 106.2μW with a supply voltage of 1V. The entire circuitry is designed, simulated and analyzed by using Cadence EDA tool with 180 nm CMOS technology.