Bit-line Research Articles

A 1G-cell floating-gate NOR flash memory in 65 nm technology with 100 ns random access time

A 1G-cell NOR flash memory chip has been designed and fabricated successfully with 65 nm technology. To compromise the array efficiency and chip speed, the paper establishes an array model including parasitics of the whole array, and optimizes the sector structure as 512 wordlines (WLs) and 4096 bitlines (BLs). Furthermore, by adding other models of long and thin metal lines, we have analyzed the speed of critical circuit nodes. As a result, the agreement of WL delay between simulation and measurement verifies the accuracy of the array model and lines models. The test results indicate that the chip achieves random access time of 100 ns and page read time of 25 ns under 3.3 V voltage supply.

Offset-Compensated Cross-Coupled PFET Bit-Line Conditioning and Selective Negative Bit-Line Write Assist for High-Density Low-Power SRAM

An offset-compensated cross-coupled PFET bit-line (BL) conditioning circuit (OC-CPBC) and a selective negative BL write-assist circuit (SNBL-WA) are proposed for high-density FinFET static RAM (SRAM). The word-line (WL) underdrive read-assist and the negative BL write-assist circuits should be used for the stable operation of high-density FinFET SRAM. However, the WL underdrive read-assist circuit degrades the performance, and the negative BL write-assist circuit consumes a large amount of energy. The OC-CPBC enhances BL development during the evaluation phase by applying cross-coupled PFETs whose offset is compensated by precharging each of the two BLs separately through diode-connected cross-coupled PFETs. The SNBL-WA performs a write assist only when a write failure is detected, and this selective write assist reduces the write energy consumption. The simulation results show that the performance and energy consumption are improved by 41% and 48%, respectively, by applying the OC-CPBC and SNBL-WA to SRAM, even with a decrease in area.

Transient and Thermal Analysis on Disturbance Immunity for 4<inline-formula> <tex-math notation="LaTeX">$\mathrm{F}^{2}$ </tex-math></inline-formula> Surrounding Gate 1T-DRAM With Wide Trenched Body

This paper presents a one-transistor dynamic random access memory (1T-DRAM) based on a novel surrounding-gate transistor with wide trenched body (WT-SGT). This 1T-DRAM exhibits favorable transient performance after word line (WL)/bit line (BL) disturbance, which is verified using Sentaurus TCAD 12.0. The proposed memory cell can be fabricated with a feature area of 4F <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and with processes that are fully compatible with conventional CMOS technology. Extended simulations reveal three key findings. First, the WT-SGT achieves a high-speed programming operation (1.17 ns) at a low operating voltage (1.6 V) and with a programming window that can be further extended by widening its trenched body. Second, the recombination rate is also reduced, thereby yielding an acceptable retention time (RT) of 625.6 ms. Third, the decreased RT after a 100-ns WL/BL disturbance is improved by 33%, as compared with a conventional SGT 1T-DRAM. We, therefore, believe that this new device will become a competitive candidate for use in future DRAM cells.

An 8-Mbit 0.18-µm CMOS 1T1C FeRAM in Planar Technology

An 8-Mbit 0.18-µm CMOS 1T1C ferroelectric RAM (FeRAM) in a planar ferroelectric technology was developed. Even though the cell area of 2.48 µm2 is almost equal to that of a 4-Mbit stacked-capacitor FeRAM (STACK FeRAM) 2.32 µm2[1], the chip size of the developed 8-Mbit FeRAM, including extra 2-Mbit parities for the error correction code (ECC), is just 52.37 mm2, which is about 30% smaller than twice of the 4-Mbit STACK FeRAM device, 37.68mm2×2[1]. This excellent characteristic can be attributed to the large cell matrix architectures of the sectional cyclic word line (WL) that was used to increase the column numbers, and to the 1T1C bit-line GND level sensing (BGS)[2][3] circuit design intended to sense bit lines (BL) that have bit cells 1K long and a large capacitance. An access time of 52 ns and a cycle time of 77 ns in RT at a VDD of 1.8 V were achieved.

Modeling of ΔIBL due to random telegraph noise with considering bit-line interference in NAND flash memory

Bit-line (BL) current fluctuation (ΔIBL = high IBL − low IBL) of the trap position is modeled as a parameter of the state (program or erase) of adjacent BL cells which affects the current density distribution appreciably. To model ΔIBL, we extracted the integrated electron current density (J0 = f(z)) and the electric blockade length (Lt) by considering the effect of the interference of adjacent cells. A characteristic function (g(z)) which has a Gaussian functional form is defined based on Lt and the trap position within the tunneling oxide from the channel surface (xT). Finally, ΔIBL is extracted through the integration of f(z) and g(z). Our model predicts accurately the ΔIBL with the trap position as a parameter of the state of BL cells, showing good agreement with 3D simulation data.

SNM Analysis of 6T SRAM at 32NM and 45NM Technique

OBJECTIVE OF THE CHAPTER In this paper we analyze the effect of SNM dependent on different parameter in read mode and write mode. We analyze SNM of different modulation like cell ratio (CR), voltage supply (Vdd), word line (WL) and bit line (BL) by spice tools using BPTM Low Power model in different technologies. We define the read margin to characterize the SRAM cells read stability. Many researchers use only 45nm technology, but we are scaling down the technologies which is more stability for the circuit. Actually stability of SRAM cell only depends on the static noise margin (SNM) and SNM is effect the stability of SRAM cell during read operation of SRAM cells.

Area-Efficient Embedded Resistive RAM (ReRAM) Macros Using Logic-Process Vertical-Parasitic-BJT (VPBJT) Switches and Read-Disturb-Free Temperature-Aware Current-Mode Read Scheme

The design of resistive RAM (ReRAM) faces two major challenges: 1) cell area versus write current requirements and 2) cell read current (ICELL) versus read disturbance. This paper proposes ReRAM macros using logic-process-based vertical parasitic-BJT (VPBJT) switches and a corresponding cell array (VPBJT-CA), resulting in a 4.5× macro density compared to conventional NMOS-switch ReRAM for given write current requirements. To overcome temperature-dependent fluctuations in the base-emitter voltage difference (VBE) of VPBJT, we propose a temperature-aware bitline (BL) voltage bias (VBL-R) (TABB) scheme to provide current-mode sensing with 4.7× larger ICELL and 1.6× faster read speeds. Test results of fabricated 0.18 μm 1 Mb and 65 nm 2 Mb VPBJT ReRAM macros confirm the efficacy of the temperature-aware VBL-R, resulting in sub-5-ns random read access times.

A novel high-density embedded AND-type split gate flash memory

A new high-density AND-type split gate (ASG) flash memory realized by the Taiwan Semiconductor Manufacturing Company (TSMC) 0.18 µm embedded flash process has been successfully demonstrated and fabricated. This ASG flash memory has a pair of symmetric floating gates for performance of 2 bits/cell. By device and process optimization, this cell can operate via highly efficient source side injection (SSI) and Fowler–Nordheim (FN) tunneling mechanisms for program and erase, respectively. Moreover, ASG flash memory significantly shrinks 50% of the unit cell size by sharing word line (WL) and eliminating bit line (BL) contact. Since the ASG flash memory cell and process used are inherited from proven split-gate technology, this work also provides a highly reliable solution for high-density embedded flash application.

Effect of Adjacent Bit-Line Cell Interference on Low Frequency Noise in NAND Flash Memory Cell Strings

The effect of adjacent bit-line (BL) interference on low frequency in 26 nm NAND flash memory was characterized. With the program (P) and erase (E) states of adjacent cells, current fluctuation (deltaI(BL)) and corner frequency (f(c)) of Lorentzian spectrum were changed. DeltaI(BL) due to RTN ranges from approximately 67.3 nA to approximately 45.9 nA with 4 different modes (P/P, P/E, E/P, E/E) of the state of adjacent cells and f(c) ranges from 48 Hz to 89 Hz. Using measured deltaI(BL) and extracted capture (tau(c)) and emission times (tau(e)) with 4 different modes, we calculated tau and f(c), and extracted the position of a trap in the channel width direction with deltaI(BL) and simulated data. The calculated data showed excellent agreement with measured spectra. Finally, we prepared energy band diagrams in P/P and P/E modes using 3-D device simulation and clarified the effect of adjacent bit-line cell interference. The control gate bias is slightly higher in P/P mode than P/E mode, and then trap energy in P/P mode is relatively lower than that in P/E mode, resulting in shorter capture time in P/P mode.

Suppression of Inhibit Cell &lt;I&gt;V&lt;/I&gt;&lt;SUB&gt;th&lt;/SUB&gt; Disturbance in Three Dimensional Stack NAND Flash Memory

In this work, we characterize inhibit cell Vth disturbance related to the 3D stack NAND channel boosting during program and propose a new method to suppress the hot carrier injection related disturbance. The hot-carrier effect on program inhibit string is arisen from the potential difference between the highly boosted channel and turned-off bit line (BL) selection device which is directly connected to the boosted channel. In the proposed method by us, electrons are flown to the channel with the edge word line (WL) biased initially at a Vpass before channel cut-off. Then the highly boosted channel potential decreases to some extent due to the re-distribution of excess electrons after channel cut-off. Consequently, when we apply the proposed method, large disturbed cell Vth in the inhibit strings for high Vpass is well controlled by suppressing hot-carrier generation, which leads to the higher pass voltage during both program and read operations while keeping reliable cell operations for 3D stack NAND.

8T SRAM Cell Design for Dynamic and Leakage Power Reduction

his paper addresses a, novel eight transistor (8T) CMOS SRAM cell design to enhance the stability and to reduce dynamic and leakage power. For the validation of proposed 8T SRAM cell, compared results with reported data. The parameters used in the proposed cell are comparable to the existing 8T SRAM cell at same technology and design rules. The stability of the proposed cell has been analyzed using N-curve metrics. Write operation is achieved in the proposed 8T SRAM cell by charging / discharging single Bit Line (BL), which results in reduction of dynamic power consumption. The proposed 8T SRAM cell has achieved 38.33% dynamic power reduction and 25.31% reduction in leakage power comparing with the reported data of 8T SRAM cell, which validate the desired design approach.

Impact of Disturb on Retention Time in Single FBRAM Cells

This manuscript presents an investigation of the wordline (WL) and bitline (BL) voltage disturb based on a single floating body random access memory (FBRAM) cell. It is found that several physical mechanisms can disturb the stored charge either fully or partially. The worst cases for disturb are shown and the disturb window for BL and WL are characterized for further operating condition optimization. Moreover, it is shown that in the very dense memory coupling between bitlines or wordlines will spread the disturb even to cells which are not sharing the same BL and WL.

Novel Field Effect Diode Type Vertical Capacitorless One Transistor Dynamic Random Access Memory Cell with Negative Hold Bit Line Bias Scheme for Improving the Hold Characteristics

In this paper, the novel field effect diode (FED) type vertical capacitorless one transistor dynamic random access memory (1T-DRAM) cell with negative hold bit line (BL) voltage (VBL) scheme is proposed. In comparison with the conventional planar type, the proposed vertical type with negative hold VBL scheme shows excellent static and disturb retention time. The proposed vertical type memory cell with negative hold VBL scheme achieves 1,000 times longer static retention time and 104 times longer BL disturb retention time at 85 °C than that of the conventional planar type. Furthermore, the proposed vertical type memory cell has a small cell size of 4F2 due to its stacked vertical structure. The proposed FED type vertical capacitorless 1T-DRAM cell with negative hold VBL scheme is shown to be an excellent candidate for stand-alone and embedded memory applications and extends scaling limitations.

Characterization of Random Telegraph Noise Generated by Process- and Cycling-Stress-Induced Traps in 26 nm NAND Flash Memory

We characterized normalized noise power density (SI/IBL2) and bit-line (BL) current fluctuation (ΔIBL) using traps generated applying cycling stress in 26 nm NAND flash memory. The ΔIBL, SI/IBL2, and capture (τc) and emission times (τe) of random telegraph noise (RTN) were measured before and after cycling stress, respectively. With cycling stress, traps were generated, and SI/IBL2 and ΔIBL were increased significantly. The τc and τe of RTN after cycling stress are similar with to those before cycling stress. RTN was characterized in terms of the trap position in the three-dimensional space (xT, yT, and zT) of the tunneling oxide and trap energy (ET). three-dimensional technology computer-aided design (TCAD) simulation was used to determine the position of zT through the effect of adjacent BL cells.

A High-Speed 7.2-ns Read-Write Random Access 4-Mb Embedded Resistive RAM (ReRAM) Macro Using Process-Variation-Tolerant Current-Mode Read Schemes

ReRAM is a promising next-generation nonvolatile memory (NVM) with fast write speed and low-power operation. However, ReRAM faces two major challenges in read operations: 1) low read yield due to wide resistance distribution and 2) the requirement of accurate bit line (BL) bias voltage control to prevent read disturbance. This study proposes two process-variation-tolerant schemes for current-mode read operation of ReRAM: parallel-series reference-cell (PSRC) and process-temperature-aware dynamic BL-bias (PTADB) schemes. These schemes are meant to improve the read speed and yield of ReRAM, while taking read disturbance into consideration. PSRC narrows the reference current distribution to achieve high read yield against resistance variation. PTADB achieves small fluctuations in BL bias voltage to prevent read disturbance, while providing rapid BL precharge speeds. This study fabricated a 4-Mb ReRAM macro to confirm the effectiveness of the proposed schemes for both SLC and MLC operations. The fastest sub-8-ns (7.2 ns) read-write random access time among megabit scaled embedded NVM macros has been demonstrated.

An Offset-Tolerant Fast-Random-Read Current-Sampling-Based Sense Amplifier for Small-Cell-Current Nonvolatile Memory

Decreasing read cell current (ICELL) has become a major trend in nonvolatile memory (NVM). However, a reduced ICELL leaves the operation of the sense amplifier (SAs) vulnerable to bitline (BL) level offset and SA input offset. Thus, small- ICELL NVMs suffer from slow read speed or low read yield. In this study, we propose a new current-sampling-based SA (CSB-SA) to suppress the offset due to device mismatch, while maintaining tolerance for insufficient precharge time. These features enable CSB-SA to achieve a read speed 6.3 ×-8.1× faster than previous SAs, for sensing 100 nA ICELLs on a 2 K-cell bitline. We fabricated a CMOS-logic-compatible, 90 nm, 512 Kb OTP macro, using the CSB-SA. This OTP macro achieves a random access time of 26 ns for reading sub-200 nA ICELL. Measurements confirm that this 90 nm CSB-SA is also capable of sub-100 nA sensing.

Low-Voltage Embedded NAND-ROM Macros Using Data-Aware Sensing Reference Scheme for VDDmin, Speed and Power Improvement

Density-prioritized memories such as NAND-ROM require a longer single-ended bitline (BL) sensing scheme to maintain high cell array efficiency and therefore suffer from a reduced BL sensing margin at ultra-low supply voltages (VDD) for read-0. This is the result of 1) reduced BL discharge driving current due to limited cell size and driving voltage; and 2) a larger BL false drop noise for read-1. This study proposes a data-aware sensing reference (DASR) scheme, capable of maintaining sensing margins for both read-0 and read-1 under given timing constraints. The key mechanism involved in maintaining the sensing margin is the adaptive changing of the reference voltage (VREF), such that the sensing headroom or potential range (VBL-VREF) for read-1 and read-0 overlap, as in differential BL sensing. Two 256 Kb DASR NAND-ROM macros, with and without code-inversion schemes, were fabricated using a 90 nm bulk CMOS logic process. The 256 Kb DASR NAND-ROM macros are functional down to 0.25 V. DASR also increases the access speed by 66.7% at 0.31 V VDD, compared with the conventional approach without the proposed DASR scheme.

An 8 Mb Multi-Layered Cross-Point ReRAM Macro With 443 MB/s Write Throughput

An 8-Mb multi-layered cross-point resistive RAM (ReRAM) macro has been developed with 443 MB/s write throughput (64-bits parallel write per 17.2-ns cycle), which is almost twice as fast as competing methods. It uses the fast switching performance of TaOx ReRAM and a new write architecture to reduce the sneak current in a cross-point cell array structure based on an 0.18-μm process. First, a bidirectional diode as a memory cell select element is developed to reduce the sneak current. Second, PMOS and NMOS are used select transistors in the source follower to realize stable switching for the selected cell in the multi-layered cross-point structure. Third, a hierarchical bitline (BL) structure is employed with a short bitline. Fourth, multi-bit write architecture is developed to realize fast write operation and to suppress the sneak current.

Design of 32-bit differential paired eFuse OTP memory in a form of two-dimensional array

A differential paired eFuse OTP (one-time programmable) memory cell which can be configured into a 2D (two-dimensional) eFuse cell array was proposed. The sensible resistance of a programmed eFuse link is a half smaller than that of the single-ended counterpart and BL datum can be sensed without a reference voltage. With this 2D array of differential paired eFuse OTP memory cells, we design a 32-bit eFuse OTP memory IP. We use a sense amplifier based D F/F circuit as the BL (bit-line) SA (sense amplifier) and design a sensing margin test circuit with a variable pull-up load. It is confirmed by the function test that the designed 32-bit OTP memory IP functions normally on 30 sample dies.

The Effect of Adjacent Bit-Line Cell Interference on Random Telegraph Noise in nand Flash Memory Cell Strings

The effect of adjacent bit-line (BL) cell interference on BL current fluctuation (ΔIBL = high IBL - low IBL) due to random telegraph noise (RTN) in floating-gate nand Flash cell strings is characterized. It was found that the electron current density (Je) of a read cell can be appreciably different depending on the position in the channel width direction because of the interference from adjacent BL cells. The interference can be controlled by the state (program or erase) of the adjacent cells. We verified that ΔIBL due to RTN increases as a high-Je position is controlled to be close to a trap position in 32-nm nand Flash memory strings. Finally, it was also shown that the adjacent cell interference affects not only ΔIBL but also the ratio of capture and emission time constants [ln(τc/τe)].