Bit-line Sense Research Articles

An asymmetrically controlled sense amplifier with boosted sensing voltage difference for low-voltage and high-density DRAM

The transistor threshold voltage mismatch and sensing noise are larger with technology scaling, while the sensing voltage difference of bit-line sense amplifier becomes smaller. Though various offset calibration techniques have been adopted in bit-line sense amplifiers to compensate for the offset mismatch, sensing offset and noise are still critical issues to limit the sensing margin. This brief proposes a bit-line sense amplifier with asymmetrically controlled isolation devices to solve the sensing offset and sensing noise problems simultaneously. Being biased to the calibration point, the target inverter acts as an amplifier with a large voltage gain (AV) to boost the sensing voltage difference, making the sensing voltage difference of the proposed amplifier be 1 + |AV| times that of a conventional latch-type sense amplifier. And the pre-sensing operation performs in parallel with boosting to suppress the sensing noise, without additional time and area consumption. By offset calibration and voltage difference boosting techniques, the proposed design has suppressed the sensing noise and enhanced the sensing margin. All designs are implemented on SMIC 40-nm technology, operating at a supply voltage of 1.05 V or less. The proposed sense amplifier has reduced the standard deviation of the decision threshold voltage to 0.62× and improved the sensing yield by 17.96%. In addition, the boosted sensing voltage difference speeds up the sensing stage, compensating for the pre-sensing time by 36%. Keeping the same number of transistors as the prior offset mismatch calibration sense amplifier, the proposed sense amplifier with improved sensing margin is suitable for low-voltage and high-density DRAM.

Fast and Efficient Offset Compensation by Noise-Aware Pre-Charge and Operation of DRAM Bit Line Sense Amplifier

This brief proposes fast and efficient offset compensation for a DRAM bit-line sense amplifier. Precharging the sense amplifier under the same conditions as the initial offset compensation eliminates the deterministic offset leaving a small stochastic offset to be cured during the compensation step. The compensated offset is maintained throughout the subsequent charge sharing and sensing periods by keeping the noise environment constant as a compensation step to prevent an additional offset from being introduced after compensation. Fast and reliable offset compensation is confirmed by yield analysis in 256 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> 288 DRAM cell array using extensive Monte Carlo simulation. Even when the offset compensation time is shortened to 2 ns, no yield drop is expected while with conventional amplifiers a sensing failure is estimated at 47.5%. An additional 1 ns reduction in charge sharing time is possible if a careful power delivery network is provided with the proposed sense amplifier.

Imbalance-Tolerant Bit-Line Sense Amplifier for Dummy-Less Open Bit-Line Scheme in DRAM

In a conventional open bit-line scheme of DRAM, the edge subarrays (MATs) located at both ends of the cell array block contain alternated real and dummy bit-lines, unavoidably leading to an additional area overhead. To reduce the area overhead, one edge MAT can be eliminated by converting the dummy bit-lines of the other edge MAT into real bit-lines. This strategy causes the conventional bit-line sense amplifiers (BLSAs) in the MATs located at both ends of the cell array block to have a much smaller complementary bit-line capacitance than a true bit-line capacitance. Thus, the sensing operation of a conventional BLSA with this unbalanced bit-line capacitance experiences various problems: sensing voltage decrease, data flipping, and asymmetric equalization. To solve these problems, we propose a novel sensing circuit that can operate effectively even under unbalanced bit-line capacitance, thus suggesting the possibility of an open bit-line scheme without dummy bit-lines. Our proposed dummy-less open bit-line scheme can save approximately 4% of the array height. Compared with the conventional unbalanced BLSA, the proposed BLSA increases the sensing voltage by more than 100%, reduces the voltage peaks by 30% during the data transfer, and reduces equalization time by 1.2 ns in HSPICE Monte Carlo simulation.

Array Design of High-Density Emerging Memories Making Clamped Bit-Line Sense Amplifier Compatible with Dummy Cell Average Read Scheme

Array Design of High-Density Emerging Memories Making Clamped Bit-Line Sense Amplifier Compatible with Dummy Cell Average Read Scheme

A Parasitics-Induced Failure Mechanism for Transistors in the Bit-Line Sense Amplifier Region of DDP DDR3 DRAM During a CDM Event

In the charged-device model (CDM) test, the peak current of the CDM is almost the same if the same package is used. Therefore, it is difficult to understand the reasons for the reduction in the CDM level of double-die package (DDP) DRAM achieved by stacking the same die and package to 30% of that of single-die package (SDP) DRAM. In this study, we analyze the CDM failure phenomenon in DDP DRAM, identify the root cause, and propose a redistribution layer (RDL) design to enhance the immunity of the CDM. To investigate the cause of the failure phenomenon, an emission test and a physical analysis were performed, and the gate oxide breakdown of a column-selection line (CSL) transistor in the sense amplifier was determined. A CDM simulation was performed after constructing a circuit in the CDM critical path to the vulnerable pin, including the CSL transistor. From the simulation results, the root cause of CDM failure was identified with the inductive peaking phenomenon due to the RDL and voltage coupling through the coupling capacitance between the RDL and CSL metal line. In other words, the voltage stress of the CSL transistor increases as the inductance and coupling capacitance increase, and the tolerable CDM immunity worsens. Moreover, no CDM failure occurs in the power and ground pins, which can be described as a low inductance of the power and ground RDL line. The reductions in the RDL inductance and the coupling capacitance of the RDL and the CSL transistor were experimentally determined for the RDL designs. As a result, the immunity of the CDM improves from 500 V to 600 and 800 V in the inductance- and coupling-capacitance-reduced designs, respectively.

A Bit-Line Voltage Sensing Circuit With Fused Offset Compensation and Cancellation Scheme

A systematic offset voltage occurs in sense amplifiers for SRAMs, mainly due to the mismatch between the threshold voltages of MOS transistors. This offset affects the reading operations of SRAMs in terms of accuracy, delay and power consumption. In this brief, a bit-line voltage sense amplifier is presented, which combines offset compensation and cancellation features. The circuit operations are carried out in four phases, in which two CMOS amplifiers are used as line buffers and they are pre-charged in the high voltage gain region in order to reduce the effects of the offset. The proposed sense amplifier has been designed and prototyped in 180-nm CMOS technology. It is capable to correct a voltage offset up to 100 mV and exhibits a minimum access time of 58 ps. These results overcome other solutions in applications where sub-threshold operations are not required and an aggressive voltage scaling is not convenient.

Inverted bit‐line sense amplifier with offset‐cancellation capability

An inverted bit-line sense amplifier (BLSA) equipped with offset compensation capability for low-power DRAM applications is proposed. The sequential operation of the inverted BLSA allows us to eliminate the edge dummy array in an open bit-line structure resulting in 1.7% less total chip area despite of 10% area penalty of the proposed BLSA occupied by extra switches. For 8-Gb DRAM in 20-nm class technology, the read failure induced by Vth variability is completely removed due to the offset cancellation. The proposed BLSA maintains the gradual increase of the sensing delay when decreasing the power supply down to 0.6 V, while intrinsic read fail prevails below 0.9 V with the conventional one.

Source Line Sensing in Magneto-Electric Random-Access Memory to Reduce Read Disturbance and Improve Sensing Margin

A source line sensing (SLS) scheme is presented, along with a corresponding memory core circuit architecture, for the sensing operation of magneto-electric random-access memory (MeRAM). Compared to a conventional bit-line sensing (BLS) scheme, the proposed SLS, which exploits the voltage-controlled magnetic anisotropy (VCMA) effect, applies a voltage across the magneto-electric tunnel junction (MEJ) with an opposite polarity. The SLS significantly reduces read disturbance and increases the sensing margin due to the enhanced coercivity of the bit during the read operation. Experimental data demonstrate that the thermal stability of nanoscale MEJs increases up to 2 times during the SLS operation compared with conventional BLS. An MEJ compact model based the SLS simulation shows that read disturbance improves by a factor greater than 10 ${}^{9}$ fJ/V $\cdot $ m and the sensing margin increases up to 3 times in the MEJ with the large VCMA coefficient $\left(>\text{100} \text{fJ}/\text{V}\cdot\text{m}\right)$ .

Read Bitline Sensing and Fast Local Write-Back Techniques in Hierarchical Bitline Architecture for Ultralow-Voltage SRAMs

Voltage scalable decoupled SRAMs operating at a subthreshold region have various challenges, such as deteriorated read bitline (RBL) swing resulting in read sensing failure and degraded cell stability due to the half-select write. This paper proposes an equalized bitline scheme to eliminate the leakage dependence on data pattern and thus improves RBL sensing and its resilience against process, voltage, and temperature variations. In addition, we propose a fast local write-back (WB) technique to implement a half-select-free write operation. With hierarchical bitline architecture, it facilitates a local read and a subsequent fast WB action to secure the original data without performance degradation. A 16-kb SRAM test chip has been fabricated in a 65-nm CMOS technology and achieved the minimum operating voltage of 0.24 V with a read access time of 4.88 μs.

Built-In Binary Code Inversion Technique for On-Chip Flash Memory Sense Amplifier With Reduced Read Current Consumption

The bit-line sense amplifier (S/A) for on-chip flash memory compares cell current with reference current to identify data that are programmed. The S/A for 0 (erased) cell data consumes a large sink current, which is greater than off-current for 1 (programmed) cell data. This brief proposes a built-in write/read path based on binary inversion methods to reduce the sensing current of S/A. An original binary code is programmed into flash memory with an inverted binary code based on the proposed bit inversion techniques. The de-inversion hardware, which is implemented with small logic gates to restore original binary data, only consumes logic current instead of analog sink current in the S/A. The proposed techniques are evaluated for the DSPStone benchmark and are applied to the modified S/A for ARM Cortex-M3-based microcontroller with 128-kB on-chip flash memory based on a 0.18-um EEPROM technology. The circuit-level simulation result for the DSPStone benchmark shows that a newly implemented chip with the S/A based on the proposed technique consumes approximately less than 22% of the operating power that conventional S/A uses.

A Current Compensation Bitline Sense Amplifier

A new bitline sense amplifier (SA) for improving performance in the presence of current compensation is analyzed. The proposed scheme utilizes a new leakage current compensation circuit, resulting in a 42.9% reduction in the delay from bitline discharge to the date been read out. Thus, this is very important for higher performance application, especially under advanced technology process.

A Sensing Noise Compensation Bit Line Sense Amplifier for Low Voltage Applications

A new bit-line sense amplifier for improving performance in the presence of data-pattern-dependent sensing noise is analyzed. The proposed scheme utilizes the power drop phenomenon in the sense amplifier driving line, resulting in an 81.5% reduction in the amplitude of data-pattern-dependent sensing noise. It is very important to accurately model power drop in compensating data-pattern-dependent sensing noise. Simulation and measurement of the proposed sensing scheme show improvement of sensing noise over a conventional bit-line sense amplifier. Moreover, the type of sense amplifier driver circuit significantly affects the magnitude of the improvement. The impact of the sense amplifier driver layout is analyzed in order to better utilize the proposed scheme. Finally, an optimum data pattern noise insensitive sense amplifier and driver are proposed.

A Sub-200-mV Voltage-Scalable SRAM With Tolerance of Access Failure by Self-Activated Bitline Sensing

The access timing control of low-voltage static random access memory cells encounters crucial challenges in the presence of within-die (WID) variations, which induce severe delay mismatches between the timing-reference circuit and the bitlines. Prevention of early activation of sense amplifiers (SAs) is thus required to improve the yield. This brief proposes a novel SA-activation scheme by sensing differential bitlines locally and concurrently. The proposed structure effectively tolerates the WID variations and supports dynamic voltage scaling down to the subthreshold supply voltage. Measurement results show that the fabricated 8-kb test chips using 90-nm technology can be operated at the supply voltage range from 1 V (nominal V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dd</sub> ) to 0.16 V. The maximum operating frequency at 0.16 V is up to 200 kHz.

Clocked-sense-amplifier-based smart-pixel optical receivers

We introduce the concept of synchronous smart-pixel optical receivers, and present the first use of a clocked-sense amplifier as a smart-pixel optical receiver. Such a receiver uses the controlled application of positive feedback to obtain low-power compact digital amplification. We describe the design and simulation of two types of optical receivers based on a clamped bit-line sense amplifier (CBLSA), and a conventional sense amplifier (CSA). Both of these circuits have been realized in 0.8 micron-linewidth foundry CMOS with hybrid-bonded GaAs-AlGaAs MQW detectors and modulators attached to the circuit. Operation in excess of 750 Mb/s is demonstrated, within a layout area of 44 μm×22 μm, with a bias-dependent estimated power dissipation of 1 to 2 mW. Operation with one or two input beams is possible, with approximate minimum detected photocurrent levels at 320 Mb/s of 8 μA (/spl sim/100 fJ) for single-beam operation and 2.5 μA/beam (/spl sim/30 fJ/beam) for two-beam operation, all in the CBLSA-based circuit.

SIMULTANEOUS SWITCHING NOISE ANALYSIS OF A 16 MB × 9 DRAM SIMM MEMORY MODULE

HSPICE simulations have been performed for a 16 Mb×9 SIMM memory module and the simultaneous switching noise has been investigated. The SPICE model of the SIMM memory module is made up of a PCB circuit model and a simplified DRAM chip model. To keep the SPICE simulation time within reasonable bounds, a simplified circuit model of a 16 Mb DRAM chip was generated by keeping the basic physical DRAM structure in the model including the bit-line sense amplifiers. The parameter values of the circuit elements in the simplified DRAM chip model were tuned to fit the measured transient supply current waveform of a commercial 16 Mb DRAM chip. The SIMM module was placed on a fabricated motherboard PCB and the simultaneous switching noise voltage on the motherboard VSS plane was measured. Good agreement between measurements and HSPICE simulations were observed.

BiCMOS circuit technology for high-speed DRAMs

A BiCMOS circuit technology featured by a novel bit-line sense amplifier has been developed. The bit-line sense amplifier is composed of a BiCMOS differential amplifier, the impedance-converting means featured by the CMOS current mirror circuit or the clocked CMOS inverter between the bit line and the base node of the BiCMOS differential amplifier, and a conventional CMOS flip-flop. This technology can reduce the access time to half that of a conventional CMOS DRAM access time. Applied to a 1-kb DRAM test chip, a new BiCMOS circuit technology was successfully verified. Furthermore, the sensitivity and area penalty of the new BiCMOS bit-line sense amplifier and future applications to megabit DRAMs are discussed. >

A high-speed sensing scheme for 1T dynamic RAMs utilizing the clamped bit-line sense amplifier

A clamped-bit-line sense amplifier (CBLSA) capable of very high-speed operation in one-transistor (1T) DRAM applications has been developed. Results from an experimental test chip demonstrate that the speed of the new circuit is insensitive to bit-line capacitance. Circuit speed is also found to be insensitive to the initial bit-line difference voltage. The CBLSA maintains a low impedance fixed potential on the bit lines during sensing, virtually eliminating sensitivity to inter-bit-line noise coupling and minimizing power supply bounce during sensing. The new sense amplifier operates at higher speeds than conventional circuits and still dissipates less power.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>