Bit-flipping Research Articles

Implementation for Two-Stage Hybrid Decoding for Low Density Parity Check (LDPC) Codes

ABSTRACT LDPC codes are gaining high attention in Channel Coding field these days. However, one of the main problems facing usage of these codes in communication systems is the high complexity decoding scheme that results in high decoding delay. Such delay is not acceptable in some applications that depend on time such as video transmission. This paper presents hardware implementation technique for Two-Stage Hybrid decoder resulting in better complexity and delay. Also, it shows comparison between soft, hard and hybrid decoding techniques in terms of memory usage, and delay time as to be used for real implementation for some applications such as DVB-S2. Keywords Channel Coding, LDPC, VHDL, Hybrid decoding. 1. INTRODUCTION The first Low-Density Parity Check Code (LDPC) was discovered by Gallager [1], [2] in 1960s where this code proved the extraordinary performance with iterative decoding that was very close to Shannon limit which is difficult to reach. LDPC codes are used in many applications such as DVB-S2 [3], which is a standard for Digital Video Broadcasting–Satellite-Second Generation because of its excellent Bit Error Rate (BER) performance. These codes are expected to be included in many future standards as well as to replace many existing channel coding techniques. There are many types of LDPC decoding algorithms that have good performance with acceptable delay time. These algorithms can be classified into soft-decision decoding algorithm such as the Sum-Product Algorithm (SPA) and hard-decision decoding algorithm such as Bit-Flipping (BF) algorithm which was discovered by Gallager. The Bit-Flipping algorithm has many modified versions [4], [5], [6] that have better BER performance compared to the original Bit-Flipping algorithm. The good BER performance of SPA comes on the expense of the high complexity which increases the delay time for the used design. Such high delay is considered as a drawback for some applications especially for those who are greatly affected by the delay such as video and audio transmission. On the other side, hard decision such as Bit Flipping algorithm and its modified versions have limited BER performance with lower complexity and delay time if compared to (SPA). So, Two-Stage Hybrid decoding algorithm proposed in [7] was used as a new decoding algorithm, where this algorithm provides a trade-off algorithm between hard and soft-decision algorithms and has better performance compared to that of BF and less complexity and delay time compared to that of SPA. This paper shows an FPGA design of the real hardware implementation for Two-Stage Hybrid decoder with comparison to SPA, and BF in terms of memory usage and delay time. The rest of the paper is organized as follows. Section (2) presents the background on SPA and BF algorithms. These algorithms provide the basis for the Two-Stage Hybrid decoding. Also, this section presents the existing Two-Stage Hybrid algorithm and how it is composed of SPA as the first stage and BF as the second stage. Section (3) introduces the hardware implementation technique for the three algorithms with showing the procedure of each algorithm to compare between their performances. Section (4) includes typical simulation results for the three decoders. Also, comparison between the three decoders is shown with respect to memory usage and delay time. Finally, conclusion and future work are presented in Section (5).

Modified Bit-Flipping Decoding of Low-Density Parity-Check Codes

A novel bit-flipping (BF) algorithm with low complexity for high-throughput decoding of low-density parity-check (LDPC) codes is presented. At each iteration, a novel threshold pattern is used to determine the code bits whether to be flipped or not, and the flipping error probability is effectively decreased. Compared with the weighted BF algorithm and its modifications, the modified BF algorithm has significantly lower complexity and decoding time. Through simulations the proposed BF algorithm is shown to achieve excellent performance and fast convergence speed while maintaining significantly low complexity thus facilitating high-throughput decoding.

Multiple candidates bit‐flipping algorithms for decoding LDPC codes

AbstractThis letter proposes an effective scheme to improve the error performance of conventional bit‐flipping (BF) algorithms for decoding low‐density parity‐check codes. The proposed scheme, which is referred to as the multiple‐candidates (MC) scheme, constructs a set of candidates for the starting vector of the iterative decoding procedure. Each candidate vector in the set is generated by randomly flipping several high error probability bits of the original hard‐decision vector. Simulation results show that two typical BF algorithms applying the MC scheme achieve noticeable gains over the original BF algorithms with moderate increase in computational cost. Copyright © 2012 John Wiley & Sons, Ltd.

Channel-independent weighted bit-flipping decoding algorithm for low-density parity-check codes

In this study, a new method for improving hard-decision bit-flipping (BF) decoding is proposed for low-density parity-check codes. The flipping criterion is derived theoretically from the soft-decision belief-propagation decoding algorithm. The proposed BF decoding algorithm is channel independent and is improved by introducing a more efficient method for computing the reliability of the parity checks. Extensive simulations are provided to demonstrate the efficiency of the proposed algorithm. Simulation results show that the proposed algorithm can achieve about 1.6 dB coding gain improvement at BER 10 -5 while reducing up to 53% iterations for decoding and maintaining low-decoding complexity, compared with the conventional weighted BF algorithm.

Hybrid decoding scheme based on WED and BF algorithms

This contribution studies the application of Weighting Erased Decoding (WED) algorithm in the decoding of LDPC codes. WED is a kind of maximum likelihood algorithm used in the decoding of linear block codes with quantized channel outputs. Based on WED algorithm and Bit Flipping (BF) algorithm, a hybrid decoding scheme is proposed, which takes advantage of the simplicity of BF and the utilizing of reliability of received symbols. Simulation results show that the proposed scheme is feasible and effective, but the performance improvement is limited and depends on a parameter similar to the minimum Hamming distance in block codes.Click

Adaptive Threshold Technique for Bit-Flipping Decoding of Low-Density Parity-Check Codes

The bit-flipping (BF) algorithm for decoding of low-density parity-check (LDPC) codes requires less complex hardware than other decoding algorithms, but its error correcting performance needs to be improved. In this letter, a threshold adaptation scheme is applied to BF algorithm based decoding of LDPC codes. Our experiments show that the optimal threshold value for BF depends on the error conditions, and threshold adjustment during decoding helps to prevent meaningless no-flipping iterations. Based on these statistical observations, the adaptive threshold technique is proposed to pursue both the maximum error correcting capability and the fastest decoding convergence.

Gradient descent bit flipping algorithms for decoding LDPC codes

A novel class of bit-flipping (BF) algorithm for decoding low-density parity-check (LDPC) codes is presented. The proposed algorithms, which are referred to as gradient descent bit flipping (GDBF) algorithms, can be regarded as simplified gradient descent algorithms. The proposed algorithms exhibit better decoding performance than known BF algorithms, such as the weighted BF algorithm or the modified weighted BF algorithm for several LDPC codes.

VLSI Implementation of a High-Throughput Soft-Bit-Flipping Decoder for Geometric LDPC Codes

VLSI-based decoding of geometric low-density parity-check (LDPC) codes using the sum-product or min-sum algorithms is known to be very difficult due to large memory requirement and high interconnection complexity caused by high variable and column degrees. In this paper, a low-complexity high-performance algorithm is introduced for decoding of such high-weight LDPC codes. The developed soft-bit-flipping (SBF) algorithm operates in a similar way to the bit-flipping (BF) algorithm but further utilizes reliability of estimates to improve error performance. A hybrid decoding scheme comprised of the BF and SBF algorithms is also proposed to shorten the decoding time. Parallel and pipelined VLSI architecture is developed to increase the throughput without consuming much chip area. The (1057, 813) and (273, 191) projective-geometry LDPC codes are used for performance evaluation, and the former is designed in VLSI.

Hybrid decoding of finite geometry low-density parity-check codes

For finite geometry low-density parity-check codes, heavy row and column weights in their parity check matrix make the decoding with even min–Sum (MS) variants computationally expensive. To alleviate it, the authors present a class of hybrid schemes by concatenating a parallel bit flipping (BF) variant with an MS variant. Meanwhile, the BF variant, with much less computational complexity, attempts decoding the receive sequence firstly, and only decoding failure of the BF variant triggers the MS variant. Hence the BF variant performance heavily impacts the overall hybrid scheme, which is illustrated in two case studies. Computational and hardware complexity is then elaborated to justify the feasibility of the hybrid schemes. In most SNR region of interest, without compromising performance or convergence rate, the proposed hybrid schemes can save substantial computational complexity when compared with the MS variant decoding alone.

Weighting Factor Estimation Method for Peak Power Reduction Based on Adaptive Flipping of Parity Bits in Turbo-Coded OFDM Systems

In this paper, we propose a weighting factor (WF) estimation method for peak power reduction (PPR) based on adaptive flipping of parity carriers in a turbo-coded orthogonal frequency-division multiplexing (OFDM) system. In this PPR scheme, the peak-to-average power ratio of a turbo-coded OFDM signal is reduced with adaptive flipping of the phase of the parity carriers corresponding to the WFs. At the receiver, the WFs are estimated at a turbo decoder by exploiting the redundancy of an error-correcting code using no extra side information. The proposed WF estimation method is based on an iterative decoding of the turbo code, i.e., the turbo decoder provides not only error correction capability but the WF estimation function as well. When the proposed WF estimation method is used for the system using a turbo code with constraint length <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">K</i> = 4 and a code rate of <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> = 1/2, the instantaneous power of the OFDM signal at the complementary cumulative distribution function of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-4</sup> can be reduced by about 2.1 dB through the application of the PPR scheme. When the bit error rate (BER) performance is evaluated as a function of the peak signal-to-noise power ratio (PSNR), the proposed method achieves better BER performance than the case without the PPR in an attenuated 12-path Rayleigh fading condition. The improvements in BER performance as a function of PSNR are about 1.1, 2.0, and 2.1 dB at BER = 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-4</sup> for turbo-coded OFDM signals using QPSK, 16-state quadrature amplitude modulation (QAM), and 64-state QAM schemes, respectively.

Iterative List Decoding of Some LDPC Codes

We present an iterative list decoding algorithm for low-density parity-check (LDPC) codes. In particular we apply this decoder to a class of LDPC codes from finite geometries and show that the (73,45,10) projective geometry code can be maximum-likelihood (ML) decoded with low complexity. Moreover, the list decoding approach enables us to give a theoretical analysis of the performance. We also consider list bit-flipping (BF) decoding of longer LDPC codes.

Low-Latency Decoding of EG LDPC Codes

We describe simple iterative decoders for low-density parity-check codes based on Euclidean geometries, suitable for practical very-large-scale-integration implementation in applications requiring very fast decoders. The decoders are based on shuffled and replica-shuffled versions of iterative bit-flipping (BF) and quantized weighted BF schemes. The proposed decoders converge faster and provide better ultimate performance than standard BF decoders. We present simulations that illustrate the performance versus complexity tradeoffs for these decoders. We can show in some cases through importance sampling that no significant error floor exists.

Improved Bit-Flipping Decoding of Low-Density Parity-Check Codes

In this correspondence, a new method for improving hard-decision bit-flipping decoding of low-density parity-check (LDPC) codes is presented. Bits with a number of unsatisfied check sums larger than a predetermined threshold are flipped with a probability p /spl les/ 1 which is independent of the code considered. The probability p is incremented during decoding according to some rule. With a proper choice of the initial p, the proposed improved bit-flipping (BF) algorithm achieves gain not only in performance, but also in average decoding time for signal-to-noise ratio (SNR) values of interest with respect to p = 1.

Computation of switching noise in printed circuit boards

Simultaneous switching noise (SSN) is a phenomenon with adverse and severe effects when a large number of high speed chip drivers switch simultaneously causing a large amount of current to be injected into the power distribution grid. The effects of SSN are manifested in a variety of transient and permanent system malfunctions including the appearance of undesirable glitches on what should otherwise be quiet signal lines and the flipping of state bits in registers and memories. Current approaches for dealing with SSN are largely ad hoc, relying primarily on the ability of expert designers to postulate worst-case scenarios for the occurrence of SSN-related errors and to analyze these scenarios using pessimistic estimates of packaging parasitics. This paper takes a first step toward evolving a systematic methodology for modeling and analysis of SSN in printed circuit boards (PCB's). The presented methodology adopts a combination of macro- and micro-models which allow for a system level treatment of the problem without losing the necessary detailed descriptions of the power/ground planes, the signal traces and the vertical interconnections through vias or plated holes. This approach has been applied to a variety of PCB structures and has allowed for an effective characterization of switching noise and a comprehensive understanding of its effects on PCB performance.