VLSI Implementation of a High-Throughput Soft-Bit-Flipping Decoder for Geometric LDPC Codes

Abstract

VLSI-based decoding of geometric low-density parity-check (LDPC) codes using the sum-product or min-sum algorithms is known to be very difficult due to large memory requirement and high interconnection complexity caused by high variable and column degrees. In this paper, a low-complexity high-performance algorithm is introduced for decoding of such high-weight LDPC codes. The developed soft-bit-flipping (SBF) algorithm operates in a similar way to the bit-flipping (BF) algorithm but further utilizes reliability of estimates to improve error performance. A hybrid decoding scheme comprised of the BF and SBF algorithms is also proposed to shorten the decoding time. Parallel and pipelined VLSI architecture is developed to increase the throughput without consuming much chip area. The (1057, 813) and (273, 191) projective-geometry LDPC codes are used for performance evaluation, and the former is designed in VLSI.