Bit-flipping Research Articles

Two-Round Selection-Based Bit Flipping Decoding Algorithm for LDPC Codes

This paper presents a novel iterative reliability-based bit flipping (BF) algorithm for decoding low-density parity-check codes. The new decoder is a single BF algorithm called two-round selection -based bit flipping. It introduces the idea of a two-round selection of the flipped bit, based successively on hard and soft received channel values. In the first stage, a set of unreliable bits is identified, and then a second selection is used, to pick out among them the bit to flip. In the second round of selection, the initial belief about received signals, contributes efficiently to selecting the best candidate bit. We demonstrate through simulations over the binary-input additive white Gaussian noise channel and the Rayleigh fading channel that the proposed algorithm exhibits better decoding performance when compared with some well-known soft decision BF algorithms. A complexity analysis of the proposal and a comparison to other BF decoders are also presented.

Deep-Learning-Based Adaptive Error-Correction Decoding for Spin-Torque Transfer Magnetic Random Access Memory (STT-MRAM)

Spin-torque transfer magnetic random access memory (STT-MRAM) is a promising emerging non-volatile memory (NVM) technology with wide applications. However, the data recovery of STT-MRAM is affected by the diversity of channel raw bit error rate (BER) across different dies caused by process variations, as well as the unknown resistance offset due to temperature change. Therefore, it is critical to develop effective decoding algorithms of error correction codes for STT-MRAM. In this paper, we first propose a neural bit-flipping (BF) decoding algorithm, which can share the same trellis representation as the state-of-the-art neural decoding algorithms, such as the neural belief propagation (NBP) and neural offset min-sum (NOMS) algorithm. Hence a neural network (NN) decoder with a uniform architecture but different NN parameters can realize all these neural decoding algorithms. Based on such a unified NN decoder architecture, we further propose a novel deep learning (DL)-based adaptive decoding algorithm whose decoding complexity can be adjusted according to the change of the channel conditions of STT-MRAM. Extensive experimental evaluation results demonstrate that the proposed neural decoders can greatly improve the performance over the standard decoders, with similar decoding latency and energy consumption. Moreover, the DL-based adaptive decoder can work well over different channel conditions of STT-MRAM irrespective of the unknown resistance offset, with a 50% reduction of the decoding latency and energy consumption compared to the fixed decoder.

A Format Compliant Framework for HEVC Selective Encryption After Encoding

The security protection of Ultra-High-Definition (UHD) video is facing grand challenges due to changeable application scenarios. The video business is highly dependent on the video format structure, which makes the format compliance of the encryption algorithm essential. Existing HEVC Selective Encryption (SE) algorithms are difficult to encrypt with format compliance while independent from the encoding, which limits their practical application. In order to realize the format compliant encryption on encoded bitstream, this paper first proposes a non-diffusion rule by analyzing the coding format specification of High Efficiency Video Coding (HEVC). Following the non-diffusion rule, a Bit Flipping (BF) method and a Bit Insertion-Deletion (BID) method are proposed based on the lower bound mapping of the bypass syntax element bit coding interval. Then, considering the various binarization methods and the correlation between syntax elements when decoding, this paper proposes the Validity Principle (VP) and Independence Principle (IP) of format compliant encryption. Focusing on the binary bits of the primary bypass elements in HEVC, the encryptability of them is analyzed in detail, and the corresponding format compliant encryption schemes based on BF, BID methods are constructed. Based on the above, a Format Compliance Encryption (FCE) framework after encoding is formulated. The flexibility, security, and adaptability of the framework are analyzed. Finally, through experiments from the aspects of format compliance, encryption speed, and perception effect, the proposed methods, schemes, and framework are format compliance while ensuring the basic performance and security requirements.

Iterative Hard-Decision Decoding Algorithms for Binary Reed-Muller Codes

In this paper, novel hard-decision iterative decoding algorithms for binary Reed-Muller (RM) codes are presented. First, two algorithms are devised based on the majority-logic decoding algorithm with reliability measures of the received sequence. The bit-flipping (BF) and the normalized bit-flipping (NBF) decoding algorithms are hard-decision decoding algorithms. According to the updated hard reliability measures, the BF and NBF algorithms flip one bit of the received hard-decision sequence at a time in each iteration. The NBF decoding algorithm performs better than the BF decoding algorithm by normalizing the reliability measures of the information bits. Moreover, the BF and NBF algorithms are modified to flip multiple bits in one iteration to reduce the average number of iterations. The modified decoding algorithms are called the multiple-bits-flipping (MBF) algorithm and the normalized multiple-bits-flipping (NMBF) algorithm, respectively. The proposed algorithms have low computational complexities and can converge rapidly after a small number of iterations. The simulation results show that the proposed hard-decision decoding algorithms outperform the conventional decoding algorithm.

A Soft-Aided Staircase Decoder Using Three-Level Channel Reliabilities

The soft-aided bit-marking (SABM) algorithm is based on the idea of marking bits as highly reliable bits (HRBs), highly unreliable bits (HUBs), and uncertain bits to improve the performance of hard-decision (HD) decoders. The HRBs and HUBs are used to assist the HD decoders to prevent miscorrections and to decode those originally uncorrectable cases via bit flipping (BF), respectively. In this paper, an improved SABM algorithm (called iSABM) is proposed for staircase codes (SCCs). Similar to the SABM, iSABM marks bits with the help of channel reliabilities, i.e., using the absolute values of the log-likelihood ratios. The improvements offered by iSABM include: (i) HUBs being classified using a reliability threshold, (ii) BF randomly selecting HUBs, and (iii) soft-aided decoding over multiple SCC blocks. The decoding complexity of iSABM is comparable of that of SABM. This is due to the fact that on the one hand no sorting is required (lower complexity) because of the use of a threshold for HUBs, while on the other hand multiple SCC blocks use soft information (higher complexity). Additional gains of up to 0.53 dB with respect to SABM and 0.91 dB with respect to standard SCC decoding at a bit error rate of $10^{-6}$ are reported. Furthermore, it is shown that using 1-bit reliability marking, i.e., only having HRBs and HUBs, only causes a gain penalty of up to 0.25 dB with a significantly reduced memory requirement.

A Low-Latency BF Decoding of LDPC Codes With Dynamic Thresholds

This letter proposes a high throughput bit-flipping (BF) algorithm for regular LDPC codes with dynamic thresholds. In the iterative decoding, the flipping threshold is dynamically updated according to the previous flipping results. Compared to the exiting hard-information-based BF algorithms, the proposed algorithm can get better decoding performance. At the same time, in order to accelerate the convergence speed, we limit the number of occurrences of high thresholds which effectively reduces the invalid decoding iterations. The proposed algorithm has better decoding performance and lower average number of iterations which is suitable for the flash storage systems with low latency and high throughput requirements.

An area efficient and high throughput implementation of layered min-sum iterative construction a posteriori probability LDPC decoder.

Area efficient and high speed forward error correcting codes decoder are the demand of many high speed next generation communication standards. This paper explores a low complexity decoding algorithm of low density parity check codes, called the min-sum iterative construction a posteriori probability (MS-IC-APP), for this purpose. We performed the error performance analysis of MS-IC-APP for a (648,1296) regular QC-LDPC code and proposed an area and throughput optimized hardware implementation of MS-IC-APP. We proposed to use the layered scheduling of MS-IC-APP and performed other optimizations at architecture level to reduce the area and to increase the throughput of the decoder. Synthesis results show 6.95 times less area and 4 times high throughput as compared to the standard min-sum decoder. The area and throughput are also comparable to the improved variants of hard-decision bit-flipping (BF) decoders, whereas, the simulation results show a coding gain of 2.5 over the best implementation of BF decoder in terms of error performance.

Information Storage Bit-Flipping Decoder for LDPC Codes

Tabu-list random-penalty gradient descent bit-flipping (TRGDBF) decoder is the state-of-the-art hard-decision low-density parity-check (LDPC) decoder in terms of error-correction performance on binary symmetric channel (BSC). However, the TRGDBF decoder suffers from a long critical path caused by the global maximum-finding operation, limiting the achievable throughput. This brief proposes an information storage bit-flipping (ISBF) decoder to solve this problem. Different from the existing bit-flipping (BF) decoders which adopt serial decoding manner, in the ISBF decoder, by storing the previous decoding information, the global maximum-finding operation can be executed in parallel to other decoding operations, significantly shortening the critical path. Moreover, a nonuniform flipping rule is incorporated to achieve a better decoding performance. We also present an efficient architecture to implement the ISBF decoder. The design example demonstrates that compared to other hard-decision BF decoders, the ISBF decoder could provide both the best decoding performance and throughput on BSC.

Multi-Stage Bit-Flipping Decoding Algorithms for LDPC Codes

We present two general multi-stage (MS) bit-flipping (BF) decoding algorithms for low-density parity-check (LDPC) codes. Both algorithms consist of soft-decision (SD) and hard-decision BF decoding parts. In comparison with known MS LDPC decoders, our approach is much simpler as all stages share the same BF structure. The only complexity increase is due to the use of an adaptive stage-switching (SS) mechanism which gives near-optimal SS timing. A new design issue we address is that the first-stage algorithm’s parameter has to be re-tuned to achieve the optimal overall performance. The numerical results demonstrate that the proposed decoding methods can significantly improve the error-rate performance of the conventional SD BF decoders.

High‐throughput Bit Flipping decoder for structured LDPC codes

Low-density parity-check (LDPC) codes are predominantly used in many energy scavenging devices, data centres, and communication devices. In this work, the authors propose a high-throughput parallel bit-flipping (BF) decoder using multithreshold BF algorithm. The decoder is endowed with features including low interconnect complexity, simpler computations, and high throughput. The decoder has been synthesised in 65 nm technology for (273, 191) and (1023, 781) finite-geometry LDPC (FG-LDPC) codes. These decoders require an area of 0 . 1 and 0 . 45 mm 2 , and they achieve an average throughput of 147 . 57 and 268 . 5 Gbps and energy efficiency of 0 . 92 and 0 . 91 pJ/bit for (273, 191) and (1023, 781) FG-LDPC codes, respectively. Compared to the state-of-the-art design, the proposed designs offer 4 . 5 times higher normalised throughput.

A Probabilistic Parallel Bit-Flipping Decoder for Low-Density Parity-Check Codes

This paper presents a new bit flipping (BF) decoder, called the probabilistic parallel BF (PPBF) for low-density parity-check codes on the binary symmetric channel. In the PPBF, the flipping operation is performed in a probabilistic manner which is shown to significantly improve the error correction performance. The advantage of the PPBF also comes from the fact that no global computation is required during the decoding process and that all the computations can be executed in the local computing units and in parallel. The PPBF provides a considerable improvement of the operating frequency and complexity, compared to other known BF decoders, while obtaining a significant gain in error correction. An improved version of the PPBF, called non-syndrome PPBF is also introduced, in which the global syndrome check is moved out of the critical path and a new terminating mechanism is proposed. In order to show the superiority of the new decoders in terms of hardware efficiency and decoding throughput, the corresponding hardware architectures are presented in Section II . The application-specific integrated circuit synthesis results confirm that the operating frequency of the proposed decoders is significantly improved, compared to that of the BF decoders in the literature while requiring lower complexity to be efficiently implemented.

Classification-Based Algorithm for Bit-Flipping Decoding of GLDPC Codes Over AWGN Channels

In this letter, an improved bit-flipping (BF) decoder for generalized LDPC over AWGN channels is proposed. It takes the advantage of the fast BF decoding with only initial help from the channel soft information by introducing a classification step at first. Second, it adds an auxiliary bit in messages between the bipartite graph nodes as a tool for increasing the decision reliability and improving the performance. The reliability is presented as a tool for diminishing the effect of the generated trapping sets. The proposed classification threshold is mathematically derived, and the algorithm is revealed to surpass the various BF algorithms concerning the bit error rate performance.

Noisy Gradient Descent Bit-Flipping Decoder Based on Adjustment Factor for LDPC Codes

As a class of bit-flipping (BF) decoder, the noisy gradient descent bit flipping (NGDBF) algorithm outperforms the original GDBF and other BF algorithms. To increase the reliability of the inversion function, we propose a modified NGDBF algorithm by introducing an adjustment factor on the syndrome. Moreover, for the multi-bit flipping, we present an adaptive inversion threshold which depends on the numbers of negative bipolar syndromes. The simulation results show that our proposed algorithm outperforms the NGDBF algorithm for both single-bit and multi-bit flipping schemes.

An Efficient Combined Bit-Flipping and Stochastic LDPC Decoder Using Improved Probability Tracers

This paper presents an efficient combined bit-flipping (BF) and stochastic low-density parity-check decoder, where a BF decoder is used to achieve a reduction in decoding cycles. A node-wise probability tracer is adopted at each variable node (VN) in order to achieve a BER performance comparable to the normalized min-sum algorithm, where check-to-variable (C2V) messages are used as inputs, rather than the variable-to-check (V2C) messages adopted in previous stochastic decoders. The complexity of the VN units is greatly reduced by sharing common units used in the generation of V2C messages together with a probability tracer. The C2V-based probability tracer enables the design of a decoder that provides a short critical path. The proposed methods are demonstrated by designing a (2048, 1723) decoder that is implemented in a 90 nm process. A total of 1460 K logic gates are integrated in a decoder that has an area of 4.12 $\mbox{mm}^2$ and achieves a coded throughput of 39.3 Gb/s at a clock frequency of 749 MHz. To the best of the authors’ knowledge, the proposed decoder achieves the best normalized throughput-to-area ratio among the stochastic decoders reported in the open literatures.

Two-Side State-Aided Bit-Flipping Decoding of Generalized Low Density Parity Check Codes

A modified bit-flipping (BF) decoding algorithm is proposed for hard-decoding of generalized low- density parity-check codes over binary channels. This approach introduces an extra bit between the variable nodes and constraint nodes representing the decision reliability of each node. The local decoding failure is also analyzed to provide a reasonable treatment for the most of its causes. The approach is not in the direction of constructing codes with minimum trapping sets, but to reduce their effect in the decoder at a cost of little increase in the resources. The algorithm, which is called two-side state-aided BF, is shown by simulations to outperform previous BF algorithms in terms of error performance.

Comparison of Technologies for the Implementation of SBF Decoder for Geometric LDPC Codes

Background/Objectives: The main aim of the proposed design is to optimize the consumption in chip area by improving the error performance by detection and correction. Generally, it is difficult to implement the VLSI based decoding of Geometric LDPC codes because of high complexity and large memory requirements. Methods/Statistical Analysis: In this proposed design architecture we have considered the Soft-Bit Flipping (SBF) algorithm employed here utilizes reliability estimation to improve error performance and it has advantages of Bit Flipping (BF) algorithms. Findings: This proposed design architecture is compared for different technologies using Leonardo spectrum software in Mentor Graphics Tools. We can also obtain the area and delay reports using this tool and optimization of the design is being proposed. Application/Improvement: In future works, this algorithm can be improved with still more security level by having a trade off between performance and data transmission. It can also enhanced by implementing it in real time applications for data decoding and correction, for smaller size datum.

Bayesian Estimation and Inference Using Stochastic Electronics.

In this paper, we present the implementation of two types of Bayesian inference problems to demonstrate the potential of building probabilistic algorithms in hardware using single set of building blocks with the ability to perform these computations in real time. The first implementation, referred to as the BEAST (Bayesian Estimation and Stochastic Tracker), demonstrates a simple problem where an observer uses an underlying Hidden Markov Model (HMM) to track a target in one dimension. In this implementation, sensors make noisy observations of the target position at discrete time steps. The tracker learns the transition model for target movement, and the observation model for the noisy sensors, and uses these to estimate the target position by solving the Bayesian recursive equation online. We show the tracking performance of the system and demonstrate how it can learn the observation model, the transition model, and the external distractor (noise) probability interfering with the observations. In the second implementation, referred to as the Bayesian INference in DAG (BIND), we show how inference can be performed in a Directed Acyclic Graph (DAG) using stochastic circuits. We show how these building blocks can be easily implemented using simple digital logic gates. An advantage of the stochastic electronic implementation is that it is robust to certain types of noise, which may become an issue in integrated circuit (IC) technology with feature sizes in the order of tens of nanometers due to their low noise margin, the effect of high-energy cosmic rays and the low supply voltage. In our framework, the flipping of random individual bits would not affect the system performance because information is encoded in a bit stream.

Dynamic Weighted Bit-Flipping Decoding Algorithms for LDPC Codes

Bit-flipping (BF) decoding of low-density parity-check codes is of low complexity but gives inferior performance in general. To improve performance and provide new BF decoder options for complexity-performance tradeoffs, we propose new designs for the flipping function (FF), the flipped bit selection (FBS) rule and the checksum weight updating schedule. The new FF adjusts the checksum weights in every iteration while our FBS rules take more information into account. These two modifications represent efforts to track more closely the evolutions of both check and variable nodes' reliabilities. Two selective update schedules are proposed to offer more performance and complexity tradeoffs. The combinations of the new FBS rule and known FFs result in new BF decoders with improved performance and a modest complexity increase. On the other hand, combining the new FF and FBS rule gives a new decoder with performance comparable to that of the normalized min-sum algorithm while if we use a much simpler FBS rule instead, the decoder suffers little performance loss with reduced complexity. We also present a simple decision-theoretical argument to justify the new checksum weight formula and a time-expanded factor graph model to explain the proposed selective weight-updating schedules.

A Dominating Error Region Strategy for Improving the Bit-Flipping LDPC Decoder of SSDs

This brief presents a dominating error region strategy (DERS) that improves the bit-flipping (BF) low-density parity-check decoder for solid-state drives. With the help of the DERS, the state-of-the-art BF decoding algorithms achieve better error correction performance while taking less iterations. Specifically, the DERS provides solutions for restricting the occurrences of an even number of flipped bits and bit-error propagations, both of which are intrinsic problems to current BF decoding algorithms. The DERS can be implemented with a simple circuitry and serve as a fine-tuning technique for the decoding reliability–performance tradeoff. In this brief, the DERS is evaluated with numerical analysis and computer simulations.

Multi-Threshold Bit Flipping Algorithm for Decoding Structured LDPC Codes

A novel bit-flipping (BF) decoding algorithm is proposed for structured low-density parity-check (LDPC) codes. The proposed BF algorithm which is called multi-threshold bit-flipping (MTBF) algorithm, flips multiple bits by using multiple thresholds at each iteration. It only requires some real operations before iterations and requires only logical operations during the iterations. The MTBF algorithm has lower complexity than the weighted bit-flipping algorithm and its modifications. Simulations show that the proposed algorithm has fast convergence speed and good performance.