Abstract
Area efficient and high speed forward error correcting codes decoder are the demand of many high speed next generation communication standards. This paper explores a low complexity decoding algorithm of low density parity check codes, called the min-sum iterative construction a posteriori probability (MS-IC-APP), for this purpose. We performed the error performance analysis of MS-IC-APP for a (648,1296) regular QC-LDPC code and proposed an area and throughput optimized hardware implementation of MS-IC-APP. We proposed to use the layered scheduling of MS-IC-APP and performed other optimizations at architecture level to reduce the area and to increase the throughput of the decoder. Synthesis results show 6.95 times less area and 4 times high throughput as compared to the standard min-sum decoder. The area and throughput are also comparable to the improved variants of hard-decision bit-flipping (BF) decoders, whereas, the simulation results show a coding gain of 2.5 over the best implementation of BF decoder in terms of error performance.
Highlights
Low density parity check (LDPC) codes [1,2] are used in many communication systems [3] and are of particular interest in data storage systems [4] due to their excellent error correction capability
We proposed an area-efficient and high throughput hardware implementation of the MS-Iterative Construction of A Posteriori Probability (IC-APP) algorithm
We used the lay-ered scheduling of the MS-IC-APP in order to eliminate the CTV message memory and performed some other optimizations in the hardware in order to optimize the area-efficiency of the decoder
Summary
Low density parity check (LDPC) codes [1,2] are used in many communication systems [3] and are of particular interest in data storage systems [4] due to their excellent error correction capability. These fully parallel and ultra high throughput decoders are implemented at the expense of large area Another class of decoding algorithms called the hard-decision algorithms result in very low complexity decoders but at the cost of reduced error correction performance. We. An area efficient and high throughput implementation of layered MS-IC-APP LDPC decoder analyzed the performance of MS-IC-APP for a regular quasi-cyclic (QC) LDPC code and compared the performance with MS algorithm and the improved variants of the hard-decision BF algorithms. Simulation and implementation results show better error correction performance of the layered MS-IC-APP algorithm, especially, at low frame error rate and comparable hardware complexity as compared to the hard-decision BF algorithms.
Sign-in/Register to view highlights & summary 
Published Version (
Free)
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call