Binary Signed-digit Research Articles

Improving Architectures of Binary Signed-Digit CORDIC With Generic/Specific Initial Angles

Coordinate rotation digital computer (CORDIC) is widely used in digital signal processing (DSP) to calculate functions. One of the elegant ways to accelerate CORDIC is employment of the redundant binary signed-digit (BSD) number systems, so-called BSD-CORDIC. This paper aims to achieve efficient BSD-CORDIC structures for generic/specific initial angles. First, three generic BSD-CORDIC algorithms are optimized by exploiting a suitable data gating technique as well as appropriate BSD encodings. The synthesis results demonstrate that for generic CORDIC, the proposed BSD-CORDIC schemes enhance the existing ones in terms of speed, power consumption, and area overhead. Second, the look-ahead BSD-CORDIC is proposed as a special case of BSD-CORDIC with specific initial angles. We also show that for the applications like fast Fourier transform (FFT), where the initial angles are known in advance, the proposed look-ahead BSD-CORDIC with the posibit-negabit encoding, as our best presenting structure, noticeably improves speed, power consumption, and area overhead.

Novel Binary Signed-Digit Addition Algorithm for FPGA Implementation

Signed-digit (SD) number representation systems have been studied for high-speed arithmetic. One important property of the SD number system is the possibility of performing addition without long carry chain. However, many numbers of logic elements are required when the number representation system and such an adder are realized on a logic circuit. In this study, we propose a new adder on the binary SD number system. The proposed adder uses more circuit area than the conventional SD adders when those adders are realized on ASIC. However, the proposed adder uses 20% less number of logic elements than the conventional SD adder when those adders are realized on a field-programmable gate array (FPGA) which is made up of 4-input 1-output LUT such as Intel Cyclone IV FPGA.

Area–Time–Power Efficient FFT Architectures Based on Binary-Signed-Digit CORDIC

Fast Fourier transform (FFT) is a significant technique in the digital signal processing (DSP). The intrinsic weak point of the primary designs of FFT was the use of multipliers. CORDIC is the most prevalent method to replace the multipliers of FFTs. In order to enhance the speed of CORDIC, redundant binary signed-digit (BSD) encodings can be utilized, so-called BSD-CORDIC. The main goal of this paper is to improve the efficiency of BSD-CORDIC-based FFT. The redundant improved composed (RIC) CORDIC is proposed as a novel BSD-CORDIC. The main idea behind the RIC CORDIC lies in prior determination of the required iterations in such a way that the maximum number of iterations is reduced, which results in speedup and decrease in hardware resources. Also, some of the iterations still can be skipped, which leads to further reduction in the power consumption. The synthesis results demonstrate that the FFT based on the RIC BSD-CORDIC enhances speed, power consumption, and area overhead.

EFFICIENT FLOATING POINT FAST FOURIER TRANSFORM BUTTERFLY ARCHITECTURE USING BINARY SIGNED DIGIT MULTIPLIER AND ADDERS

Fast Fourier transform (FFT) is one of the most important tools in digital signal processing as well as communication system because transforming time domain to S-plane is very convenient using FFT. As FFT uses various techniques to convert a signal from time domain to S-domain and inverse, out of which butterfly technique is the one on which paper is focused on. Butterfly technique uses additions and multiplications of operands to get the required output. Floating point (FP) is used as operands due to their flexibility. As the computations involving FP has less speed, we have used binary signed digit (BSD). BSD will take the less time for addition and subtraction. Three bit BSD adder and FP adder together will make a fused dot product add (FDPA) unit. In FDPA, unit addition and subtraction will be one group and multiplication will be one group and then their respective results will be fused. Modified booth encoding and decoding algorithm are used here to make the complex multiplication with ease.

Floating-Point Butterfly Architecture Based on Binary Signed-Digit Representation

Fast Fourier transform (FFT) coprocessor, having a significant impact on the performance of communication systems, has been a hot topic of research for many years. The FFT function consists of consecutive multiply add operations over complex numbers, dubbed as butterfly units. Applying floating-point (FP) arithmetic to FFT architectures, specifically butterfly units, has become more popular recently. It offloads compute-intensive tasks from general-purpose processors by dismissing FP concerns (e.g., scaling and overflow/underflow). However, the major downside of FP butterfly is its slowness in comparison with its fixed-point counterpart. This reveals the incentive to develop a high-speed FP butterfly architecture to mitigate FP slowness. This brief proposes a fast FP butterfly unit using a devised FP fused-dot-product-add (FDPA) unit, to compute AB ± CD ± E, based on binary-signed-digit (BSD) representation. The FP three-operand BSD adder and the FP BSD constant multiplier are the constituents of the proposed FDPA unit. A carry-limited BSD adder is proposed and used in the three-operand adder and the parallel BSD multiplier so as to improve the speed of the FDPA unit. Moreover, modified Booth encoding is used to accelerate the BSD multiplier. The synthesis results show that the proposed FP butterfly architecture is much faster than previous counterparts but at the cost of more area.

Comments on &quotArea Time Efficient Sign Detection Technique for Binary Signed-Digit Number System&quot proposed by Srikanthan, Lam and Suman

It is shown that the sign detection technique for binary signeddigit number system reported by Srikanthan, Lam and Suman [1] cannot work correctly. The root cause of the problem is detected and some modifications are proposed. The proposed modifications are found to be significant. General Terms Unconventional Number Systems, Algorithm, VLSI

Fast calculation of number of binary signed digit representations of an integer

Binary Signed Digit(BSD) representation of an integer is widely used in computer arithmetic,cryptography and digital signal processing.An integer of length n bits can have several BSD representations.In this paper,the authors studied the properties of the number of BSD representation of an integer,and presented two improved non-recursion algorithms.They can rapidly calculate the exact number of BSD representations of an integer of a certain length,and the storage requirements get reduced.

Efficient realisation of arithmetic algorithms with weighted collection of posibits and negabits

Most common uses of negatively weighted bits (negabits), normally assuming arithmetic value 21(0) for logical 1(0) state, are as the most significant bit of 2's-complement numbers and negative component in binary signed-digit (BSD) representation. More recently, weighted bit-set (WBS) encoding of generalised digit sets and practice of inverted encoding of negabits (IEN) have allowed for easy handling of any equally weighted mix of negabits and ordinary bits (posibits) via standard arithmetic cells (e.g., half/full adders, compressors, and counters), which are highly optimised for a host of simple and composite figures of merit involving delay, power, and area, and are continually improving due to their wide applicability. In this paper, we aim to promote WBS and IEN as new design concepts for designers of computer arithmetic circuits. We provide a few relevant examples from previously designed logical circuits and redesigns of established circuits such as 2's-complement multipliers and modified booth recoders. Furthermore, we present a modulo-(2 n + 1) multiplier, where partial products are represented in WBS with IEN. We show that by using standard reduction cells, partial products can be reduced to two. The result is then converted, in constant time, to BSD representation and, via simple addition, to final sum.

Differential Power Analysis on Countermeasures Using Binary Signed Digit Representations

Side channel attacks are a very serious menace to embedded devices with cryptographic applications. To counteract such attacks many randomization techniques have been proposed. One efficient technique in elliptic curve cryptosystems randomizes addition chains with binary signed digit (BSD) representations of the secret key. However, when such countermeasures have been used alone, most of them have been broken by various simple power analysis attacks. In this paper, we consider combinations which can enhance the security of countermeasures using BSD representations by adding additional countermeasures. First, we propose several ways the improved countermeasures based on BSD representations can be attacked. In an actual statistical power analysis attack, the number of samples plays an important role. Therefore, we estimate the number of samples needed in the proposed attack.

On binary signed digit representations of integers

Applications of signed digit representations of an integer include computer arithmetic, cryptography, and digital signal processing. An integer of length n bits can have several binary signed digit (BSD) representations and their number depends on its value and varies with its length. In this paper, we present an algorithm that calculates the exact number of BSDR of an integer of a certain length. We formulate the integer that has the maximum number of BSDR among all integers of the same length. We also present an algorithm to generate a random BSD representation for an integer starting from the most significant end and its modified version which generates all possible BSDR. We show how the number of BSD representations of k increases as we prepend 0s to its binary representation.

Enhanced Exhaustive Search Attack on Randomized BSD Type Countermeasure

We propose a new analysis technique against a class of countermeasure using randomized binary signed digit (BSD) representations. We also introduce some invariant properties between BSD representations. The proposed analysis technique can directly recover the secret key from power measurements without information for algorithm because of the invariant properties of BSD representation. Thus the proposed attack is applicable to all countermeasures using BSD representations. Finally, we give the simulation results against some countermeasures using BSD representation such as Ha-Moon method, Ebeid-Hasan method, and the method of Agagliate et al. The results show that the proposed attack is practical analysis method.

Leading guard digits in finite precision redundant representations

Redundant number representations are generally used to allow constant time additions, based on the fact that only bounded carry-ripples take place. But, carries may ripple out into positions which may not be needed to represent the final value of the result and, thus, a certain amount of leading guard digits are needed to correctly determine the result. Also, when cancellation during subtractions occurs, there may be nonzero digits in positions not needed to represent the result of the calculation. It is shown here that, for normal redundant digit sets with radix greater than two, a single guard digit is sufficient to determine the value of such an arbitrary length prefix of leading nonzero digits. This is also the case for the unsigned carry-save representation, whereas two guard digits are sufficient, and may be necessary, for additions in the binary signed-digit and 2's complement carry-save representations. Thus, only the guard digits need to be retained during sequences of additions and subtractions. At suitable points, the guard digits may then be converted into a single digit, representing the complete prefix.

Algorithm of asynchronous binary signed-digit recoding on fast multiexponentiation

Multiexponentiation, for the 2-dimension one especially, is a very important but time-consuming operation in many ElGamal-like public key cryptosystems. An efficient multiexponentiation method is firstly proposed by Shamir in ElGamal’s paper. Shamir’s method requires 1.75 n modular multiplications in average, where n is the bit-length of the exponents. Using minimal weight binary signed-digit (BSD) representations in Shamir’s method can reduce the number of multiplications to 1.556 n. Due to there are many minimal weight BSD representations for an integer, Dimitrov et al. proposed a new 2-dimension multiexponentiation algorithm to recode the canonical binary signed-digit representations. The average number of the number 1.556 n is reduced to 1.534 n. After the publish of the Dimitrov–Jullien–Miller algorithm, there are many research on receding BSD representation of a pair of integers. The most interesting one is the joint sparse form. The number of multiplication can be reduced to 1.500 n in joint sparse form when the exponent length is near infinite. In this paper, we propose a new asynchronous recoding algorithm to reduce the factor to 1.509n. For comparison to all the previous algorithm, the property of asynchronous receding is especially suitable for multi-dimension multiexponentiation.

Area-time efficient sign detection technique for binary signed-digit number system

Computer arithmetic operations based on the BSD (binary signed-digit) number representation system lend themselves well to high-speed computations due to the facilitation of limited carry addition/subtraction. We propose an area-time efficient method for sign detection in a BSD number system based on optimized reverse tree structure. When compared to other popular approaches, such as the most significant carry detection-based CLA (carry look-ahead) and MRC (multilevel reverse carry) implementations, the proposed method is superior to both area and time costs in VLSI. Synthesis results for different word lengths show that the proposed approach to sign detection in the BSD number system continues to maintain its advantage over area and time measures.

RADIX MODULAR MULTIPLICATION ALGORITHM

In this paper, the concept of a new Radix Modular Multiplication Algorithm (MMA) is proposed. The novelty of the new Radix-2n MMA is that the intermediate partial sums (IPSs) are not restricted to be less than the modulus M, but only to be represented by N bits, where N is the number of bits needed to represent the modulus M. Hence, the IPSs become redundant to the modulus M. Two new Radix-2n MMAs (for n=2 and 4) based on the proposed concept are considered in detail as well. It is shown that a parallel multiplier based on the new Radix-4 MMA achieves twice the speed of a parallel multiplier based on a recent Radix-2 MMA. This result becomes more significant when it is noted that doubling the speed was achieved without any increase in the hardware requirement. In addition, it is shown that the parallel multiplier based on the new Radix-16 MMA achieves four times the speed of that of the Radix-2 MMA with the same hardware requirement. When compared to the existing Radix-4 MMAs that are based on Carry Save format and Binary Signed Digit (BSD) representation, it is shown that the delay per step of the proposed Radix-4 multiplier is decreased by more than 40% when the intermediate steps are implemented using Carry Save Adders (CSAs).

Fast multiplier design using redundant signed-digit numbers

A high speed multiplier design is presented using redundant binary signed-digit number representation internally while the input operands and the output product are in two's complement form. The design of a carry free redundant binary signed-digit (RBSD) adder cell is presented. The multiplication algorithm uses bit-pair recording to generate the partial products. The partial products are added in the form of a binary tree using carry free RBSD adder cells. The regular structure of these adder cells results in a multiplier design that is suitable for VLSI implementation. The increased speed is achieved through the carry free addition of partial products using redundant signed-digit numbers. The use of a recoding scheme will reduce the number of rows of partial products by a factor of two. The proposed multiplier design has a multiplication time of order O(log2 n) and area-time complexity of order O(n2 log2 n) for a word length of n.