Abstract
In this paper, the concept of a new Radix Modular Multiplication Algorithm (MMA) is proposed. The novelty of the new Radix-2n MMA is that the intermediate partial sums (IPSs) are not restricted to be less than the modulus M, but only to be represented by N bits, where N is the number of bits needed to represent the modulus M. Hence, the IPSs become redundant to the modulus M. Two new Radix-2n MMAs (for n=2 and 4) based on the proposed concept are considered in detail as well. It is shown that a parallel multiplier based on the new Radix-4 MMA achieves twice the speed of a parallel multiplier based on a recent Radix-2 MMA. This result becomes more significant when it is noted that doubling the speed was achieved without any increase in the hardware requirement. In addition, it is shown that the parallel multiplier based on the new Radix-16 MMA achieves four times the speed of that of the Radix-2 MMA with the same hardware requirement. When compared to the existing Radix-4 MMAs that are based on Carry Save format and Binary Signed Digit (BSD) representation, it is shown that the delay per step of the proposed Radix-4 multiplier is decreased by more than 40% when the intermediate steps are implemented using Carry Save Adders (CSAs).
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