Abstract
In this paper the Efficient Montgomery Modular Multiplication (MMM) algorithms has projected and its implementation in hardware accessible using the Carry Save Adder (CSA) architecture algorithms for Multi-Core system. The proposed designing Montgomery Modular Multiplication algorithm based on the Multi-Core Iteration Array Level and pipeline process to increase its Performance. We show that the architecture has greater performance in AMD Gizmo Processor architectures, Here comparison is done between the developed Montgomery Modular Multiplication and Modular excluded with CSA multiplier. Two parameters like Speed and Power consumption analysed by implemented Multi-Core Gizmo Processor Board with Dual Kernel and Xilinx VHDL As a result, the performance can be improved by 34% with 516-bit and 1024-bit, 2048-bit Montgomery modular multiplication being performed clock cycles respectively.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
