Binary Signed Digit Number Research Articles

QCA-Based Adder for Redundant Binary Signed Digit Numbers

QCA-Based Adder for Redundant Binary Signed Digit Numbers

Design and Implementation of Fast Booth-2 Multiplier on Artix FPGA

Abstract Now a day’s speed is very important to meet the requirement of user in today’s chips. We want faster smart phones, laptops and other gadgets that can work at a speed even beyond our imagination. In this paper we have designed a fast multiplier which can provide better results. RBSD stands for Redundant Binary Signed Digit number system which enables fast computing by reducing carry propagation time as carry is not propagated to later stages. This number system is signed digit number representation. This RBSD multiplier is implemented using VIVADO 2019.2 version. The multiplier is implemented in VHDL language. Although there is a slight increase in the delay using VIVADO Multiplier, there is a significant decrease in the number of LUT used. We have used artix FPGA[4] with part number xc7a200tisbv484.

Notes on &quotA Novel Conversion Scheme from a Redundant Binary Number to Two's Complement Binary Number for Parallel Architectures&quot proposed by Choo et. al.

In this article, it is shown that although the reverse conversion scheme for binary signed-digit number system proposed by Choo et. al. can not support full parallelism; the rules on which it is based are correct. In this connection, a mathematical induction technique is used to validate the decomposition rules. Accordingly, it can be inferred that the reverse conversion scheme for binary signed-digit number system proposed by Veeramachaneni et. al. works correctly and performs reverse conversion in Ω (log n) time, where, n is the input size. As a consequence, the scheme by Veeramachaneni et. al. need to be considered as a potential contender of the more recent schemes for the same. General Terms Unconventional Number System, Computer Arithmetic Algorithm.

Comments on &quotArea Time Efficient Sign Detection Technique for Binary Signed-Digit Number System&quot proposed by Srikanthan, Lam and Suman

It is shown that the sign detection technique for binary signeddigit number system reported by Srikanthan, Lam and Suman [1] cannot work correctly. The root cause of the problem is detected and some modifications are proposed. The proposed modifications are found to be significant. General Terms Unconventional Number Systems, Algorithm, VLSI

A Common Subexpression Elimination Tree Algorithm

A common subexpression elimination algorithm is proposed to minimize the complexity of the multiple constant multiplication operation. The coefficients (constants) of the multiple constant multiplication are represented using the binary signed digit number system. The binary signed digit representations of each coefficient are enumerated using the representation tree. The algorithm traverses the tree to calculate the possible subexpressions at each node. Each subexpression is used to find a possible decomposition for the coefficient to be encoded. A complexity formula is proposed to compare the decompositions. The algorithm is designed to prune the tree when it finds a decomposition with minimum complexity. This reduces the search space while minimizing the hardware complexity. Results show that the algorithm has better performance than other published algorithms including linear programming optimization methods. The algorithm outperforms the subexpression sharing method in that uses only the canonical signed-digit representations.

Area-time efficient sign detection technique for binary signed-digit number system

Computer arithmetic operations based on the BSD (binary signed-digit) number representation system lend themselves well to high-speed computations due to the facilitation of limited carry addition/subtraction. We propose an area-time efficient method for sign detection in a BSD number system based on optimized reverse tree structure. When compared to other popular approaches, such as the most significant carry detection-based CLA (carry look-ahead) and MRC (multilevel reverse carry) implementations, the proposed method is superior to both area and time costs in VLSI. Synthesis results for different word lengths show that the proposed approach to sign detection in the BSD number system continues to maintain its advantage over area and time measures.

Efficient implementation of regular parallel adders for binary signed digit number representations

Signed digit number representations diminish the latency of addition at moderate hardware cost and thus can play an important role in processor design, especially for processor architectures like superscalar, superpipelining, and VLIW. Moreover, they are very useful for the construction of on-line arithmetic systems that operate in most significant digit first style. Due to inadequate formal models, implementations of adders for signed digit number representations have been somewhat clumsy in the past. Usually it had been overlooked that the choice of a good representation for the digits is of crucial importance to an efficient implementation. In this paper we propose a formal model for addition on binary signed digit number representations that comprises all aspects of representing the digits by bits. We characterize all feasible adder functions, derive lower bounds on the fan-in of time-optimal adder cells for the various representations, and show thereby that there are ‘good’ and ‘bad’ representations.

Very-high-speed VLSI 2s-complement multiplier using signed binary digits

A high-speed 8*8-bit multiplier design for 2s-complement binary numbers is presented. The multiplier uses the binary signed-digit number system to achieve both high speed and layout simplicity, and is implemented in double layer metal 2 mu m CMOS technology. The multiplication time for the array was found by simulation to be 18 ns at 25 degrees C and its size was measured as 1.7 mm*2.3 mm (excluding pads). Power dissipation was calculated as just less than 40 mW at 55 MHz, and the transistor count is 3754 transistors.

Fast multiplier design using redundant signed-digit numbers

A high speed multiplier design is presented using redundant binary signed-digit number representation internally while the input operands and the output product are in two's complement form. The design of a carry free redundant binary signed-digit (RBSD) adder cell is presented. The multiplication algorithm uses bit-pair recording to generate the partial products. The partial products are added in the form of a binary tree using carry free RBSD adder cells. The regular structure of these adder cells results in a multiplier design that is suitable for VLSI implementation. The increased speed is achieved through the carry free addition of partial products using redundant signed-digit numbers. The use of a recoding scheme will reduce the number of rows of partial products by a factor of two. The proposed multiplier design has a multiplication time of order O(log2 n) and area-time complexity of order O(n2 log2 n) for a word length of n.

Carry-free addition of recoded binary signed-digit numbers

Signed-digital number representation systems have been defined for any radix r>or=3 with digit values ranging over the set (- alpha ,...,-1,0,1,..., alpha ), where alpha is an arbitrary integer in the range r/2 >