Binary Logic Operations Research Articles

High energy efficient and configurable CIM macro for image processing

Traditional von Neumann architecture, characterized by separate memory and processing units connected by a limited-capacity memory bus, faces challenges in handling tasks with high energy efficiency requirements. In contrast, the compute-in-memory (CIM) architecture offers a promising alternative, facilitating high parallelism in data processing while integrating storage functions, thereby significantly reducing memory access frequency and power consumption. This study presents a fully digital CIM macro featuring a novel self-write-back 12T cell. This bitcell is capable of performing Boolean logic operations and autonomously writing back results into the in-situ cell, thereby significantly improving energy efficiency.This can be used for binary logical operations between each pixel of two images without requiring additional storage area. A bidirectional read/write architectural design enables matrix transposition. This can achieve image rotation.Additionally, this novel 12T cell also offers the option to choose not to write back the results of logical operations, thereby providing the flexibility and configurability for image processing. Combined with an adder tree, it enables multiply-and-accumulate (MAC) operation for convolutional neural networks(CNNs). This can be used for feature extraction. We propose an 18T full adder structure with lower power-delay product than current state-of-the-art full adders, which is advantageous for improving the synthesis performance of the adder tree.The CIM macro supports a 4-bit × 4-bit MAC operation. The proposed CIM macro, designed and simulated using a 28 nm CMOS process with a 16 Kb static random access memory (SRAM), demonstrates promising results. At VDD = 0.9 V, the logic operation energy consumption is 1.35 fJ/bit with an energy efficiency of 740TOPS/W, and MAC operation energy consumption is 15.91 fJ/bit with an energy efficiency of 62.85 TOPS/W.

Binary and ternary logic-in-memory using nanosheet feedback field-effect transistors with triple-gated structure

In this study, we demonstrate binary and ternary logic-in-memory (LIM) operations of inverters and NAND and NOR gates comprising nanosheet (NS) feedback field-effect transistors (FBFETs) with a triple-gated structure. The NS FBFETs are reconfigured in p- or n-channel modes depending on the polarity of the gate bias voltage and exhibit steep switching characteristics with an extremely low subthreshold swing of 1.08 mV dec–1 and a high ON/OFF current ratio of approximately 107. Logic circuits consisting of NS FBFETs perform binary and ternary logic operations of the inverters and NAND and NOR gates in each circuit and store their outputs under zero-bias conditions. Therefore, NS FBFETs are promising components for next-generation LIM.

A reconfigurable binary/ternary logic conversion-in-memory based on drain-aligned floating-gate heterojunction transistors

A new type of heterojunction non-volatile memory transistor (H-MTR) has been developed, in which the negative transconductance (NTC) characteristics can be controlled systematically by a drain-aligned floating gate. In the H-MTR, a reliable transition between N-shaped transfer curves with distinct NTC and monolithically current-increasing transfer curves without apparent NTC can be accomplished through programming operation. Based on the H-MTR, a binary/ternary reconfigurable logic inverter (R-inverter) has been successfully implemented, which showed an unprecedentedly high static noise margin of 85% for binary logic operation and 59% for ternary logic operation, as well as long-term stability and outstanding cycle endurance. Furthermore, a ternary/binary dynamic logic conversion-in-memory has been demonstrated using a serially-connected R-inverter chain. The ternary/binary dynamic logic conversion-in-memory could generate three different output logic sequences for the same input signal in three logic levels, which is a new logic computing method that has never been presented before.

BC-MVLiM: A Binary-Compatible Multi-Valued Logic-in-Memory Based on Memristive Crossbars

Logic-in-memory with memristive crossbars is an attractive approach for realizing beyond von Neumann architectures. Multi-valued logic (MVL) containing more than two logic levels can enhance the computing speed with reduced number of logic operations. In this paper, a binary-compatible multi-valued logic-in-memory (BC-MVLiM) scheme is proposed with memristive dual-crossbars where both inputs and outputs are represented by the multi-level cells of memristors. Both of the binary and multiple-valued logic operations can be implemented in the proposed BC-MVLiM scheme depending on the radix of inputs. The proposed BC-MVLiM circuitry supports multiple row-wise and column-wise logic gates with multiple fan-ins and fan-outs for binary and ternary systems by leveraging both inter-and intra-crossbar operations. Experimental results show that the proposed BC-MVLiM-based multi-digit adder enhances the computation speed by up to 76.10% and 83.82%, for binary and ternary systems, respectively, as compared with the previously published memristive logic designs. By preventing the errors from propagating across multiple stages, the error rate of proposed BC-MVLiM is also reduced by up to 98.20% compared to the previous memristive logic designs in the presence of device variations.

Actively switchable terahertz Spiral-Shaped metamaterial with programmable performance

Two designs of actively switchable terahertz (THz) spiral-shaped metamaterial (SSM) are presented in this study. They are composed of four spiral meta-atoms with different orientations. The electromagnetic responses of SSM devices show the fifth-resonance to provide five switching windows for binary encoding due to their transmission intensities with polarization-dependent characteristic. In addition, by actively changing the configuration of elevated spiral meta-atoms, a dual-resonance switching function can be realized. It proves the binary encoding and logic operation such as NAND and OR gates. These characteristics indicate that the proposed SSM designs can be promising optoelectronic switching and multi-bit programmable devices in the THz spectrum.

Memristive FHN spiking neuron model and brain-inspired threshold logic computing

The FitzHugh-Nagumo (FHN) spiking model has rich dynamics behaviors and can imitate the firing process of a neuron. The memristor is a nonvolatile and resistance tunable device, which gradually becomes a potential candidate for performing dynamic behaviors and implementing neuromorphic computation in the nervous system. In this paper, the memristive FitzHugh-Nagumo (MFHN) spiking model is presented. Firstly, we introduce a memristor to the FHN spiking model to build the MFHN spiking model and analyze the phase plane trajectory of the MFHN model. Secondly, we couple two MFHN models with a memristor and experimentally simulate the dynamic behaviors of two coupled neurons. The synchronous and asynchronous phenomena of two coupled neurons are discussed. Thirdly, the feasibility of the MFHN spiking model is demonstrated by the realization of binary logical operations and the implementation of binary adders. The comparison between the MFHN binary adder and the FHN binary adder is conducted. The simulation results illustrate that the proposed model efficiently performs rich, dynamic behaviors and higher firing frequency. The coupled MFHN models show the effectiveness of a memristor acting as an electric coupling synapse. The threshold logic computation can be completed efficiently by the MFHN spiking model. The MFHN binary adders reproduce the computing functions and behaviors of the biological neuron.

CryoCiM: Cryogenic compute-in-memory based on the quantum anomalous Hall effect

The scaling of the already matured complementary metal-oxide-semiconductor technology is steadily approaching its physical limit, motivating the quest for a suitable alternative. Cryogenic operation offers a promising pathway toward continued improvement in computing speed and energy efficiency without aggressive scaling. However, the memory wall bottleneck of the traditional von-Neumann architecture persists even at cryogenic temperature. That is where a compute-in-memory (CiM) architecture, which embeds computing within the memory unit, comes into play. Computations within the memory unit help to reduce the expensive data transfer between the memory and the computing units. Therefore, CiM provides extreme energy efficiency that can enable lower cooling cost at cryogenic temperature. In this work, we demonstrate CryoCiM, a cryogenic compute-in-memory framework utilizing a nonvolatile memory system based on the quantum anomalous Hall effect (QAHE). Our design can perform memory read/write and universal binary logic operations (NAND, NOR, and XOR). We custom design a peripheral circuit assembly that can perform the read/write and single-cycle in-memory logic operations. The utilization of a QAHE-based memory system promises robustness against process variations, through the usage of topologically protected resistive states for data storage. CryoCiM is a major step toward utilizing exclusively cryogenic phenomena to serve the dual purpose of storage and computation with ultra-low power (∼nano-watts) operations.

Word-based encryption algorithm using dictionary indexing with variable encryption key length

<p>This paper proposes a new algorithm for text encryption utilizing English words as a unit of encoding. The algorithm vanishes any feature that could be used to reveal the encrypted text through adopting variable code lengths for the English words, utilizing a variable-length encryption key, applying two-dimensional binary shuffling techniques at the bit level, and utilizing four binary logical operations with randomized shuffling inputs. English words that alphabetically sorted are divided into four lookup tables where each word has assigned an index. The strength of the proposed algorithm concluded from having two major components. Firstly, each lookup table utilizes different index sizes, and all index sizes are not multiples of bytes. Secondly, the shuffling operations are conducted on a two-dimensional binary matrix with variable length. Lastly, the parameters of the shuffling operation are randomized based on a randomly selected encryption key with varying size. Thus, the shuffling operations move adjacent bits away in a randomized fashion. Definitively, the proposed algorithm vanishes any signature or any statistical features of the original message. Moreover, the proposed algorithm reduces the size of the encrypted message as an additive advantage which is achieved through utilizing the smallest possible index size for each lookup table.</p>

Features of a Multivalued Generalization of Binary Logic Operations in Linear Algebra for Problems of Digital Processing of Current-Output Sensor Signals

Features of a Multivalued Generalization of Binary Logic Operations in Linear Algebra for Problems of Digital Processing of Current-Output Sensor Signals

Fault section diagnosis of power systems with logical operation binary gaining‐sharing knowledge‐based algorithm

Fault section diagnosis (FSD) is a critical part of the power system dispatching and control. To diagnose the faulty section(s) correctly, an improved binary variant of gaining-sharing knowledge-based algorithm (GSK) named LOBGSK is presented in this paper. It stretches the original GSK over binary search space so as to solve the 0-1 integer programming FSD problem. In LOBGSK, individuals are encoded by binary numbers and logical operations instead of real arithmetic operations are designed to update the individuals. By this, LOBGSK can avoid transcoding in solving the FSD problem. To validate the effectiveness of LOBGSK, it is first applied to a 4-substation test system considering various fault scenarios. Then it is further implemented to the IEEE 118-bus system and an actual fault event occurred in a practical power grid in Jilin province of China. In addition, the influence of three key parameters of LOBGSK is also investigated. Simulation results show that LOBGSK is robust against its key parameters and can offer a 100% successful rate to diagnose different faults quickly, which is demonstrated by the reported results of some published FSD methods. Furthermore, it outperforms seven state-of-the-art metaheuristic algorithms and the original GSK in solving the FSD problem of power systems.

On the Logical Computational Complexity Analysis of Turbo Decoding Algorithms for the LTE Standards

Evaluating the computational complexity of decoders is a very important aspect in the area of Error Control Coding. However, most evaluations have been performed based on hardware implementations. In this paper, different decoding algorithms for binary Turbo codes which are used in LTE standards are investigated. Based on the different mathematical operations in the diverse equations, the computational complexity is derived in terms of the number of binary logical operations. This work is important since it demonstrates the computational complexity breakdown at the binary logic level as it is not always evident to have access to hardware implementations for research purposes. Also, in contrast to comparing different Mathematical operations, comparing binary logic operations provides a standard pedestal in view to achieve a fair comparative analysis for computational complexity. The usage of the decoding method with fewer number of binary logical operations significantly reduces the computational complexity which in turn leads to a more energy efficient/power saving implementation. Results demonstrate the variation in computational complexities when using different algorithms for Turbo decoding as well as with the incorporation of Sign Difference Ratio (SDR) and Regression-based extrinsic information scaling and stopping mechanisms. When considering the conventional decoding mechanisms and streams of 16 bits in length, Method 3 uses 0.0065% more operations in total as compared to Method 1. Furthermore, Method 2 uses only 0.0035% of the total logical complexity required with Method 1. These computational complexity analysis at the binary logical level can be further used with other error correcting codes adopted in different communication standards.

Computer-aided mobility analysis of parallel mechanisms

To determine mobility properties is one of the most challenging issue in the analysis and synthesis of parallel manipulators (PMs). However, currently, the most used methods mainly rely on experiences and manual analysis, which led to inefficient implementation. The motivation of this paper is to present an automatic mobility analysis algorithm and software package for the researchers and designers with an effective and practical means. According to the topological design theory of PMs based on position and orientation characteristic (POC) equations, this paper proposes a set of computer algorithmic rules and procedures for automated mobility analysis of PMs in the most user-friendly and efficient way. Firstly, a complete digital information model for topological structures which has a mapping relationship with the POC of a PM is proposed. This model not only describes the dimension of the motion outputs, but also includes the mapping relationship between the output orientation and the axes of the kinematic joints. Secondly, algorithmic rules are established that convert the union and intersection operations of POC into binary logical operations and then the detailed algorithmic procedures for an automatic mobility analysis are presented. In what follows, a corresponding software for automatic mobility analysis is described. The software package is equipped with a GUI that facilitates the input and allows the visualization of the results. Finally, four typical examples are provided to show the effectiveness of the software package for most of parallel mechanisms (not including some paradoxical mechanisms).

Design and Performance Investigations with Ultra High Speed Optical ALU

Abstract All-optical arithmetic and logic unit is an integral part of contemporary optical data processing network. Accordingly, in this paper a method to develop all-optical arithmetic unit has been proposed. The proposed logic unit consists of semiconductor optical amplifier (SOA) whose fast non-linear characteristics have been utilized for the execution of numerous binary logic operations such as AND, OR, NAND, NOR, EXOR, buffer etc., as well as arithmetic operations, for instance half-addition and half-subtraction, etc. Numerical simulations for the various logic operations have been realized and output verified for the 100 Gbps data rate. Numerical executions have been also done for the crucial key parameters as the bias voltage, confinement factor, and laser power, yielded with good extinction ratio more than 10 dB. The proposed design consists of SOA with benefits of design as rapid switching speed, consumes low power and avoids optoelectronic translation. The design is having with good prospect for impending all optical complex computing networks.

Memcomputing and Nondestructive Reading in Functional Ferroelectric Heterostructures

The storage and processing of information on the same device, known as $m\phantom{\rule{0}{0ex}}e\phantom{\rule{0}{0ex}}m\phantom{\rule{0}{0ex}}c\phantom{\rule{0}{0ex}}o\phantom{\rule{0}{0ex}}m\phantom{\rule{0}{0ex}}p\phantom{\rule{0}{0ex}}u\phantom{\rule{0}{0ex}}t\phantom{\rule{0}{0ex}}i\phantom{\rule{0}{0ex}}n\phantom{\rule{0}{0ex}}g$, is a next-generation approach to computing. To this end, the authors present a ferroelectric-insulator-ferroelectric memcapacitor, based on different polarization configurations in the two ferroelectric layers. This setup allows digital and analog memory applications augmented by binary logic operations based on capacitive switching. Multiple stable capacitive states offer many possibilities: simple memory cells with nondestructive reading and improved fatigue; neuromorphic or chaotic circuits; low power consumption; simplified architectures; and reduced manufacturing cost.

An Expert System for Assessing Technogenic Risks of Electrical Installations Using Temporal Logic

The article presents an expert system in which knowledge bases formalize technogenic risks in electrical installations of agricultural enterprises. The knowledge bases contain rules for the influence of risk factors on the value of the technogenic risk of the electrical installations. The rules are described as a set of fuzzy linguistic statements. Fuzzy linguistic statements can be temporal. Simple temporal statements are formed by application to a simple linguistic statement of one of the unitary operations of the past time “always in the past” or “at some time in the past” of temporal logic. Temporal composite statements are formed of simple statements using the binary fuzzy logical operations “AND,” “OR,” and “priority AND” as ligaments. Using the developed expert system, estimation of the risk of an accident at an electrical installation of AO Altaikraienergo Network Co. was carried out both without and with the use of temporal operators. In the first case, magnitude of the risk of an accident (basis) RB =2.3 × 10–4, which is evaluated as valid. In the second case (RT =1.4 × 10–3), an unacceptable (high) risk was obtained. Analysis of electrical facilities of the considered production facility also confirmed noncompliance with requirements of electrical safety. Our research showed that the proposed expert system for assessing technogenic risks of electrical installations using temporal logic gives a more adequate assessment of the technogenic safety of the considered production facility.

Detection of Various Biomarkers and Enzymes via a Nanocluster-Based Fluorescence Turn-on Sensing Platform.

The profiling of disease-related biomarkers is an essential procedure for the accurate diagnosis and intervention of metabolic disorders. Therefore, the development of ultrasensitive and highly selective fluorogenic biosensors for diverse biomarkers is extremely desirable. There is still a considerable challenge to prepare nanocluster-based fluorescence turn-on probes capable of recognizing multiple biomolecules. We herein provide a novel nanocluster-based chemical information processing system (CIPS) for the programmable detection of various metabolites and enzymes. This CIPS consists of biocatalytic reactions between substrates and their respective oxidases to generate H2O2, which was then employed to synthesize bright fluorescent silver nanoclusters (Ag NCs). Utilizing this system, we are able to accurately probe a series of substrates/corresponding oxidases with high sensitivity and specificity, including glucose/glucose oxidase, uric acid/uric acid oxidase, sarcosine/sarcosine oxidase, choline/choline oxidase, xanthine/xanthine oxidase, and lactic acid/lactic acid oxidase. Furthermore, this metabolite profiling CIPS can be integrated with binary logic operations, which create an intelligent tool for the high-throughput screening of various diseases in vitro (e.g., diabetes, gout, prostate cancer, cardiovascular disease, and lactic acidosis).

GXNOR-Net: Training deep neural networks with ternary weights and activations without full-precision memory under a unified discretization framework

Although deep neural networks (DNNs) are being a revolutionary power to open up the AI era, the notoriously huge hardware overhead has challenged their applications. Recently, several binary and ternary networks, in which the costly multiply-accumulate operations can be replaced by accumulations or even binary logic operations, make the on-chip training of DNNs quite promising. Therefore there is a pressing need to build an architecture that could subsume these networks under a unified framework that achieves both higher performance and less overhead. To this end, two fundamental issues are yet to be addressed. The first one is how to implement the back propagation when neuronal activations are discrete. The second one is how to remove the full-precision hidden weights in the training phase to break the bottlenecks of memory/computation consumption. To address the first issue, we present a multi-step neuronal activation discretization method and a derivative approximation technique that enable the implementing the back propagation algorithm on discrete DNNs. While for the second issue, we propose a discrete state transition (DST) methodology to constrain the weights in a discrete space without saving the hidden weights. Through this way, we build a unified framework that subsumes the binary or ternary networks as its special cases, and under which a heuristic algorithm is provided at the website https://github.com/AcrossV/Gated-XNOR. More particularly, we find that when both the weights and activations become ternary values, the DNNs can be reduced to sparse binary networks, termed as gated XNOR networks (GXNOR-Nets) since only the event of non-zero weight and non-zero activation enables the control gate to start the XNOR logic operations in the original binary networks. This promises the event-driven hardware design for efficient mobile intelligence. We achieve advanced performance compared with state-of-the-art algorithms. Furthermore, the computational sparsity and the number of states in the discrete space can be flexibly modified to make it suitable for various hardware platforms.

XOR Logic Gate by Carbon/Metal Nanoinks Based on a Double-Stage Optical Kerr Gate Configuration

Two-input binary exclusive-or logic operations were presented by the assistance of multiwall carbon nanotubes in a double-stage optical Kerr gate scheme with two control beams. The samples were prepared by the aerosol pyrolysis method and decorated by platinum nanoparticles using a chemical vapor deposition technique. The nanostructures were suspended in ethanol to obtain carbon/metal nanoinks with different concentrations and then randomly distributed networks integrated in thin film form were fabricated. Polarization-selectable functions were obtained in the double-stage scheme by using nanosecond third-order nonlinear optical effects at 532 nm wavelength exhibited by the samples. Potential applications for ultrafast identification and encryption of nonlinear optical signals were discussed.

Programmable microfluidic logic device fabricated with a shape memory polymer.

Manipulation of particles in a microfluidic system is an important research subject in biomedical engineering. However, most conventional passive techniques for particle control have difficulties in integrating other functions into microfluidic channels. A unique microfluidic valve was proposed in this study for switchable particle control by employing a shape memory polymer (SMP). A microfluidic logic device can be programmed based on deformation of the SMP microchannel constructed on a poly(dimethylsiloxane) (PDMS) film. Particles in a viscoelastic flow were focused at preferred equilibrium locations by the competition between inertia and elastic forces. The channel shape played an important role in determining those forces in the channel. Hydrodynamic behavior and shape recovery behavior of the SMP microchannel were modeled theoretically. It was confirmed that the particle valve prepared with the SMP implemented a programmable binary logic operation in the microfluidic channel.

Realization of quantum logic operations in coupled oscillators with third order nonlinearity under influence of Gaussian pulses

The possibility of realization of unary and binary quantum logic operations in a system with coherently correlated Kerr cells taking into account the dissipation was considered and established. The time characteristics of the system for realization of quantum logic operations were studied.