Binary Encoder Research Articles

Design and simulation of a universal N-bit binary encoder using single electron linear threshold gates

The Single-Electron (SE) Linear Threshold Gate (LTG) is one of the basic functional Single-Electron Nano-Devices (SENDs). In this paper, using a SE LTG as the basic building block in an artificial neural network (ANN) is reviewed. A universal SE ANN 2-bit (4-to-2) binary encoder, which is composed of only two SE LTGs, is designed. The detailed schematic diagrams along with the corresponding SIMON 2 simulation results (that include input and output signals as well as the stability diagrams) of the designed binary encoder are included. The proposed SE ANN 2-bit binary encoder can easily be generalized to design n-bit binary encoders. As an example of this generalization, a SE ANN 3-bit (8-to-3) binary encoder, which is composed of three SE LTGs, is designed and its SIMON 2 simulation results are presented. This design is compared with the previously reported C-SET 3-bit binary encoder.

A high-throughput fully hardwired CABAC encoder for QFHD H.264/AVC main profile video

We propose a very high-throughput fully hardwired CABAC encoder for ultra-high resolution video. Our architecture includes hardwired circuits for binarization, context modeling, neighbor data access, and a six-stage pipelined binary arithmetic encoder (BAE). Our BAE can encode multiple bins per cycle. In order to keep up with the BAE throughput, we propose acceleration methods for the bin and context index generations of several types of frequent syntax elements (SE). We further propose a novel architecture that shortens the critical path of renormalization and bitstream generation. Our design can encode 1.42 bins per cycle on the average, and it achieves a throughput of 315 Mbin/sec. Simulation results show that it can real-time encode QFHD (3840×2176) video at 30 fps or 1080 HD (1920×1088) at 60 fps for H.264/AVC main profile, level 5.1 by running at 222 MHz. We have successfully integrated the proposed CABAC encoder into an H.264/AVC encoder system using an SoC platform.

Interblock memory for turbo coding

We investigate a binary code, which is implemented by serially concatenating a multiplexer, a multilevel delay processor, and a signal mapper to a binary turbo encoder. To achieve improved convergence behavior, we modify the binary code by passing only a fraction of the bits in the turbo code through the multilevel delay processor and the signal mapper. Two decoding methods are discussed and their performances are evaluated.

Optical Spatial Quantization for Higher Performance Analog-to-Digital Conversion

A novel optical spatial quantized analog-to-digital conversion scheme for real-time conversion at ultrahigh sampling frequencies is presented. At each sampling instant, the analog input voltage deflects an optical sampling pulse onto an array of photodetectos. The output code is derived from the output voltages of the photodetectors on which the optical beam lands. Particular benefits of the proposed architecture are significant reduction in jitter through the use of a mode-locked laser to generate the sampling pulses, high quantization bandwidth through a fully optical quantization scheme, and the system simplicity through the use of just one phase modulator and an embedded binary encoder in the binary-connected photodetector arrays. We experimentally demonstrate an eight-level quantization consuming only 7.2 pJ per quantization with 18-GHz bandwidth, projected to an estimated bandwidth of 30 GHz. Measured 8-ps full-width half-maximum photodetectors output voltages promise the potential of realizing a 3-bit 125-GS/s analog-to-digital converter.

Memory-Efficient Semi-Quasi Renormalization for Arithmetic Coding

We propose a highly efficient, look-up table-based, renormalization method that can be used by any binary arithmetic encoder with the follow-on procedure. It replaces the time-consuming branching operations in the renormalization process with table look-ups and some simple bit-wise operations. We show that our new renormalization method outperforms the currently used ones with much less memory requirement than the previously known, table-based quasi-coder

Codes based on a trellis cut-set transformation. I. Rotationally invariant codes

Let a trellis section /spl Tscr/ generate a trellis code /spl Cscr/. We study two trellis sections based on /spl Tscr/, a trellis section /spl Tscr//sub cs/ and a trellis section /spl Tscr//sub de/. We show that /spl Tscr/ can be transformed to a cut-set trellis section /spl Tscr//sub cs/, which is equivalent to /spl Tscr/ in the sense that both /spl Tscr/ and /spl Tscr//sub cs/ generate /spl Cscr/ and both /spl Tscr/ and /spl Tscr//sub cs/ have the same decoding complexity. A differential encoder trellis section is equivalent to the trellis section obtained by following /spl Tscr/ with a differential encoder. It is shown that both /spl Tscr//sub cs/ and /spl Tscr//sub de/ have inverse transform trellis sections. A differential encoder trellis section generates a rotationally invariant (RI) code in a particularly simple and straightforward way. But an RI code need not have a differential encoder trellis section. However, for all of the RI codes examined here, we show that the cut-set trellis section can be arranged into a differential encoder trellis section. This means that these codes can be decomposed into an encoder followed by a differential encoder. Further we show that when /spl Tscr/ is formed using a linear binary convolutional encoder and a mapping by set partitioning, then /spl Tscr/ followed by a differential encoder gives an RI code which in some cases is as good as the best previously known codes, after applying the inverse transform to /spl Tscr//sub de/.

Asynchronous analogue-to-digital converter for single-electroncircuits

An analogue-to-digital conversion scheme based on the e-periodic transfer characteristics of an SET inverter is proposed. The authors demonstrate the 4 bit analogue-to-digital converter performance using Monte-Carlo simulation in which an SET inverter implements a binary quantiser and encoder for one significant bit. This scheme can be easily extended to higher order bits.

Block Codes Formed from Catastrophic Convolutional Encoders: Applications to BCM

This article describes the construction of block codes derived from trellis termination of a binary catastrophic convolutional encoder. Two construction methods are considered: the Zero Tail (ZT) method and a modified Tail Biting (TB) method. 4-PSK block coded modulation (BCM) schemes are designed based on the constructed codes. These schemes outperform similar schemes derived from the best non-catastrupltic encoder.

Mapping of Trellises Associated with General Encoders onto High-Performance VLSI Architectures

A rate 1/n binary generic convolutional encoder is a shift-register circuit where the inputs % MathType!MTEF!2!1!+-% feaafiart1ev1aaatCvAUfeBSjuyZL2yd9gzLbvyNv2CaerbuLwBLn% hiov2DGi1BTfMBaeXatLxBI9gBaerbd9wDYLwzYbItLDharqqtubsr% 4rNCHbGeaGqiVu0Je9sqqrpepC0xbbL8F4rqqrFfpeea0xe9Lq-Jc9% vqaqpepm0xbba9pwe9Q8fs0-yqaqpepae9pg0FirpepeKkFr0xfr-x% fr-xb9adbaqaaeGaciGaaiaabeqaamaabaabaaGcbaGaamyEamaaBa% aaleaacaWGRbaabeaaaaa!3807!<![CDATA[$$\left( {\Delta \theta ,\Delta f} \right)$$ are information bits and the outputs % MathType!MTEF!2!1!+-% feaafiart1ev1aaatCvAUfeBSjuyZL2yd9gzLbvyNv2CaerbuLwBLn% hiov2DGi1BTfMBaeXatLxBI9gBaerbd9wDYLwzYbItLDharqqtubsr% 4rNCHbGeaGqiVu0Je9sqqrpepC0xbbL8F4rqqrFfpeea0xe9Lq-Jc9% vqaqpepm0xbba9pwe9Q8fs0-yqaqpepae9pg0FirpepeKkFr0xfr-x% fr-xb9adbaqaaeGaciGaaiaabeqaamaabaabaaGcbaGaamyEamaaBa% aaleaacaWGRbaabeaaaaa!3807!<![CDATA[$$\left( {\Delta \theta ,\Delta f} \right)$$ are blocks of n bits generated as linear combinations on the appropriate shift register contents. The decoding of the outputs of a convolutional encoder can be carried out by the well-known Viterbi algorithm. The communication pattern of the Viterbi Algorithm is given as a graph, called trellis, associated to the state diagram of the corresponding encoder. In this paper we present a methodology that permits the efficient mapping of the Viterbi algorithm onto a column of an arbitrary number of processors. This is done through the representation of the data flow by using mathematical operators which present an inmediate hardware projection. A single operator string has been obtained to represent a generic encoder through the study of the data flow of free-forward encoders and feed-back encoders. The formal model developed is employed for the partitioning of the computations among an arbitrary number of processors in such a way that the data are recirculated opimizing the use of the processors and the communications. As a result, we obtain a highly regular and modular architecture suitable for VLSI implementation.

Subnanosecond sampling all‐optical analog‐to‐digital converter using symmetric self‐electro‐optic effect devices

A system to convert an analog optical system to a digital one in an optical environment using basic symmetric self-electro-optic effect devices (S-SEEDs) is detailed. It is shown that quantization and binary encoding can readily be achieved using the logic capabilities of S-SEEDs. A quantizer prototype has been constructed and proper op- eration observed. The effect of the hysteresis inherent in the S-SEED is discussed and three techniques are proposed to eliminate the problems caused by hysteresis. The logic operations needed for the construction of the binary encoder with the minimum number of S-SEEDs are facili- tated using a reference beam. An alternate, efficient design of the binary encoder is also presented. Using a novel time quantization technique, a sampling rate in excess of 1 gigasamples/s is achievable. © 1996 So- ciety of Photo-Optical Instrumentation Engineers. Subject terms: analog-to-digital conversion; quantization; symmetric-self-electro- optic effect devices; hysteresis; binary encoding logic.

Fully parallel superconducting analog-to-digital converter

The authors present measurements that follow up on a design of a 3-b wideband analog-to-digital converter (ADC) given by E. Fang et al. (IEEE Trans. Magn., vol.27, no.3, p.2891-4, 1991). The original design has been modified, and some circuit parameters have been changed to optimize the margins. Based on this modified design, the authors have fabricated and were able to demonstrate the functionality not only of simple logic gates, including inverters, AND, OR, NAND, NOR, and XOR, but also of much more complicated combinations, including a complete 2-b ADC and a complete 3-b binary encoder. After a brief description of the design and modifications, low-speed tests of these circuits are presented and discussed. Simulations have shown that the complete 3-b ADC can work up to 5 GHz.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A novel analog-to-digital conversion architecture using electron waveguides

An analog-to-digital (A/D) conversion architecture based on the quantized conductance of electron waveguides has been demonstrated. In the scheme, a dual electron waveguide (DWG) device implements a binary quantizer and encoder for one significant bit of resolution. The conductance values of the one and off states in the binary code are 2e/sup 2//h and zero, respectively. By cascading multiple DWG devices, higher order significant bits can be attained. Here the first significant bit and the second significant bit of the analog-to-digital conversion architecture using a DWG device fabricated in an AlGaAs/GaAs modulation-doped heterostructure are shown.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

SNR merits of binary modulation codes in equalized digital recording systems

For a digital recording system with a binary modulation encoder and a linearly dispersive channel with additive noise, the author determines optimum mean-square performance of the linear, partial-response, and decision-feedback equalizers. The analysis revolves around the power spectral density A( Omega ) of the code and the folded signal-to-noise ratio X( Omega ) of the channel. The latter function is analyzed for stylized optical and magnetic recording channels. For all equalizers it is shown that the effect of coding is similar to increasing X( Omega ) by an additive portion 1/A( Omega ). This favors depressions of A( Omega ) at frequencies where X( Omega ) is poor. However, for A( Omega ) to have any depressions, the signaling rate must be increased with respect to uncoded storage, and this inevitably degrades X( Omega ). At high information densities the degradation is often too large for coding to be rewarding. Examples serve to illustrate these results. >

Bit probabilities of optimal binary source codes

The probabilities of the bits produced by an optimal binary source encoder for a memoryless source are analyzed. The class of sources for which the probability of zero must equal 1/2 for any such encoder is described. Procedures that minimize (maximize) the absolute difference of the bit probabilities are discussed. Corresponding upper bounds are derived and compared for the class of uniform sources.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Reconsidering natural binary encoding for absolute position measurement application

It is well known that absolute encoders using natural binary codes are prone to reading errors because more bits can change between adjacent scale sectors. Some solutions, such as V-scan, were proposed to solve this problem, but they required too many additional reading heads and decoding circuits to be competitive with the reduced complexity obtained when using the Gray code. The author describes a novel natural binary absolute encoder using an original scanning technique that solves more efficiently the problem of the inherent code reading errors. It is shown that for the same nominal resolution, the complexity of the encoder is similar to, if not better than, that of the Gray-type encoder. >

Design of coded CPFSK modulation systems for bandwidth and energy efficiency

Consideration is given to the problems related to the design of M-ary continuous-phase frequency-shift keying (CPFSK) systems with modulation index h=J/M, combined with eternal rate r binary convolution encoders. The following questions are raised and answered: (1) how should different encoder-modulator systems be compared and how can comparable systems be recognized from the system parameters, i.e. M, h, and r?; (2) what are the limits on the information rate per unit bandwidth, versus signal-to-noise ratio, when reliable transmission is required?; (3) how does one choose the system parameters M, h, and r when the overall system has to achieve a specified performance?; and (4) how does one design the external rate r binary convolutional encoder to put in front of the M-ary CPFSK modulation system with h=J/M? A simple approximation for the bandwidth of a CPFSK signal is given and shown to be sufficiently accurate for system design purposes. The design of the external convolutional encoder is carried out in a novel way that leads to fewer states in the combined encoder-modulator system and thus yields improved performance for a given demodulation-decoding complexity compared to previous approaches for the design of coded CPFSK systems.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Coset codes. I. Introduction and geometrical classification

Practically all known good constructive coding techniques for bandlimited channels, including lattice codes and various trellis-coded modulation schemes, can be characterized as coset codes. A coset code is defined by a lattice partition Lambda / Lambda ' and by a binary encoder C that selects a sequence of cosets of the lattice Lambda '. The fundamental coding gain of a coset code, as well as other important parameters such as the error coefficient, the decoding complexity, and the constellation expansion factor, are purely geometric parameters determined by C Lambda / Lambda '. The known types of coset codes, as well as a number of new classes that systematize and generalize known codes, are classified and compared in terms of these parameters.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Four-valued interface circuits for NMOS VLSI

Abstract In this paper we present radix 4 to binary encoder and decoder interface circuits for NMOS VLSI. The circuits can be implemented using standard binary NMOS fabrication processes and are designed to operate correctly over the entire target range of device parameters specified by MOSIS. They have been simulated using SPICE with the typical parameters provided by MOSIS, and found to work correctly. Thus these circuits can be readily used to reduce pinouts of binary NMOS logic chips, and thereby allow significant cost savings.

The Correlation of the Output of a Binary Convolutional Encoder

In this paper we discuss the correlation properties of the output of a binary convolutional encoder. We consider both random statistically independent inputs and first-order Markov inputs. It is shown that for random inputs, the ensemble average of the product of the outputs of a convolutional encoder taken two at a time is always either 0 or 1, and that for almost all good codes the ensemble average is always 0.

Correction of errors in multilevel Gray coded data

In this paper we present a new error-control technique intended for use in 2^l -level data-transmission systems that employ Gray coding to transform a binary source sequence into the 2^l -ary transmitted sequence. The codes, which we call i -compressed codes, make use of the structure of binary codes and have the property that for some integer i , 1 \leq i \leq l , transmission errors can be corrected if the erroneously received signals lie less than 2^{i-1} levels from the corresponding correct, or nominal signal levels. The number of such errors that can be corrected is related to the error-correcting capability of the underlying binary code used in the construction. In return for this restriction on the magnitude of correctable errors in the received signal, these codes have higher rates than binary codes of comparable length (in bits) and number of correctable errors. Hence in applications where it can be assumed that the fraction of errors exceeding a certain magnitude is negligible (or at least tolerable), this technique is more efficient than the conventional practice of placing a binary encoder between the data source and modulator and a binary decoder between the demodulator and data sink. Furthermore, although the i -compressed codes are nonbinary, the decoding algorithm is that of the underlying binary code plus a small amount of additional processing; hence it is generally simpler to implement than other nonbinary decoding algorithms. It is also observed that the rate of an i -compressed code is always greater than that of the underlying binary code. Thus certain classes of low-rate binary codes that have simple decoding algorithms can be used as underlying codes in the construction of high-rate easily decodable i -compressed codes. Finally, for the case i = 1 , encoding and decoding becomes exceptionally simple and for this case it is possible to make use of soft decisions at the receiver to improve the performance.