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Abstract
Abstract In this paper we present radix 4 to binary encoder and decoder interface circuits for NMOS VLSI. The circuits can be implemented using standard binary NMOS fabrication processes and are designed to operate correctly over the entire target range of device parameters specified by MOSIS. They have been simulated using SPICE with the typical parameters provided by MOSIS, and found to work correctly. Thus these circuits can be readily used to reduce pinouts of binary NMOS logic chips, and thereby allow significant cost savings.
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