Binary Encoder Research Articles

Monolithic integrated superconducting nanowire digital encoder

Superconducting digital circuits are promising technologies that can overcome bottlenecks in both classical and quantum computation due to their ultra-high operation speed and extremely low power dissipation. Superconducting nanowire cryotrons (nTrons) are emerging as one type of superconductor switching devices, offering advantages complementary to conventional Josephson junctions. Achieving monolithic integration of a reasonable number of nTrons into a functional digital circuit is a crucial step to extend its application. In this study, we constructed a monolithic integrated nTron-based binary encoder, which includes input fanout circuits, on-chip biasing, combinational logic routing and multi-gate nTrons. This represents a monolithic nTron digital circuit comprising 137 nTron gates, 424 resistors, 274 inductors, and 164 vias developed using a two-superconducting-layer fabrication process. The performance of this monolithic nTron encoder surpasses that of our previously demonstrated circuit with discrete nTron components. The maximum bias margin is 28% for the fanout circuit and 60% for the multi-gate nTron when using a signal generator, while the minimum timing jitter is 40 ps. The total power dissipation mainly from biasing resistors is 19.6 μW, making it more power efficient than RSFQ encoders. The encoder is then packaged and connected with a superconducting nanowire single-photon detector array for demonstrating its function of addressing pixel locations. Compared to the conventional readout, the nTron encoder shows a minimum readout error rate lower than 10−4 and reduces the readout RF lines from 15 to 4. The design and fabrication technologies could enrich integrated nTron digital circuits beyond current limits and promote their applications in classical and quantum systems.

A new architecture of Thermometer to Binary code encoder for 4 - bit FLASH ADC in 45nm CMOS process

A new architecture of Thermometer to Binary code encoder for 4 - bit FLASH ADC in 45nm CMOS process

Binary-Convolution Data-Reduction Network for Edge–Cloud IIoT Anomaly Detection

Industrial anomaly detection, which relies on the analysis of industrial internet of things (IIoT) sensor data, is a critical element for guaranteeing the quality and safety of industrial manufacturing. Current solutions normally apply edge–cloud IIoT architecture. The edge side collects sensor data in the field, while the cloud side receives sensor data and analyzes anomalies to accomplish it. The more complete the data sent to the cloud side, the higher the anomaly-detection accuracy that can be achieved. However, it will be extremely expensive to collect all sensor data and transmit them to the cloud side due to the massive amounts and distributed deployments of IIoT sensors requiring expensive network traffics and computational capacities. Thus, it becomes a trade-off problem: “How to reduce data transmission under the premise of ensuring the accuracy of anomaly detection?”. To this end, the paper proposes a binary-convolution data-reduction network for edge–cloud IIoT anomaly detection. It collects raw sensor data and extracts their features at the edge side, and receives data features to discover anomalies at the cloud side. To implement this, a time-scalar binary feature encoder is proposed and deployed on the edge side, encoding raw data into time-series binary vectors. Then, a binary-convolution data-reduction network is presented at the edge side to extract data features that significantly reduce the data size without losing critical information. At last, a real-time anomaly detector based on hierarchical temporal memory (HTM) is established on the cloud side to identify anomalies. The proposed model is validated on the NAB dataset, and achieves 70.0, 64.6 and 74.0 on the three evaluation metrics of SP, RLFP and RLFN, while obtaining a reduction rate of 96.19%. Extensive experimental results demonstrate that the proposed method achieves new state-of-the-art results in anomaly detection with data reduction. The proposed method is also deployed on a real-world industrial project as a case study to prove the feasibility and effectiveness of the proposed method.

Probabilistic constellation shaping-aided underwater acoustic communication with vector approximate message passing iterative equalization.

A probabilistic constellation shaping (PCS)-aided single-carrier transceiver is proposed to improve spectral efficiency for underwater acoustic (UWA) communications. At the transmitter, the information bits are input into a distribution matcher followed by a systematic binary encoder, which yields a sequence of sign bits with a uniform distribution and a sequence of amplitude bits with a non-uniform distribution. Based on these two sequences, the PCS is then realized by mapping coded bits onto a quadrature amplitude modulation constellation. At the receiver, an improved frequency-domain turbo equalizer based on the vector approximate message passing (VAMP) is proposed for the PCS-UWA communication system to eliminate the multipath interference. It exploits the a priori symbol probability information benefiting from the PCS at the beginning of the turbo iteration and over the self-iteration of the VAMP soft equalizer, improving the symbol detection performance. Finally, the first experimental demonstration of a deep-sea PCS-UWA communication system and numerical simulation of shallower water are presented. The experimental results reveal the PCS-UWA communication system significantly outperforms traditional systems with no PCS. Also, the proposed receiver is superior to the classical adaptive turbo equalizer based on the improved proportionate normalized least mean square algorithm even with data reuse.

Design of High Performance and Power Efficient Flash ADC

In this paper, Flash Analog to digital converter is implemented. The designed Flash ADC consists of a resistive ladder network, comparators, the thermometer to a binary encoder and the entire design is carried out using Tanner tools employing 180nm technology. The reference voltage applied to the resistive ladder network is 1.8V. A two-stage operational amplifier is used as a comparator in the flash ADC. Here, we are modifying the structure of operational Amplifier using Power Gating Technique. Binary code is obtained from the thermometer code by utilizing a Mux based encoder by designing the MUX in domino Logic. The major problem that usually appears in flash ADC is as the number of resolution bits increases, the Area, as well as the power consumption of the circuit, also increases. In this paper, we principally concentrated to lessen the propagation delay of the ADC by optimizing encoder circuitry. With the purpose of reducing latency, Encoder is implemented using 2:1 mux based on Pseudo NMOS Logic. Performance parameters of Flash ADC such as delay as well as average power are calculated and compared.

Comprehensive Composition to Spot Intrusions by Optimized Gaussian Kernel SVM

The intrusion interjects network devices and holds a switch of the network with the command which regulates the programmer and programmer govern the nasty code inoculated in the device for attaining intelligence about the devices. In this paper, the researchers organized the IDS framework by using machine learning algorithms like Linear SVM, RBF SVM, Sigmoid SVM, and Polynomial SVM to detect intrusions and estimate the performance of numerous algorithms for attaining the optimized algorithm. The researchers utilized the KDDCUP99 for equating the accuracy, precision, and recall of the algorithms, and for classifications, the researchers utilized the binary encoder tools. The performance analysis calculates that RBF SVM is the finest classifier amongst the other SVMs, and the prediction report predicts that Linear SVM results with 99.2% accuracy, Sigmoid SVM results with 99.7% accuracy, Polynomial SVM results with 99.5% accuracy, and RBF SVMs results with 99.99% accuracy.

Action Recognition From a Single Coded Image.

The unprecedented success of deep convolutional neural networks (CNN) on the task of video-based human action recognition assumes the availability of good resolution videos and resources to develop and deploy complex models. Unfortunately, certain budgetary and environmental constraints on the camera system and the recognition model may not be able to accommodate these assumptions and require reducing their complexity. To alleviate these issues, we introduce a deep sensing solution to directly recognize human actions from coded exposure images. Our deep sensing solution consists of a binary CNN-based encoder network that emulates the capturing of a coded exposure image of a dynamic scene using a coded exposure camera, followed by a 2D CNN for recognizing human action in the captured coded exposure image. Furthermore, we propose a novel knowledge distillation framework to jointly train the encoder and the action recognition model and show that the proposed training approach improves the action recognition accuracy by an absolute margin of 6.2%, 2.9%, and 7.9% on Something 2-v2, Kinetics-400, and UCF-101 datasets, respectively, in comparison to our previous approach. Finally, we built a prototype coded exposure camera using LCoS to validate the feasibility of our deep sensing solution. Our evaluation of the prototype camera show results that are consistent with the simulation results.

Terahertz binary coder based on graphene metasurface

In this paper, we demonstrate a terahertz (THz) binary encoder based on graphene metasurface. The unit cell of the device consists of two parallel metal bars and two split-ring resonators (SRRs) embedded with two graphene ribbons. For two SRRs in the unit cell, one is connected to an electrode on the right side, and the other is connected to the electrode on the left side of the device, respectively. When no voltage is applied, the device has two passbands whose central frequencies locating at 0.85 THz and 1.14 THz, respectively. Unlike many THz tunable filters which modulate the amplitude of different bands at the same time, this encoder can achieve separately modulation of each passband. By electrically adjusting the Fermi energy of graphene on each SRR individually, the maximum modulation depth at the two central frequencies can be up to 80% and 87%, respectively. Furthermore, the function of THz frequency range binary coding is realized, i.e., four different binary coders of 11, 10, 01 and 00 are obtained in the transmission. Our work paves a new way for the development of multifunctional integrated THz devices, which will be of great significance in THz switching, communication and one-chip integrated THz system.

Low-power sector-based transition reduction bus encoding technique in SOC interconnects

The data word transmission process on an on-chip bus results in the switching of data bits on bus wires, which charges and discharges the capacitance associated with the wires. Consequently, dynamic power dissipation and increase in delay occurs. Data word transmission is required to change data values that are transmitted over these buses for reducing the transition activity, thereby decreasing the power consumption and delay of the bus. Bus encoding is the commonly used technique to reduce the transition activity of the bus. In this study about the memory bus encoding, i.e., a dynamic sector encoding technique, that is, a sector-based encoding technique is proposed. In this technique, the source word space is divided into a number of sectors with a unique identifier. A dynamic sector (DS) encoder reduces the number of transitions 19.23% more than that reduced by a binary encoder. DS encoding technique is a novel method that reduces the number of transition then reduces the power dissipation and delay when compared to previous encoding techniques which are used in the memory operations.

Optical Binary Encoder and Decoder With Ultra-Low Power Consumption

We propose and experimentally demonstrate on-chip optical encoder and decoder with ultra-low power consumption. The key device is a silicon photonic crystal (PC) L3 nanocavity with small mode volume. Consequently, the nonlinear effects in the nanocavity are strongly enhanced and could be excited by lower powers. Leveraging different optical power levels, the transmission spectra of the PC nanocavity could be flexibly manipulated. By utilizing proper determining powers, the output powers could be defined as the corresponding optical codes. In the experiment, the binary encoder and decoder are successfully demonstrated with required optical powers of 0.04 mW and 0.032 mW, respectively. Unlike most previous optical encoders and decoders with high powers (tens of milliwatts) or large size (several square millimeters), our scheme which could simultaneously realize the optical encoder and decoder only requires ultra-low powers as 0.04 mW with a compact size of 100 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . To the best of our knowledge, it is a record combined the power consumption and device size for on-chip optical encoder and decoder.

Methodology and comparative design of an efficient 4‐bit encoder with bubble error corrector for 1‐GSPS flash type ADC

The design of a 4-bit encoder with a bubble error correction of first order is described in this study. Since encoder restricts speed of the flash analogue-to-digital converter (ADC), therefore, an improved and faster encoder is an essential requirement to push its limits. Encoder is divided into two parts: one-hot code generator [or bubble error corrector (BEC)] and binary encoder. Binary encoder proposed in this study is the modified Fat-Tree encoder of types I and II. Three types of BECs which have been compared in this study are OR gate based, NAND gate based and the proposed BEC. The proposed BEC consumes less power and provides better speed as compared to NAND based and OR gate based BECs. It can be further employed for higher order bubble correction as well. The proposed BEC consumes dynamic power of 87.071 μW and leakage power of 18.3563 pW exhibiting the delay of 38.3 ps with 1.8 V supply voltage and 1 GHz clock frequency. It has a power-delay product of 3.335 fJ, energy-delay product of 127.7305 Js and an intrinsic area of 4.753 mm 2 .

Energy-Throughput Configurable Design for Video Processing Binary Arithmetic Encoder

Video encoding draws high research interest, due to the enormous demand for video traffic and real-time encoding for transmission. In video encoding standards such as HEVC (High-Efficiency Video Coding), the final step of the encoding stage is the CABAC (Context-Adaptive Binary Arithmetic Coding). The coding efficiency of the CABAC comes at the cost of increased computational complexity, especially for parallelization purposes, being the BAE (Binary Arithmetic Encoder) the critical part of CABAC. Thus, an important goal is to balance the real-time throughput requirements and the power/energy consumption in the design of BAE dedicated hardware. This work introduces a novel configurable high-throughput BAE design, named ET-BAE, utilizing a combination of a new modified Multiple-Bypass Bins Scheme (MBBS) and a power-saving approach into a single ASIC design with two-mode configuration. Synthesis and power-analysis results show that the configurable BAE design, the first of its kind with this feature, is more energy-efficient and less area consuming than utilizing non-configurable versions. The ET-BAE is able to accomplish the same real-time requirements of its competitors.

БАГАТОШАРОВА МОДЕЛЬ ТА МЕТОД НАВЧАННЯ ДЛЯ ДЕТЕКТУВАННЯ ШКІДЛИВОГО ТРАФІКУ НА ОСНОВІ АНСАМБЛЮ ДЕРЕВ РІШЕНЬ

The model and training method of multilayer feature extractor and decision rules for a malware traffic detector is proposed. The feature extractor model is based on a convolutional sparse coding network whose sparse encoder is approximated by a regression random forest model according to the principles of knowledge distillation. In this case, an algorithm of growing sparse coding neural gas has been developed for unsupervised training the features extractor with automatic determination of the required number of features on each layer. As for feature extractor, at the training phase to implement of sparse coding the greedy L1-regularized method of Orthogonal Matching Pursuit was used, and at the knowledge distillation phase, the L1-regularized method at the least angles (Least regression algorithm) was additionally used. Due to the explaining-away effect, the extracted features are uncorrelated and robust to noise and adversarial attacks. The proposed feature extractor is unsupervised trained to separate the explanatory factors and allows to use the unlabeled training data, which are usually quite large, with the maximum efficiency. As a model of the decision rules proposed to use the binary encoder of input observations based on an ensemble of decision trees and information-extreme closed hyper-surfaces (containers) for class separation, that are recovery in radial-basis of Hemming' binary space. The addition of coding trees is based on the boosting principle, and the radius of class containers is optimized by direct search. The information-extreme classifier is characterized by low computational complexity and high generalization capacity for small sets of labeled training data. The verification results of the trained model on open CTU test data sets confirm the suitability of the proposed algorithms for practical application since the accuracy of malware traffic detection is 96.1 %.

An Efficient Hardware Implementation of Residual Data Binarization in HEVC CABAC Encoder

HEVC-standardized encoders employ the CABAC (context-based adaptive binary arithmetic coding) to achieve high compression ratios and video quality that supports modern real-time high-quality video services. Binarizer is one of three main blocks in a CABAC architecture, where binary symbols (bins) are generated to feed the binary arithmetic encoder (BAE). The residual video data occupied an average of 75% of the CABAC’s work-load, thus its performance will significantly contribute to the overall performance of whole CABAC design. This paper proposes an efficient hardware implementation of a binarizer for CABAC that focuses on low area cost, low power consumption while still providing enough bins for high-throughput CABAC. On the average, the proposed design can process upto 3.5 residual syntax elements (SEs) per clock cycle at the maximum frequency of 500 MHz with an area cost of 9.45 Kgates (6.41 Kgates for the binarizer core) and power consumption of 0.239 mW (0.184 mW for the binarizer core) with NanGate 45 nm technology. It shows that our proposal achieved a high overhead-efficiency of 1.293 Mbins/Kgate/mW, much better than the other related high performance designs. In addition, our design also achieved a high power-efficiency of 8288 Mbins/mW; this is important factor for handheld applications.

A Superconducting Binary Encoder with Multigate Nanowire Cryotrons.

Many classic and quantum devices need to operate at cryogenic temperatures, demanding advanced cryogenic digital electronics for processing the input and output signals on a chip to extend their scalability and performance. Here, we report a superconducting binary encoder with ultralow power dissipation and ultracompact size. We introduce a multigate superconducting nanowire cryotron (nTron) that functions as an 8-input OR gate within a footprint of approximately 0.5 μm2. Four cryotrons compose a 4-bit encoder that has a bias margin of 18.9%, an operation speed greater than 250 MHz, an average switching jitter of 75 ps, and a power dissipation of less than 1 μW. We apply this encoder to read out a superconducting-nanowire single-photon detector array whose pixel location is digitized into a 4-bit binary address. The small size of the nanowire combined with the low power dissipation makes nTrons promising for future monolithic integration.

FPGA Implementation of CABAC Binary Arithmetic Encoder Based on HEVC

Based on the H.265/HEVC video coding standard,a hardware pipeline structure is implemented in this study in the regular mode of a binary arithmetic encoder in CABAC coding.Based on the characteristics of the algorithm,the hardware architecture of the coding engine is designed and optimized.The probability state data are stored in a SRAM,and the probability estimation updating operation is optimized using a lookup table.The coding data are packaged to simplify the calculation obtained by the update of the probability estimation to optimize the coding speed of the video data stream.Binary arithmetic coding uses a multistage pipeline structure to support four-way parallel encoding.Simulation results show that the hardware of the CABAC binary arithmetic coder can complete the encoding of four bins per clock cycle,which satisfies the higher frame rate of 1080p video real-time encoding requirements.

A Low-Power, High-Speed Readout for Pixel Detectors Based on an Arbitration Tree

In this article, a low-power, high-speed arbitration tree for pixel detector readout is presented. The synchronized, binary tree priority encoder establishes a position-dependent priority list at the start of every time frame. Pixels that indicate the presence of data for readout are sequentially granted access to a shared bus for data transfer to the periphery, without the use of an additional global strobe signal. It can be used for either full frame imaging or zero-suppressed readout, in which case it can simultaneously generate the pixel address. To increase the readout frame rate, the pixel array is subdivided into two halves, which allow interleaved latching of data at the output serializer. The design was implemented in a 65-nm LP-CMOS process for the readout of a $64\times64$ pixel array. Measurement results demonstrate a deadtimeless, full frame imaging rate of ~50 kfps, achieved with a dedicated output for every ( $32\times32$ ) 1024 pixels and for a pixel data packet of 11 bits, with no bit errors detected over 1000 frames. The measured energy per bit is 0.94 pJ.

A 34-FPS 698-GOP/s/W Binarized Deep Neural Network-Based Natural Scene Text Interpretation Accelerator for Mobile Edge Computing

The scene text interpretation is a critical part of the natural scene interpretation. Currently, most of the existing work is based on high-end graphics processing units (GPUs) implementation, which is commonly used on the server side. However, in Internet of Things (IoT) application scenarios, the communication overhead from the edge device to the server is quite large, which sometimes even dominates the total processing time. Hence, the edge-computing oriented design is needed to solve this problem. In this paper, we present an architectural design and implementation of a natural scene text interpretation (NSTI) accelerator, which can classify and localize the text region on pixel-level efficiently in real-time on mobile devices. To target the real-time and low-latency processing, the binary convolutional encoder–decoder network is adopted as the core architecture to enable massive parallelism due to its binary feature. Massively parallelized computations and a highly pipelined data flow control enhance its latency and throughput performance. In addition, all the binarized intermediate results and parameters are stored on chip to eliminate the power consumption and latency overhead of the off-chip communication. The NSTI accelerator is implemented in a 40 nm CMOS technology, which can process scene text images (size of 128 × 32) at 34 fps and latency of 40 ms for pixelwise interpretation with the pixelwise classification accuracy over 90% on ICDAR-03 and ICDAR-13 dataset. The real energy-efficiency is 698 GOP/s/W and the peak energy-efficiency can get up to 7825 GOP/s/W. The proposed accelerator is 7 times more energy efficient than its optimized GPU-based implementation counterpart, while maintaining a real-time throughput with latency of 40 ms.

Optical logic operation via plasmon-exciton interconversion in 2D semiconductors

Nanophotonic devices manipulating light for high-speed computing are a counterpart of speed-limited electronic circuits. Although plasmonic circuits are a promising platform for subwavelength miniaturization, the logic-operation principle is still limited to mimicking those of photonic waveguides using phase shifts, polarization, interference, and resonance. Meanwhile, reconfigurable interconversion between exciton and plasmon engender emerging applications like exciton transistors and multiplexers, exciton amplifiers, chiral valleytronics, and nonlinear excitonics. Here, we propose optical logic principles realized by exciton-plasmon interconversion in Ag-nanowires (NW) overlapped on transition metal dichalcogenides (TMDs) monolayers. Excitons generated from TMDs couple to the Ag-NW plasmons, eventually collected as output signals at the Ag-NW end. Using two lasers, we demonstrate AND gate by modulating single excitons in Ag-NW on MoS2 and a half-adder by modulating dual excitons in lateral WSe2 and WS2. Moreover, a 4-to-2 binary encoder is realized in partially overlapped MoSe2 and MoS2 using four-terminal laser inputs. Our results represent great advances in communication processing for optical photonics integrable with subwavelength architectures.

Improvement of Gray ROM-Based Encoder for Flash ADCs

In this paper, gray ROM-based encoder is proposed for the implementation of flash ADCs encoder block based on converting the conventional 1-of-[Formula: see text] thermometer codes to 2-of-[Formula: see text] codes ([Formula: see text]). The proposed gray ROM-based encoder is composed of three stages. In the first stage, the thermometer codes are converted to 2-of-[Formula: see text] codes by the use of two-input AND and four-input merged AND–OR gates. In the second stage, 2-of-[Formula: see text] codes are turned to [Formula: see text] gray codes and a binary code by a quasi-gray ROM encoder and a binary ROM encoder, respectively. Finally, in the third stage, [Formula: see text] MSB bits and LSB bit are determined by a quasi-gray-to-binary converter and a CMOS inverter, respectively. The advantages of the proposed encoder over the conventional encoder are higher speed of second stage, low power, low area and low latency with the same bubble and meta-stability errors removing capability. To demonstrate the mentioned specifications, two 5-bit flash ADCs with the conventional and proposed encoders in their encoder blocks are analyzed and simulated at 2-GS/s and 3.2-GS/s sampling rates in 0.18-[Formula: see text]m CMOS process. Simulation results show that the ENOBs of flash ADCs with the conventional and proposed encoders are equal. In this case, the proposed encoder outputs are determined to be approximately 30[Formula: see text]ps faster than the conventional encoder at 2 GS/s. The power dissipations of the conventional and proposed encoders were 19.50[Formula: see text]mW and 13.90[Formula: see text]mW at 3.2-GS/s sampling rate from a 1.8-V supply and also the latencies of the encoders were 4 ADC clocks and 3 ADC clocks, respectively. In this case, the number of D-FFs and logic gates of the proposed encoder is decreased approximately by 37% when compared to the conventional encoder.