Bilayer Tunnel Field-effect Transistor Research Articles

Gate Leakage Tunneling Impact on the InAs/GaSb Heterojunction Electron–Hole Bilayer Tunneling Field-Effect Transistor

Among the different types of bilayer tunneling field-effect transistors exploiting interband tunneling phenomena with tunneling directions aligned with gate-induced electric fields, the utilization of InAs/GaSb channels proves to be an appealing means to enhance ON-current levels. Ultrathin channel thicknesses make quantum confinement be the agent that closes the broken gap of the InAs/GaSb heterojunction leading to a staggered gap which blocks the tunneling current in the OFF state. In this paper, the gate leakage tunneling current is analyzed as one of the main critical processes degrading the performance of the proposed structure. Appropriate gate stacks of HfO2/Al2O3 combined with gate-to-drain underlaps are shown to effectively suppress this leakage tunneling, while at the same time, preserve an adequate electrostatic control over the channel. Simulation results for the most optimized configurations feature ON-state levels of up to $400\mu \text{A}/\mu \text{m}$ and subthreshold swings of $\approx 3$ mV/dec over more than 7 decades of current.

Ambipolar leakage suppression in electron–hole bilayer TFET: investigation and analysis

In this paper, we propose and simulate two new structures of electron–hole bilayer tunnel field-effect transistors (EHBTFET). The proposed devices are n-heterogate with $$\hbox {M}_{1}$$ as overlap gate, $$\hbox {M}_{2}$$ as underlap gate and employs a high-k dielectric pocket in the drain underlap. Proposed structure 1 employs symmetric underlaps (Lgs = Lgd = Lu). The leakage analysis of this structure shows that the lateral ambipolar leakage between channel and drain is reduced by approximately three orders, the OFF-state leakage is reduced by one order, and the $$I_{\mathrm{ON}}/I_{\mathrm{OFF}}$$ ratio is increased by more than one order at $$V_\mathrm{{GS}}=V_{\mathrm{DS}} =1.0$$ V as compared to the conventional Si EHBTFET. The performance is improved further by employing asymmetric underlaps ( $$\hbox {Lgs}\ne \hbox {Lgd}$$ ) with double dielectric pockets at source and drain, called as proposed structure 2. The pocket dimensions have been optimized, and an average subthreshold swing of 17.7 mV/dec (25.5% improved) over five decades of current is achieved with an ON current of $$0.23~\upmu \hbox {A}/\upmu \hbox {m}$$ (11% improved) in proposed structure 2 in comparison with the conventional EHBTFET. Further, the parasitic leakage paths between overlap/underlap interfaces are blocked and the OFF-state leakage is reduced by more than two orders. A high $$I_{\mathrm{ON}}/I_{\mathrm{OFF}}\,\hbox {ratio}~>10^{9}$$ (two orders higher) is achieved at $$V_{\mathrm{DS}} =V_{\mathrm{GS}} =1.0~\hbox {V}$$ in the proposed structure 2 in comparison with the conventional one.

Vertical-Structured Electron-Hole Bilayer Tunnel Field-Effect Transistor for Extremely Low-Power Operation With High Scalability

In this paper, a novel vertical-structured electron-hole bilayer tunnel field-effect transistor (V-EHBTFET), which features dual gates located at each side of Si fin, is proposed and its electrical characteristics are examined by a technology computer-aided design simulation depending on device parameters. Comparing with the conventional EHBTFET, V-EHBTFET shows a comparable performance in terms of subthreshold swing, OFF- and ON-state currents, and turn-ON voltage with much higher scalability with the help of a novel device architecture. An exemplary self-aligned process flow is also proposed.

Confinement-induced InAs/GaSb heterojunction electron–hole bilayer tunneling field-effect transistor

Electron–Hole Bilayer Tunneling Field-Effect Transistors are typically based on band-to-band tunneling processes between two layers of opposite charge carriers where tunneling directions and gate-induced electric fields are mostly aligned (so-called line tunneling). However, the presence of intense electric fields associated with the band bending required to trigger interband tunneling, along with strong confinement effects, has made these types of devices to be regarded as theoretically appealing but technologically impracticable. In this work, we propose an InAs/GaSb heterostructure configuration that, although challenging in terms of process flow design and fabrication, could be envisaged for alleviating the electric fields inside the channel, whereas, at the same time, making quantum confinement become the mechanism that closes the broken gap allowing the device to switch between OFF and ON states. The utilization of induced doping prevents the harmful effect of band tails on the device performance. Simulation results lead to extremely steep slope characteristics endorsing its potential interest for ultralow power applications.

Analysis of the Heterogate Electron–Hole Bilayer Tunneling Field-Effect Transistor With Partially Doped Channels: Effects on Tunneling Distance Modulation and Occupancy Probabilities

Within the research in bilayer tunneling field-effect transistors (TFETs) exploiting interband tunneling phenomena with tunneling directions aligned with gate-induced electric fields, simulation results for the heterogate electron–hole bilayer TFET (HG-EHBTFET) showed that this type of devices succeeded in suppressing the parasitic tunneling leakage currents appearing in EHBTFETs as a result of the variable quantization strength inside the channel. In this paper, and conversely to standard approaches with entirely intrinsic channels, we investigate the possibility of modulating the band-to-band tunneling (BTBT) distance by acting on the subband discretization profiles through partially doped channels. We also analyze the impact of this pocket doping inside the channel on the occupancy probabilities involved in the BTBT processes in a germanium HG-EHBTFET.

A Novel Reconfigurable Sub-0.25-V Digital Logic Family Using the Electron-Hole Bilayer TFET

We propose and validate a novel design methodology for logic circuits that exploits the conduction mechanism and the presence of two independently biased gates (“n-gate” and “p-gate”) of the electron-hole bilayer tunnel field-effect transistor (EHBTFET). If the device is designed to conduct only under certain conditions, e.g., when $V_{\mathrm {n-gate}} = V_{\mathrm {DD}}$ and $V_{\mathrm {p-gate}} = 0$ , it then shows an “XOR-like” behavior that allows the implementation of certain logic gates with a smaller number of transistors compared to conventional CMOS static logic. This simplifies the design and possibly results in faster operation due to lower node capacitances. We demonstrate the feasibility of the proposed EHBTFET logic for low supply voltage operation using mixed device/circuit simulations including quantum corrections.

A Computational Study of Tunneling Field-Effect Transistors: Challenges and Design Optimizations

Complementary-metal-oxide-semiconductor (CMOS) transistors have been commonly employed in the electronics industry for the past decades thank to their excellent scalability, low cost, and high performance. The semiconductor industry follows the Moore’s law which predicts that the number of transistors in an integrated circuit (IC) approximately doubles every two years. High packing density enables more logic circuits to be fabricated on a given IC chip area which lowers the cost per function. However, exponential growth of the number of transistors per IC chip leads to a drastic increase in the power density. Basically, power consumption of an IC can be categorized into two components: active power (PActive ) and passive power (PPassive ). PActive is given by αfCVDD 2 , where α is the activity factor, f is the operating frequency, C is the load capacitance, and VDD is the power supply voltage. PPassive is the power dissipation of transistors that are at the OFF state. Its magnitude is proportional to the product of OFF state current (IOFF ) and VDD . With the shrinking of physical dimensions of CMOS devices into sub-10 nanometer regime, direct source to drain tunneling and gate leakage can significantly increase the IOFF , which in turn increases the static power. In other words, power consumption has imposed a serious issue for advanced technology nodes. Since both active and passive powers are strongly dependent on the VDD , one effective way to reduce the power consumption is to scale down the VDD . The threshold voltage (VTH ) of the conventional MOSFETs needs to be reduced so that the same ION can be sustained at reduced VDD . However, decreasing VTH without scaling the subthreshold swing (S) will result in a high IOFF . This causes high passive power consumption. In the conventional MOSFET, the high energy electrons following the Fermi-Dirac distribution contribute to the subthreshold current which sets the lower limit of the subthreshold swing. Thus, a steeper switching characteristic is required in order to retain the same ION and IOFF when VDD is reduced. In this context, tunneling field-effect transistors (TFET) based on band-to-band tunneling (BTBT) is a promising candidate to overcome the 60mV/dec swing limitation at room temperature faced in conventional MOSFETs. Although a steeper switching characteristic can be achieved in TFETs, the ION of TFETs is still too low to satisfy the drive current requirement for low power application projected by the International Technology Roadmap for Semiconductors (ITRS). The performance of TFET can be enhanced via a few innovations, such as the employment of direct band gap materials, heterostructures with staggered band alignments, and inventive device structure designs. Recent advancements in TFET shows that enhancement in TFET is attained when the BTBT direction is aligned to the gate induced electric field, so-called vertical TFET (VTFET). This is due to the greater efficiency of the gate to control the band bending. In this work, we investigate the performance of the vertical TFET based on group IV and III-V materials. The vertical TFET considered is the Electron-Hole Bilayer TFET. The device Hamiltonians for all channel materials are constructed based on the full-band sp3d5s*tight-binding (TB) model. The atomistic TB model offers a realistic calculation which captures the properties of nano-scale structures more accurately. The carrier transport of VTFET is calculated using a quantum simulator based on the formalism of non-equilibrium Green’s function (NEGF). Subsequently, the atomic charge obtained from NEGF is coupled with the Poisson solver to solve for the atomic potential self-consistently. The optimization of VTEFT is carried out in terms of ON-current and subthreshold swing. The materials considered consist of silicon, germanium, and indium antimonide, and hetero-structures from III-V semiconductors. The effects of the device geometries, such as the length of overlap (LOV ) and underlap (LUN ) regions, are studied in order to provide insights in enhancing the electrical performance of VTFETs. Our study shows that heterojunction consisting of GaSb (source) and InAs (drain) offers higher current than that of Si homojunction. The electrical performance of VTEFT is further benchmarked with that of the conventional lateral PIN structure. In conclusion, this work presents the challenges and key design considerations of VTEFT.

The Electron-Hole Bilayer TFET: Dimensionality Effects and Optimization

An extensive parameter analysis is performed on the electron–hole bilayer tunnel field-effect transistor (EHBTFET) using a 1-D effective mass Schrodinger–Poisson solver with corrections for band non-parabolicity considering thin InAs, In0.53Ga0.47As, Ge, Si0.5Ge0.5, and Si films. It is found that depending on the channel material and channel thickness, the EHBTFET can operate either as a 2-D–2-D or 3-D–3-D tunneling device. InAs offers the highest $I_{\mathrm{\scriptscriptstyle ON}}$ , whereas for the Si and Si0.5Ge0.5 EHBTFETs, significant current levels cannot be achieved within a reasonable voltage range. The general trends are explained through an analytical model that shows close agreement with the numerical results.

Black Phosphorus: New Opportunities in Electronic Device Applications

Black phosphorus (BP) is one of layered materials drawing significant attentions in solid-state and electrochemical societies. BP has a direct bandgap, which can be tuned by varying the thickness of material or the number of layers. Due to its large carrier mobility, BP is considered as a promising contender for the future electronic device applications. However, designing field-effect transistors (FETs) based on BP is not straightforward since the relevant device physics can be significantly different from that of conventional metal-oxide-semiconductor (MOS) FETs based on 3D materials such as silicon or III-V semiconductors. Therefore, careful engineering practices are required to use BP for transistor applications. In this study, we will mainly discuss design strategies for conventional FET structures and tunnel FETs (TFETs) based on the novel layered material of BP. We perform self-consistent atomistic quantum transport simulations using non-equilibrium Green’s function (NEGF) formalism with tight-binding approximation. For high-performance device applications, conventional FET structure based on BP is considered. Our simulation results reveal that, among few-layer BPs, monolayer BP can provide the best device performance with the largest on current (~5 mA/μm), the largest on-off current ratio (~107), and the smallest subthreshold swing (62 mV/dec), showing three times larger on current and three orders of magnitude smaller off current compared to 2022 International Technology Roadmap for Semiconductors (ITRS). Although bilayer BP FETs also exhibit as comparable device performance as monolayer BP FETs, in general, thicker BP is not preferable mainly due to the worse gate electrostatic control, which affects the overall device performance negatively. Secondly, for low-power devices, BP is integrated into the lateral tunnel FET structure, where small off current and steep subthreshold slope are of great importance rather than on state characteristics. Our simulation results show bilayer and trilayer BP are preferable for TFETs applications, unlike the conventional FET structure, while monolayer BP suffers from small on current due to its large bandgap. By carefully engineering various device parameters, an ultra-high on-off current ratio (> 1011) and an extremely small subthreshold swing (~15 mV/dec) can be achieved in bilayer and trilayer BP TFETs, demonstrating the great potential of few-layer BP over monolayer. This study shows that BP FETs can be tuned for various target applications by engineering the material and device parameters properly.

Band-to-band tunneling distance analysis in the heterogate electron–hole bilayer tunnel field-effect transistor

In this work, we analyze the behavior of the band-to-band tunneling distance between electron and hole subbands resulting from field-induced quantum confinement in the heterogate electron–hole bilayer tunnel field-effect transistor. We show that, analogously to the explicit formula for the tunneling distance that can be easily obtained in the semiclassical framework where the conduction and valence band edges are allowed states, an equivalent analytical expression can be derived in the presence of field-induced quantum confinement for describing the dependence of the tunneling distance on the body thickness and material properties of the channel. This explicit expression accounting for quantum confinement holds valid provided that the potential wells for electrons and holes at the top and bottom of the channel can be approximated by triangular profiles. Analytical predictions are compared to simulation results showing very accurate agreement.

Quantum Mechanical Confinement in the Fin Electron-Hole Bilayer Tunnel Field-Effect Transistor

Quantum mechanical confinement in electron–hole bilayer tunnel field-effect transistors (EHBTFETs) affects in a substantial way the band-to-band tunneling (BTBT) mechanism that constitutes their operating principle. Field-induced quantization is known to set off effective bandgap widening phenomena—with the subsequent BTBT probability reduction that it entails—and to give rise to harmful parasitic tunneling processes. Both of these effects degrade the potential steep switching behavior of bilayer TFETs. In this paper, we show that the novel FinEHBTFET proves to be a promising structure for its scalability potential and propose a solution to alleviate the impact on it of quantum confinement, as well as to suppress the parasitic tunneling processes that show up when quantization is considered. Moreover, we demonstrate for different fin materials that the utilization of asymmetric configurations delaying the formation of electron inversion layers allows us to boost $I_{\mathrm{\scriptscriptstyle ON}}$ levels.

Design and Analysis of CMOS-Compatible III-V Compound Electron-Hole Bilayer Tunneling Field-Effect Transistor for Ultra-Low-Power Applications.

In this work, we design and analyze complementary metal-oxide-semiconductor (CMOS)-compatible III-V compound electron-hole bilayer (EHB) tunneling field-effect transistors (TFETs) by using two-dimensional (2D) technology computer-aided design (TCAD) simulations. A recently proposed EHB TFET exploits a bias-induced band-to-band tunneling (BTBT) across the electron-hole bilayer by an electric field from the top and bottom gates. This is in contrast to conventional planar p(+)-p(-)-n TFETs, which utilize BTBT across the source-to-channel junction. We applied III-V compound semiconductor materials to the EHB TFETs in order to enhance the current drivability and switching performance. Devices based on various compound semiconductor materials have been designed and analyzed in terms of their primary DC characteristics. In addition, the operational principles were validated by close examination of the electron concentrations and energy-band diagrams under various operation conditions. The simulation results of the optimally designed In0.533Ga0.47As EHB TFET show outstanding performance, with an on-state current (Ion) of 249.5 μA/μm, subthreshold swing (S) of 11.4 mV/dec, and threshold voltage (Vth) of 50 mV at VDS = 0.5 V. Based on the DC-optimized InGaAs EHB TFET, the CMOS inverter circuit was simulated in views of static and dynamic behaviors of the p-channel device with exchanges between top and bottom gates or between source and drain electrodes maintaining the device structure.

Assessment of pseudo-bilayer structures in the heterogate germanium electron-hole bilayer tunnel field-effect transistor

We investigate the effect of pseudo-bilayer configurations at low operating voltages (≤0.5 V) in the heterogate germanium electron-hole bilayer tunnel field-effect transistor (HG-EHBTFET) compared to the traditional bilayer structures of EHBTFETs arising from semiclassical simulations where the inversion layers for electrons and holes featured very symmetric profiles with similar concentration levels at the ON-state. Pseudo-bilayer layouts are attained by inducing a certain asymmetry between the top and the bottom gates so that even though the hole inversion layer is formed at the bottom of the channel, the top gate voltage remains below the required value to trigger the formation of the inversion layer for electrons. Resulting benefits from this setup are improved electrostatic control on the channel, enhanced gate-to-gate efficiency, and higher ION levels. Furthermore, pseudo-bilayer configurations alleviate the difficulties derived from confining very high opposite carrier concentrations in very thin structures.

Germanium electron–hole bilayer tunnel field-effect transistors with a symmetrically arranged double gate

A germanium tunnel field-effect transistor (TFET) with a bias-induced electron–hole bilayer (EHB) with double gates that are symmetrically arranged and independently biased is simulated. The symmetric double gate scheme is feasible, presenting a simple EHB-TFET structure that is practicable for industrial fabrication. According to simulation results, the improvement of on/off current ratio of ∼108 is achieved by inserting a lightly-doped drain-source (LDD) region. Also, fin-type EHB-TFETs show an extremely low average sub-threshold swing of 11 mV/decade over 4 decades at VDD = 0.5 V, and thus are suitable for ultra-low power applications.

Response to “Comment on ‘Assessment of field-induced quantum confinement in heterogate germanium electron–hole bilayer tunnel field-effect transistor’” [Appl. Phys. Lett. 106, 026102 (2015)

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A Novel Fin Electron–Hole Bilayer Tunnel Field-Effect Transistor

A novel fin electron-hole bilayer tunnel field-effect transistor (FinEHBTFET) is proposed and investigated by simulation. In this structure, a narrow fin is placed at the middle of a conventional p <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> -i-n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> tunnel field-effect transistor, and two separate gates formed on left and right sides of the fin are used to control the channel. The FinEHBTFET achieves drive current when band-to-band tunneling happens between the bias-induced electron-hole bilayer at the two sides of the fin. The FinEHBTFET shows a high I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> ratio more than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sup> , and an average SS of 3 mV/dec over three decades of drain current.

Assessment of field-induced quantum confinement in heterogate germanium electron–hole bilayer tunnel field-effect transistor

The analysis of quantum mechanical confinement in recent germanium electron–hole bilayer tunnel field-effect transistors has been shown to substantially affect the band-to-band tunneling (BTBT) mechanism between electron and hole inversion layers that constitutes the operating principle of these devices. The vertical electric field that appears across the intrinsic semiconductor to give rise to the bilayer configuration makes the formerly continuous conduction and valence bands become a discrete set of energy subbands, therefore increasing the effective bandgap close to the gates and reducing the BTBT probabilities. In this letter, we present a simulation approach that shows how the inclusion of quantum confinement and the subsequent modification of the band profile results in the appearance of lateral tunneling to the underlap regions that greatly degrades the subthreshold swing of these devices. To overcome this drawback imposed by confinement, we propose an heterogate configuration that proves to suppress this parasitic tunneling and enhances the device performance.

Quantum Mechanical Study of the Germanium Electron–Hole Bilayer Tunnel FET

The electron-hole bilayer tunnel field-effect transistor (EHBTFET) is an electronic switch that uses 2-D-2-D sub-band-to-sub-band tunneling (BTBT) between electron and hole inversion layers and shows significant subthermal swing over several decades of current due to the step-like 2-D density of states behavior. In this paper, EHBTFET has been simulated using a quantum mechanical model. The model results are compared against transactions on computer-aided design simulations and remarkable differences show the importance of quantum effects and dimensionality in this device. Ge EHBTFET with channel thickness of 10 nm results as a promising device for low supply voltage, subthreshold logic applications, with a super steep switching behavior featuring SSavg ~ 40 mV/dec up to VDD. Furthermore, it has been demonstrated that high on current levels ( ~ 40 μA/μm) can be achieved due to the transition from phonon-assisted BTBT to direct BTBT at higher biases.

The electron–hole bilayer tunnel FET

We propose a novel tunnel field-effect transistor (TFET) concept called the electron–hole bilayer TFET (EHBTFET). This device exploits the carrier tunneling through a bias-induced electron–hole bilayer in order to achieve improved switching and higher drive currents when compared to a lateral p–i–n junction TFET. The device principle and performances are studied by 2D numerical simulations. Output and transfer characteristics, as well as the impact of back gate bias, silicon thickness and gate length on the device behavior are evaluated. Device performances are compared for Si and Ge implementations. Nearly ideal average subthreshold slope (SSAVG∼10mV/dec over 7 decades of current) and ION/IOFF>108 at VD=VG=0.5V are obtained, due to the OFF–ON binary transition which leads to the abrupt onset of the band-to-band tunneling inside the semiconductor channel. Remarkably, for Ge EHBTFETs the ION (∼11μA/μm at VDD=0.5V) is 10× larger than in Ge tunnel FETs and 380× larger than in Si EHBTFETs.

Complementary Germanium Electron–Hole Bilayer Tunnel FET for Sub-0.5-V Operation

In this letter, we present a novel device, the germanium electron-hole (EH) bilayer tunnel field-effect transistor, which exploits carrier tunneling through a bias-induced EH bilayer. The proposed architecture provides a quasi-ideal alignment between the tunneling path and the electric field controlled by the gate. The device principle and performances are studied by 2-D numerical simulations. This device allows interesting features in terms of low operating voltage (<; 0.5 V), due to its super-steep subthreshold slope (SSAVG ~ 13 mV/dec over six decades of current), ION/IOFF ratio of ~ 109, and drive current of ION ~ 10 μA/μm at VDD = 0.5 V. The same structure with symmetric voltages can be used to achieve a p-type device with ION and IOFF levels comparable to the n-type, which enables a straightforward implementation of complementary logic that could theoretically reach a maximum operating frequency of 1.39 GHz when VDD = 0.25 V.