Bilayer Thin Film Transistors Research Articles

Verifying the physical role of upper-active-layer on charge transport together with bias stability in bilayer-channel oxide thin-film transistors

In this work, we report the fabrication of solution-processed bilayer-structure oxide thin-film transistors (TFTs) exhibiting superior electrical characteristics and enhanced positive/negative bias stabilities. This was achieved by tuning the carrier concentration and bandgap of the top active layer in the bilayer semiconductor. The characteristics of the top layer were modulated through aluminum (Al) doping in indium oxide semiconductors. Bilayer-channel TFTs with an optimized indium-aluminum-oxide top layer (In:Al ratio of 8:2) demonstrated effective electron transport via percolation conduction and exhibited high mobility. Furthermore, the optimized bilayer TFTs displayed small threshold voltage shifts under positive and negative bias stress, attributed to the effective formation of a quasi-two-dimensional electron gas and the suppression of oxygen vacancies. An in-depth study on engineering the carrier concentration and bandgap of the bilayer structure provides insights into material design and fabrication strategies for high-performance and stable heterostructure transistors.

Enhancement in electrical properties of dual-active-layer amorphous SiZnSnO/SiInZnO thin film transistors

Bi-layer thin film transistors (TFTs) have been fabricated with a channel structure comprising a dielectric layer, a semiconducting amorphous-Si-In-Zn-O (a-SIZO) layer, and a semiconducting amorphous-Si-Zn-Sn-O (a-SZTO) layer, aiming to improve field effect mobility and stability. These films were deposited using RF sputtering at room temperature. The TFTs with a bottom gate top contact, processed at 500 °C, exhibited high mobilities (>32 cm2 V−1 s−1) along with a current on/off ratio of approximately 108 and a subthreshold swing (SS) value below 0.5 V decade−1 primarily because of reduced trap density and presence of highly conducting ultrathin a-SIZO layer. Furthermore, the bi-layer TFTs demonstrated notable stability under negative and positive bias temperature stress conditions.

Solution-processed bilayer InGaZnO/In2O3 thin film transistors at low temperature by lightwave annealing

At low temperatures about 230 °C, bilayer InGaZnO/In2O3 thin film transistors (TFTs) were prepared by a solution process with lightwave annealing. The InGaZnO/In2O3 bilayer TFTs with SiO2 as dielectric layer show high electrical performances, such as a mobility of 7.63 cm2V−1s−1, a threshold voltage (V th) of 3.8 V, and an on/off ratio higher than 107, which are superior to single-layer InGaZnO TFTs or In2O3 TFTs. Moreover, bilayer InGaZnO/In2O3 TFTs demonstrated a great bias stability enhancement due to the introduction of top InGaZnO film act as a passivation layer, which could prevent the interaction of ambient air with the bottom In2O3 layer. By using high dielectric constant AlO x film, the InGaZnO/In2O3 TFTs exhibit an improved mobility of 47.7 cm2V−1s−1. The excellent electrical performance of the solution-based InGaZnO/In2O3 TFTs shows great application potential for low-cost flexible printed electronics.

Impact of heavy ions on a-Si:H/PolySi bilayer thin film transistors with Schottky barrier source and drain based on Nickel Silicide

This study investigates the influence of heavy ion irradiation on thin film transistors (TFTs) based on an a-Si:H/PolySi active layer and Schottky barrier-based source and drain. Through the use of Technology Computer-Aided Design (TCAD) simulations, we analyze the impact on device performance. We examine the ambipolar device characteristics by varying the thickness of the active layer (Poly-Si) and studying the corresponding physics. Our results reveal that reducing the active layer thickness from 140 to 80 nm decreases the magnitude of the threshold voltage (|VT|) for both nMOS and pMOS operating voltages. Additionally, the subthreshold slope is reduced for both nMOS and pMOS as the active layer thickness is decreased from 140 to 80 nm.Further, we investigated the transient response of the drain current to heavy ion irradiation in the sensitive regions across the Schottky barrier-based source and drain. We specifically analyze the phenomenon of bipolar amplification for various Linear Energy Transfer (LET) values, ranging from 0.1 MeV cm2/mg to 100 MeV cm2/mg. Our findings indicate that increasing the LET values from 0.1 MeV cm2/mg to 100 MeV cm2/mg results in amplified bipolar behavior and a drain current overshoot of over 10 % for both pMOS and nMOS operating voltages. To summarize, this work highlights the effects of heavy ion irradiation on TFTs with an a-Si:H/PolySi active layer and Schottky barrier-based source and drain. The study explores the influence of active layer thickness on device characteristics and demonstrates the transient response of drain current under different LET values. These findings contribute to a better understanding of the behavior and performance of TFTs subjected to heavy ion irradiation.

The improved properties of solution-based InGaSnO (IGTO) thin film transistor using the modification of InZnO (IZO) layer

For improving the properties of indium-gallium-tin oxide (IGTO) thin film transistors (TFTs) based on solution method, indium-zinc oxide (IZO) thin film was used as a modification layer. When IZO did not perform post-annealing, the performance improvement of bilayer TFTs was not significant. When IZO performed post-annealing, the performance improvement of the bilayer TFTs was obvious. We also compared the effects of annealing time on the performance of IGTO TFTs. The modifying effects of IZO and the suitable annealing time led to a great improvement in the performance of TFTs. The mobility was increased by about 10 times than monolayer IGTO (0.27 cm2V−1s−1→4.38 cm2V−1s−1), and the threshold voltage and subthreshold swing were also very small (0.60 V, 0.55). We attribute the performance improvement of dual active layer TFTs to two reasons. On the one hand, the modifying effects of IZO made the IGTO defect state less and the film denser. On the other hand, the bilayer TFTs form a heterojunction structure similar to 2-dimensional electron gas (2DEG), which enhanced the mobility of the TFTs. This paper provides a research basis for the process of preparing dual active layers by solution method, and provides a new idea for the performance improvement of IGTO.

37.1: Invited Paper: A Room‐Temperature Manufacturing Strategy: Nd:AIZO/Al2O3 Thin‐Film Transistor

Metal oxide semiconductors (MOS) have shown great application potential as the active layer of thin film transistors (TFTs). However, MOTFTs usually require an annealing process(≥300°C), which is not conducive to its application in flexible substrates. Here, we establish a Room‐Temperature manufacturing strategy of TFT, which consist of a Nd:AIZO/Al2O3 bilayer structure as the active layer. The Nd:AIZO/Al2O3 bilayer TFTs without further thermal annealing processing show reasonable device characteristics with mobility(µsat) of 28.7 cm2 V‐1 s‐1, an Ion/Ioff ratio of 108, a threshold voltage(Vth) of 0.2 V, and a subthreshold swing(SS) of 0.25 V/decade. The room‐ temperature preparation of Nd:AIZO/Al2O3 bilayer TFT is compatible with low‐cost flexible substrates, which is anticipated in the application of large‐size flexible electronic devices, especially of the "green" flexible display area.

Enhanced Electrical Performance and Bias‐Stress Stability of Solution‐Processed Bilayer Metal Oxide Thin‐Film Transistors

Herein, solution‐processed indium gallium zinc oxide (IGZO) thin‐film transistors (TFTs) with a bilayer structure are investigated by embedding an ultrathin layer of indium zinc oxide (IZO) between the gate dielectric and IGZO film. The optimized IGZO/IZO bilayer TFTs exhibit a high field‐effect mobility (μFE) of 8.3 cm2 V−1 s−1, and the bias‐stress stability of the bilayer TFTs is greatly improved compared with that of the single‐layer IGZO devices. In addition, temperature‐dependent mobility and VT are investigated to reveal the trap distribution in the bilayer IGZO/IZO and single‐layer IGZO TFTs. Moreover, low‐voltage bilayer TFTs with a high mobility of 10.4 cm2 V−1 s−1 are demonstrated.

Transmission Line Method Analysis on the Electrical Properties of Bi-Layer Channel Oxide Thin Film Transistors with Oxide-Metal-Oxide Electrodes

Amorphous oxide thin film transistors (TFTs) is designed with bi-layer channel structure of SiInZnO/SiZnSnO (SIZO/SZTO). Bi-layer TFTs has excellent characteristics, such as high mobility, excellent on/off ratio, and low sub-threshold swing compared with the single layer TFTs. In the bi-layer structure, electrical properties were improved by the bottom layer of SIZO film with high carrier concentration and the SZTO film of the top layer could improve stability. Source and drain (S/D) electrodes adopt oxide-metal-oxide (OMO) of SiInZnO/Ag/SiInZnO (SIZO/Ag/SIZO) structure to manufacture high performance TFTs. The sheet resistance ( $$R_{sh}$$ ) and contact resistance ( $$R_{c}$$ ) of single layer TFTs and bi-layer TFTs were obtained using transmission line method (TLM), and the bi-layer TFTs exhibited low $$R_{sh}$$ and $$R_{c}$$ resistances with OMO electrodes. The low $$R_{sh}$$ was found to be advantageous to lowering the $$R_{c}$$ at the S/D electrodes when the OMO structure was applied to a TFTs as revealed in the outstanding device performances. OMO electrodes provide potential possibility to improve oxide TFT with excellent characteristics.

ZnO bilayer thin film transistors using H2O and O3 as oxidants by atomic layer deposition

This work demonstrates a novel design of thin film transistors composed of a bilayer structure of ZnO thin films (O3 as oxidant/H2O as oxidant) prepared by atomic layer deposition. Based on this structure, a large ION/IOFF ratio of 108 at VDS = 0.1 V, a high field-effect mobility of 31.1 ± 0.26 cm2 V−1 s−1, a low threshold voltage of 0.14 ± 0.07 V and a proper subthreshold swing of 0.21 ± 0.02 V/decade as well as an excellent positive bias stress stability have been obtained. The improved performance of the bilayer structured devices is attributed to the first channel layer of ZnO (H2O as oxidant) decreasing the interfacial trap density and providing high mobility, and the second channel layer of ZnO (O3 as oxidant) suppressing the off-state current as well as a newly formed sub-channel at the interface between the two channel layers.

Defect Self‐Compensation for High‐Mobility Bilayer InGaZnO/In2O3 Thin‐Film Transistor

AbstractHere, the bilayer InGaZnO/In2O3 thin‐film transistors (TFTs) are deposited by radio‐frequency magnetron sputtering at room temperature. A high field‐effect mobility (μFE) of 64.4 cm2 V−1 s−1 and a small subthreshold swing (SS) of 204 mV per decade are achieved in the bilayer‐stack TFTs fabricated upon SiO2/Si substrate, with large improvement compared to the single‐layer InGaZnO and In2O3 TFTs. Implementing HfO2 and Si3N4 as high‐k gate dielectrics, μFE and SS are correspondingly enhanced to be 67.5 and 79.1 cm2 V−1 s−1, and 85 and 92 mV per decade in the bilayer TFTs. Defect self‐compensation effect is also revealed, i.e., (In)+ + (O)− → In − O, while, respectively, considering the indium‐ and oxygen‐related defects in InGaZnO and In2O3 and exploring the numerical simulations in SILVACO/Atlas (for electrical performance) and Quantum Espresso (for physical analysis). The InO formation can result in a significant reduction in defect density (validated by the X‐ray photoelectron spectra and low‐frequency noise characterizations) and therefore improvement of μFE and SS in the bilayer‐stack TFT. The important role of defect self‐compensation mechanism while combining different individual channel layers in the oxide semiconducting TFTs is underlined and highly potential application in next‐generation, fast‐speed flexible displays is shown.

ZnO Bilayer Thin Film Transistors Using H 2O and O 3 as Oxidants by Atomic Layer Deposition

This work demonstrates a novel design of thin film transistors composed of a bilayer structure of ZnO thin films (O3 as oxidant/H2O as oxidant) prepared by atomic layer deposition. Based on this structure, a large ION/IOFF ratio of 108 at VDS = 0.1 V, a high filed-effect mobility of 30.8 cm2 V-1s-1, a low threshold voltage of 0.05 V and a proper subthreshold swing of 0.24 V/decade as well as an excellent positive bias stress stability have been obtained. The improved performance of the bilayer structured devices is attributed to the first channel layer of ZnO (H2O as oxidant) decreasing the interfacial trap density and providing high mobility, and the second channel layer of ZnO (O3 as oxidant) suppressing the off-state current as well as a newly formed sub-channel at the interface between the the two channel layers.

All-sputtered, flexible, bottom-gate IGZO/Al2O3 bi-layer thin film transistors on PEN fabricated by a fully room temperature process

In this work, an innovative all-sputtered bottom-gate thin film transistor (TFT) using an amorphous InGaZnO (IGZO)/Al2O3 bi-layer channel was fabricated by fully room temperature processes on a flexible PEN substrate.

Silicon induced stability and mobility of indium zinc oxide based bilayer thin film transistors

Indium zinc oxide (IZO), silicon containing IZO, and IZO/IZO:Si bilayer thin films have been prepared by dual radio frequency magnetron sputtering on glass and SiO2/Si substrates for studying their chemical compositions and electrical characteristics in order to ascertain reliability for thin film transistor (TFT) applications. An attempt is therefore made here to fabricate single IZO and IZO/IZO:Si bilayer TFTs to study the effect of film thickness, silicon incorporation, and bilayer active channel on device performance and negative bias illumination stress (NBIS) stability. TFTs with increasing single active IZO layer thickness exhibit decrease in carrier mobility but steady improvement in NBIS; the best values being μFE ∼ 27.0, 22.0 cm2/Vs and ΔVth ∼ −13.00, −6.75 V for a channel thickness of 7 and 27 nm, respectively. While silicon incorporation is shown to reduce the mobility somewhat, it raises the stability markedly (ΔVth ∼ −1.20 V). Further, IZO (7 nm)/IZO:Si (27 nm) bilayer based TFTs display useful characteristics (field effect mobility, μFE = 15.3 cm2/Vs and NBIS value, ΔVth =−0.75 V) for their application in transparent electronics.

Effects of top-layer thickness on electrical performance and stability in VZTO/ZTO bi-layer thin-film transistors

We examined vanadium-incorporated zinc tin oxide (VZTO) thin film transistors (TFTs) with various V contents and found that VZTO films easily become semi-insulators, even at small V contents (≥1.7 at%). We also fabricated VZTO/ZTO bi-layer TFTs with various VZTO top-layer thicknesses and investigated their electrical performance and stability. Regardless of the VZTO top-layer thickness, the VZTO/ZTO TFTs exhibited the transfer characteristics of a typical TFT because VZTO top-layers had semiconducting properties, unlike single VZTO films. As compared to the reference ZTO TFT, the stability of all the bi-layer TFTs under bias and/or illumination stress was significantly improved.

InZnO/AlSnZnInO Bilayer Oxide Thin-Film Transistors with High Mobility and High Uniformity

In this letter, high-performance InZnO/AlSnZnInO (IZO/ATZIO) bilayer thin-film transistors (TFTs) with an inverted staggered back channel etch structure are presented. The channel width and the length were both $6~\mu \text{m}$ , which is small enough to be adapted to a high-resolution display backplane. High field-effect mobility ( $\mu _{\textrm {FE}})$ over 60 cm2/Vs was obtained from the structure with 8-nm IZO channel insertion between the gate dielectric and the ATZIO layer. The device shows good controllability in light of TFT operation. The subthreshold slope, turn-ON voltage ( $V_{\mathrm{\scriptscriptstyle ON}})$ , and ON/OFF ratio were 0.16 V/decade, −1.52 V, and $5\times 10^{9}$ , respectively.

Modification of intrinsic defects in IZO/IGZO thin films for reliable bilayer thin film transistors

Dual active channel IZO/IGZO thin film transistors as such and with ZnO interlayer are fabricated and characterized to investigate the impact of ultra-thin ZnO insertion on their performance and bias stability.

A study of electrical enhancement of polycrystalline MgZnO/ZnO bi-layer thin film transistors dependence on the thickness of ZnO layer

A polycrystalline MgZnO/ZnO bi-layer was deposited by using a RF co-magnetron sputtering method and the MgZnO/ZnO bi-layer TFTs were fabricated on the thermally oxidized silicon substrate. The performances with varying the thickness of ZnO layer were investigated. In this result, the MgZnO/ZnO bi-layer TFTs which the content of Mg is about 2.5 at % have shown the enhancement characteristics of high mobility (6.77–7.56 cm2 V−1 s−1) and low sub-threshold swing (0.57–0.69 V decade−1) compare of the ZnO single layer TFT (μFE = 5.38 cm2 V−1 s−1; S.S. = 0.86 V decade−1). Moreover, in the results of the positive bias stress, the ΔVon shift (4.8 V) of MgZnO/ZnO bi-layer is the 2 V lower than ZnO single layer TFT (ΔVon = 6.1 V). It reveals that the stability of the MgZnO/ZnO bi-layer TFT enhanced compared to that of the ZnO single layer TFT.

Dual electrical behavior of multivalent metal cation-based oxide and its application to thin-film transistors with high mobility and excellent photobias stability.

The effect of multivalent metal cations, including vanadium(V) and tin (Sn), on the electrical properties of vanadium-doped zinc tin oxide (VZTO) was investigated in the context of the fabrication of thin-film transistors (TFTs) using a single VZTO film and VZTO/ZTO bilayer as channel layers. The single VZTO TFT did not show any response to the gate voltage (insulator-like behavior). On the other hand, the VZTO/ZTO bilayer TFT exhibited a typical TFT transfer characteristic (semiconducting behavior). X-ray photoelectron spectroscopy revealed that, in contrast to what is commonly true in many oxides, oxygen vacancies (V(O)) in VZTO did not provide a dominant contribution to the total carrier concentration, because the V(O) peak area in the single VZTO film was 5.4% and reduced to 4.5% in VZTO/ZTO bilayer. Instead, Sn 3d5/2 and V 2p3/2 spectra suggest that the significant reduction in Sn and V ions is strongly related to the insulator-like behavior of the VZTO film. In negative-bias illumination tests and illumination tests with various photon energies, the VZTO/ZTO bilayer TFT had much better stability than the ZTO TFT. This result is attributed to the reduction of donor-like states ([Formula: see text]O) that can be positively ionized by blue and green illumination.

Controlling the Performance of P-type Cu2O/SnO Bilayer Thin-Film Transistors by Adjusting the Thickness of the Copper Oxide Layer

The effect of copper oxide layer thickness on the performance of Cu2O/SnO bilayer thin-film transistors was investigated. By using sputtered Cu2O films produced at an oxygen partial pressure, Opp, of 10% as the upper layer and 3% Opp SnO films as the lower layer we built a matrix of bottom-gate Cu2O/SnO bilayer thin-film transistors of different thickness. We found that the thickness of the Cu2O layer is of major importance in oxidation of the SnO layer underneath. The thicker the Cu2O layer, the more the underlying SnO layer is oxidized, and, hence, the more transistor mobility is enhanced at a specific temperature. Both device performance and the annealing temperature required could be adjusted by controlling the thickness of each layer of Cu2O/SnO bilayer thin-film transistors.

P-Type Cu2O/SnO Bilayer Thin Film Transistors Processed at Low Temperatures

P-type Cu2O/SnO bilayer thin film transistors (TFTs) with tunable performance were fabricated using room temperature sputtered copper and tin oxides. Using Cu2O film as capping layer on top of a SnO film to control its stoichiometry, we have optimized the performance of the resulting bilayer transistor. A transistor with 10 nm/15 nm Cu2O to SnO thickness ratio (25 nm total thickness) showed the best performance using a maximum process temperature of 170 °C. The bilayer transistor exhibited p-type behavior with field-effect mobility, on-to-off current ratio, and threshold voltage of 0.66 cm(2) V(-1) s(-1), 1.5×10(2), and -5.2 V, respectively. The advantages of the bilayer structure relative to single layer transistor are discussed.