Bi-directional ESD Research Articles

A GaN Lateral Bidirectional ESD Clamp Based on the Floating-Gate MBS and a Regulating Capacitor

A GaN Lateral Bidirectional ESD Clamp Based on the Floating-Gate MBS and a Regulating Capacitor

Design of Bi-Directional ESD Protection Circuit With Uni-Directional ESD Device in BCD Technology

Design of Bi-Directional ESD Protection Circuit With Uni-Directional ESD Device in BCD Technology

A Novel Bidirectional AlGaN/GaN ESD Protection Diode.

Despite the superior working properties, GaN-based HEMTs and systems are still confronted with the threat of a transient ESD event, especially for the vulnerable gate structure of the p-GaN or MOS HEMTs. Therefore, there is still an urgent need for a bidirectional ESD protection diode to improve the ESD robustness of a GaN power system. In this study, an AlGaN/GaN ESD protection diode with bidirectional clamp capability was proposed and investigated. Through the combination of two floating gate electrodes and two pF-grade capacitors connected in parallel between anode or cathode electrodes and the adjacent floating gate electrodes (CGA (CGC)), the proposed diode could be triggered by a required voltage and possesses a high secondary breakdown current (IS) in both forward and reverse transient ESD events. Based on the experimental verification, it was found that the bidirectional triggering voltages (Vtrig) and IS of the proposed diode were strongly related to CGA (CGC). With CGA (CGC) increasing from 5 pF to 25 pF, Vtrig and IS decreased from ~18 V to ~7 V and from ~7 A to ~3 A, respectively. The diode’s high performance demonstrated a good reference for the ESD design of a GaN power system.

Bidirectional ESD Protection Device Using PNP With pMOS-Controlled Nwell Bias

We demonstrate a PNP-based bidirectional ESD protection device with base bias controlled by two pMOS transistors, realized in a 0.18- $\mu \text{m}$ CMOS process for 5–7 V applications. With respect to the conventional floating-base PNP device, very similar ESD performance is achieved. Due to the presence of extra parasitic diodes, the dc breakdown ( ${V}_{\text {BD}}$ ) and holding ( ${V}_{H}$ ) voltages are extended up to 8.0 and 7.6 V at 150 °C, respectively. Only a very limited area increase is needed and no extra mask is required for this implementation.

Improved inductive-system-level IEC ESD performance for automotive applications using mutual ballasted ESD protection technique

A new ESD failure mode under inductive IEC stress of automotive Controller Area Network (CAN) bus is identified. Inductor saturation causes increase of the rise-time from 1ns to ~20ns, leading to non-uniform conduction in the bidirectional ESD protection circuit. A novel mutual ballasting layout technique is introduced to recover the system level ESD performance.

Design of 60-GHz Low-Noise Amplifiers With Low NF and Robust ESD Protection in 65-nm CMOS

This paper presents two 60-GHz low-noise amplifiers (LNAs) with different electrostatic (ESD) protection schemes, including the diode-based and LC-based configurations. By codesigning ESD network and input matching, both LNAs are optimized for minimum noise figure (NF) while maintaining a similar gain. Compared with the conventional double-diode approach, the proposed LC-based design uses a high current capability spiral inductor and a high breakdown voltage metal-oxide-metal capacitor as effective bidirectional ESD protection, showing much improved ESD protection level and NF under reduced power consumption. The test results demonstrate an over 8-kV human-body-model ESD level and an over 13-A very fast transmission line pulse current level for charge-device-model ESD protection. The measured NF and power gain are 5.3 dB and 17.5 dB, respectively, at 58 GHz, under a power consumption of only 18 mW. To the best of our knowledge, the LC-based ESD-protected LNA demonstrates a highest ESD protection level with a lowest NF, compared with prior arts operating at similar frequencies.

Understanding the Mechanisms of Degradation and Failure Observed in ESD Protection Devices Under System-Level Tests

The behavior and the failure mechanism of a monolithic bidirectional ESD protection device under a system-level ESD pulse are investigated. The device is realized by two diffused vertical back-to-back connected diodes. When the bottom p-n junction is stressed with an 18-kV system-level pulse, the device exhibited the typical signature of second thermal breakdown. Surprisingly, no ESD damage could initially be observed by measuring the poststress leakage current, even when the ESD level was further increased to 30 kV. A degrading <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IV</i> behavior was later found to be associated with the second thermal breakdown. Based on simulations, local crystal defects are proposed to explain the observed degradation of the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IV</i> behavior. It is shown that, in this case, leakage-current measurements alone fail to detect such ESD damage. Failure analysis of the device confirms the existence of the crystal damage.

A 5-GHz fully integrated ESD-protected low-noise amplifier in 90-nm RF CMOS

A fully integrated 5-GHz low-power ESD-protected low-noise amplifier (LNA), designed and fabricated in a 90-nm RF CMOS technology, is presented. This 9.7-mW LNA features a 13.3-dB power gain at 5.5 GHz with a noise figure of 2.9 dB, while maintaining an input return loss of -14 dB. An on-chip inductor, added as "plug-and-play," i.e., without altering the original LNA design, is used as ESD protection for the RF pins to achieve sufficient ESD protection. The LNA has an ESD protection level up to 1.4 A transmission line pulse (TLP) current, corresponding to 2-kV Human Body Model (HBM) stress. Experimental results show that only minor RF performance degradation is observed by adding the inductor as a bi-directional ESD protection device to the reference LNA.