BiCMOS Process Technology Research Articles

A 2.125-Gb/s BiCMOS fiber channel transmitter for serial data communications

A 2.125-Gb/s transmitter meeting the specifications of the emerging ANSI Fiber Channel standard has been developed using BiCMOS technology. This transmitter features (1) a fully bipolar 10:1 multiplexer (MUX) and a 2.125-GHz retimer for high-accuracy transmission of data, (2) an emitter-coupled logic (ECL) CMOS analog phase-locked loop, (3) pure ECL-level output for direct connection to the currently available optical modules, and (4) BiCMOS process technology that includes 0.25-/spl mu/m CMOS devices and 20-GHz bipolar devices. The LSI serializes 32-bit-wide, 53.125-Mb/s data into 2.125-Gb/s data through a CMOS 8B10B encoder. The chip area is 3/spl times/2 mm/sup 2/, and the power dissipation is 860 mW.

A BiCMOS wired-OR logic

This paper proposes a BiCMOS wired-OR logic for high-speed multiple input logic gates. The logic utilizes the bipolar wired-OR to circumvent the use of a series connection of MOS transistors. The BiCMOS wired-OR logic was found to be the fastest compared with such conventional gates as CMOS NOR, BiCMOS multiemitter logic and CMOS wired-NOR logic, when the number of inputs was more than four and the supply voltage was 3.3 V. The BiCMOS wired-OR logic was also determined to be the fastest of the four when the fan-out number was below 20 and the number of inputs was eight. In addition, the speed was more than twice as faster when the fan-out number was less than 10. The BiCMOS wired-OR logic was applied to a 64-b 2-stage carry look-ahead adder, and was fabricated with a 0.5-/spl mu/m BiCMOS process technology. A critical path delay time of 3.1 ns from an input to a sum output was obtained at the supply voltage of 3.3 V. This is 35% faster than that of conventional BiCMOS adders. >

A 622-Mb/s 8*8 ATM switch chip set with shared multibuffer architecture

An asynchronous transfer mode (ATM) switch chip set, which employs a shared multibuffer architecture, and its control method are described. This switch architecture features multiple-buffer memories located between two crosspoint switches. By controlling the input-side crosspoint switch so as to equalize the number of stored ATM cells in each buffer memory, these buffer memories can be treated as a single large shared buffer memory. Thus, buffers are used efficiently and the cell loss ratio is reduced to a minimum. Furthermore, no multiplexing or demultiplexing is required to store and restore the ATM cells by virtue of parallel access to the buffer memories via the crosspoint switches. Access time for the buffer memory is thus greatly reduced. This feature enables high-speed switch operation. A three-VLSI chip set using 0.8- mu m BiCMOS process technology has been developed. Four aligner LSIs, nine bit-sliced buffer-switch LSIs, and one control LSI are combined to create a 622-Mb/s 8*8 ATM switching system that operates at 78 MHz. In the switch fabric, 155-Mb/s ATM cells can also be switched on the 622-Mb/s port using time-division multiplexing. >

A fast pull‐in PLL IC using two‐mode pull‐in technique

AbstractThe phase‐locked loop (PLL) circuit used in the timing recovery of high‐speed digital communications and high‐density digital recordings must have a fast pull‐in time and low jitter. One way to satisfy both characteristics is to use a two‐mode PLL in which the loop gain is switched in the pull‐in state and the steady state. However, in the PLL with a conventional procedure, the time constant of the loop filter cannot be reduced in the pull‐in state; hence the time for phase locking after frequency locking cannot be reduced.This paper proposes a method in which the time constant of the loop filter and the loop gain are both switched. The loop gain is switched by the gain of the smoothing filter to eliminate ripple in the output from the phase comparator while the time constant is switched by the resistor in the loop filter. This method realizes a pull‐in time one‐tenth that in the PLL with conventional two‐mode operation.A PLL IC using the forementioned method was fabricated by 2‐μm BiCMOS process technology. Its capture range was ±2 percent, the pull‐in time was 100 μs, and the noise bandwidth was 128 kHz in 64‐MHz operation.

A 6-ns ECL 100 K I/O and 8-ns 3.3-V TTL I/O 4-Mb BiCMOS SRAM

The authors report a 4 M word*1 b/1 M word*4 b BiCMOS SRAM that can be metal mask programmed as either a 6-ns access time for an ECL 100 K I/O interface to an 8-ns access time for a 3.3-V TTL I/O interface. Die size is 18.87 mm*8.77 mm. Memory cell size is 5.8 mu m*3.2 mu m. In order to achieve such high-speed address access times the following technologies were developed: (1) a BiCMOS level converter that directly connects the ECL signal level to the CMOS level; (2) a high-speed BiCMOS circuit with low threshold voltage nMOSFETs; (3) a design method for determining the optimum number of decoder gate stages and the optimum size of gate transistors; (4) high-speed bipolar sensing circuits used at 3.3-V supply voltage; and (5) 0.55- mu m BiCMOS process technology with a triple-well structure.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

BiCMOS bus interface logic for advanced system applications

Abstract A brief account of the state and development trends of TTL-level bus circuits is given and a way to overcome existing design obstacles by using BiCMOS process technology is discussed. When reviewing advanced bus concepts and looking at the semiconductor devices required to support them, one still finds a strong emphasis on improving the speed/power performance of existing functions. This appears to be a long-term trend over more than two decades. Unfortunately, product features progress towards ranges where certain technology-inherent physical phenomena start to become major design problems. These are excessive power consumption (with accordingly high heat generation) with bipolar circuits, and induced noise voltages during output switching with fast CMOS logic, just to mention some of the severe effects. Texas Instruments has introduced a BiCMOS family of bus functions that is based on a combined bipolar/CMOS process technology. It is explained how the unique product features given here enable highly sophisticated bus systems to be developed without any increased design effort requirements or further application restrictions. In addition, an outlook on the future development of this technology is given.

An 8-ns 1-Mbit ECL BiCMOS SRAM with double-latch ECL-to-CMOS-level converters

The design and performance of a high-speed 1 M*1-bit SRAM with ECL I/O are described. The 6.5*16.5-mm/sup 2/ chip was fabricated with a 0.8- mu m BiCMOS process technology. A modified double-word-line (MDWL) structure and a bit-line peripheral circuitry with normally-on bit-line equalization circuit are used to achieve high-speed read operation. The read speed is further enhanced by a novel ECL-to-CMOS-level converter with a double-latch configuration. The converter dissipates no DC current and contributes to low power consumption together with an automatic power-saving function, utilizing the address transition detection (ATD) technique. The access time is typically 8 ns, and the active power is 500 mW at 50 MHz. >