Bias-temperature Stress Conditions Research Articles

Enhancement in electrical properties of dual-active-layer amorphous SiZnSnO/SiInZnO thin film transistors

Bi-layer thin film transistors (TFTs) have been fabricated with a channel structure comprising a dielectric layer, a semiconducting amorphous-Si-In-Zn-O (a-SIZO) layer, and a semiconducting amorphous-Si-Zn-Sn-O (a-SZTO) layer, aiming to improve field effect mobility and stability. These films were deposited using RF sputtering at room temperature. The TFTs with a bottom gate top contact, processed at 500 °C, exhibited high mobilities (>32 cm2 V−1 s−1) along with a current on/off ratio of approximately 108 and a subthreshold swing (SS) value below 0.5 V decade−1 primarily because of reduced trap density and presence of highly conducting ultrathin a-SIZO layer. Furthermore, the bi-layer TFTs demonstrated notable stability under negative and positive bias temperature stress conditions.

Electrical Characterization of Charge Polarity in AlF₃ Anti-Reflection Layers for Complementary Metal Oxide Semiconductor Image Sensors.

In this study, the charge polarity of aluminum fluoride (AlF3) as a function of varying thickness (tAlF3 = 20, 35, 50, 65, and 80 nm) was discussed. AlF3 films were deposited onto p-Si wafers via electron beam sputtering. Thickness dependent charge polarity and reliability issues under bias-temperature stress conditions were identified using a capacitance-voltage (C-V) characterization method. AlF3 was found to possess negative fixed charges, leading to a C-V curve shift toward the positive gate bias direction as tAlF3 was increased up to 50 nm. On the contrary, the C-V characteristics were dominantly affected by the positive charges of mobile ions and/or fluorine vacancies when tAlF3 was increased to more than 50 nm. Additionally, negative bias temperature stress (1 MV/cm, 473 K for 10 mins) increased insulator trapped charges and decreased interface traps in 20 nm thick AlF3 films. These results could be attributed to positively charged fluorine vacancies introduced by broken Al-F bonds within AlF3 films and the passivation of Si dangling bonds due to broken fluorine ions at the interface, respectively. It was believed that 20 nm thick AlF3 films sufficiently attracted holes from the Si substrate, forming a hole accumulation layer on the surface due to total charge polarity of the AlF3 dielectric being entirely governed by negative fixed charges as the thickness of AlF3 decreased. Based on these results, AlF3 films are proposed for use as an anti-reflection layer to replace HfO2 in CMOS image sensors.

DC sputtered amorphous In–Sn–Zn–O thin-film transistors: Electrical properties and stability

In this study, we investigated the electrical properties of DC sputtered amorphous In–Sn–Zn–O (a-ITZO) thin-film transistors (TFTs) fabricated under various process conditions. Fabricated a-ITZO TFTs achieved a threshold voltage (VT) of 1.0V, subthreshold swing (SS) of 0.38V/dec and field-effect mobility (μeff) of around 30cm2/Vs. An analytical field-effect mobility model is proposed for a-ITZO TFTs with key parameters extracted using different methods. The impacts of a-ITZO channel thickness and oxygen gas flow ratio on device performance were evaluated. Finally, the a-ITZO TFT bias-temperature stress (BTS) induced electrical instability was studied. In comparison to amorphous In–Ga–Zn–O (a-IGZO) TFTs, improved electrical stability was observed for a-ITZO TFTs using exactly the same BTS conditions.

Analysis of recoverable and permanent components of threshold voltage shift in NBT stressed p-channel power VDMOSFET**Project supported by the Fund from the Ministry of Education, Science and Technological Development of the Republic of Serbia (Grant Nos. OI-171026 and TR-32026) and the Ei PCB Factory, Niš.

In this study we investigate the dynamic recovery effects in IRF9520 commercial p-channel power vertical double diffused metal–oxide semiconductor field-effect transistors (VDMOSFETs) subjected to negative bias temperature (NBT) stressing under the particular pulsed bias. Particular values of the pulsed stress voltage frequency and duty cycle are chosen in order to analyze the recoverable and permanent components of stress-induced threshold voltage shift in detail. The results are discussed in terms of the mechanisms responsible for buildup of oxide charge and interface traps. The partial recovery during the low level of pulsed gate voltage is ascribed to the removal of recoverable component of degradation, i.e., to passivation/neutralization of shallow oxide traps that are not transformed into the deeper traps (permanent component). Considering the value of characteristic time constant associated with complete removal of the recoverable component of degradation, it is shown that by selecting an appropriate combination of the frequency and duty cycle, the threshold voltage shifts induced under the pulsed negative bias temperature stress conditions can be significantly reduced, which may be utilized for improving the device lifetime in real application circuits.

Effects of vacuum-ultraviolet irradiation on copper penetration into low-k dielectrics under bias-temperature stress

The effects of vacuum-ultraviolet (VUV) irradiation on copper penetration into non-porous low-k dielectrics under bias-temperature stress (BTS) were investigated. By employing x-ray photoelectron spectroscopy depth-profile measurements on both as-deposited and VUV-irradiated SiCOH/Cu stacks, it was found that under the same BTS conditions, the diffusion depth of Cu into the VUV-irradiated SiCOH is higher than that of as-deposited SiCOH. On the other hand, under the same temperature-annealing stress (TS) without electric bias, the Cu distribution profiles in the VUV-irradiated SiCOH were same with that for the as-deposited SiCOH. The experiments suggest that in as-deposited SiCOH, the diffused Cu exists primarily in the atomic state, while in VUV-irradiated SiCOH, the diffused Cu is oxidized by the hydroxyl ions (OH−) generated from VUV irradiation and exists in the ionic state. The mechanisms for metal diffusion and ion injection in VUV irradiated low-k dielectrics are discussed.

Positive gate-bias temperature instability of ZnO thin-film transistor

The positive gate-bias temperature instability of a radio frequency (RF) sputtered ZnO thin-film transistor (ZnO TFT) is investigated. Under positive gate-bias stress, the saturation drain current and OFF-state current decrease, and the threshold voltage shifts toward the positive direction. The stress amplitude and stress temperature are considered as important factors in threshold-voltage instability, and the time dependences of threshold voltage shift under various bias temperature stress conditions could be described by a stretched-exponential equation. Based on the analysis of hysteresis behaviors in current—voltage and capacitance—voltage characteristics before and after the gate-bias stress, it can be clarified that the threshold-voltage shift is predominantly attributed to the trapping of negative charge carriers in the defect states located at the gate—dielectric/channel interface.

Performance and Reliability Characterization of 1200 V Silicon Carbide Power MOSFETs at High Temperatures

Commercially available, 1200 V SiC power MOSFETs have been characterized under bias-temperature stress conditions. Two generations of devices from a single manufacturer were tested. For the first-generation MOSFETs, both plastic- and metal-packaged devices were evaluated, whereas for the second-generation MOSFETs, only plastic-packaged devices were tested. Threshold voltage was observed to decrease with increasing temperature in the absence of gate bias stress, as expected. Drain leakage current increased with increasing temperature above the rated temperature of 125°C for first-generation plastic-packaged parts, with the leakage ~10× higher for the plastic-packaged parts compared to the metal-packaged parts. A negative gate voltage was shown to reduce drain leakage current for the metal-packaged parts only, suggesting a parasitic leakage path associated with the plastic packaging. The threshold voltage shift ΔVT was minimal for T < 125°C. ΔVT increased with increasing temperature above 125°C, and was larger for negative gate voltage bias stress, suggesting that the oxide is more sensitive to trapping of holes than trapping of electrons. ΔVT was insensitive to the type of package. The second-generation SiC MOSFET showed significantly less susceptibility to bias temperature stress, especially for negative gate voltage, indicating improvement in device design and/or processing in the second-generation MOSFET. Switching gate stress showed complex behavior, with a rapid initial shift in VT followed by a much slower shift. Initial testing indicates a strong dependence on duty cycle and possible influence of self-heating. More detailed study of reliability under switching conditions is needed.

Modeling of TDDB in advanced Cu interconnect systems under BTS conditions

Due to the shrinking of the device size in integrated circuits together with the use of novel, less stable low-k back-end-of-line dielectrics more attention has to be paid to the time dependent dielectric breakdown (TDDB) effect. In this work the TDDB mechanisms are investigated and modeled based on constant-voltage bias-temperature stress (BTS) experiments from the 90nm and 45nm technology nodes. The modeling of the I-t dependencies is based on the numerical model of Haase in which it is assumed that the degradation of the dielectric is caused just by the electronic leakage current itself. By two simple modifications of the model and an adjustment of several model parameters it was possible to achieve a very good agreement between the model and the experiment for single constant-voltage BTS dependencies. For two different experimental data sets from the 45nm technology node the TDDB behavior in dependence on the bias voltage and temperature is analyzed and compared with the results of the modified Haase model and the Poole-Frenkel lifetime model.

Bias-stress-induced stretched-exponential time dependence of threshold voltage shift in InGaZnO thin film transistors

The experimental and modeling study of bias-stress-induced threshold voltage instabilities in amorphous indium-gallium-zinc oxide thin film transistors is reported. Positive stress results in a positive shift in the threshold voltage, while the transfer curve hardly moves when negative stress is induced. The time evolution of threshold voltage is described by the stretched-exponential equation, and the shift is attributed to the electron injection from the channel into interface/dielectric traps. The stress amplitudes and stress temperatures are considered as important factors in threshold voltage instabilities, and the stretched-exponential equation is well fitted in various bias temperature stress conditions.

Investigation of Cu ion drift through CVD TiSiN into SiO2 under bias temperature stress conditions

Cu gate metal oxide semiconductor (MOS) capacitors with and without thin chemical vapor deposition (CVD) TiSiN diffusion barrier were subjected to bias temperature stress (BTS) conditions. Cu drift flux for the MOS capacitor with CVD TiSiN diffusion barrier was about one order of magnitude smaller than that without the diffusion barrier. The activation energy of the drift flux was larger by a factor of 1.5 than that without the diffusion barrier. Cu thermal diffusion in the CVD TiSiN is dominant for Cu ion drift into the plasma enhanced (PE)-CVD SiO2. The Cu concentration depth profile in SiO2 showed that the Cu dose in PECVD SiO2 under thermal stress is significantly smaller than that under BTS conditions.

Investigation of the electrical properties and reliability of amorphous SiCN

Amorphous SiCN (a-SiCN) is a candidate for barrier dielectric and has lower dielectric constant ( k∼5) relative to the commonly used barrier SiN ( k∼7). In this study, we investigate the leaky behavior and barrier characteristics of a-SiCN ( k: 4∼5) doped with different nitrogen concentration. The leaky behavior of a-SiCN is Poole–Frenkel at high electric field. This is similar to SiN. Thermal stability of a-SiCN films is good enough to meet the prescription in back-end-of-line fabrication process. The bias-temperature stress (BTS) test has been conducted on a-SiCN to investigate the barrier ability against copper penetration. We find that a-SiCN could sustain the stress of electric field up to 4 mV/cm at 150 °C. In addition, a-SiCN films with higher nitrogen concentration exhibit better barrier property against copper penetration. The SIMS spectra also have been used to monitor the distributions of copper after different BTS conditions, confirming our inference on leakage mechanism.

Electrical Instability of Hydrogenated Amorphous Silicon Thin-Film Transistors for Active-Matrix Liquid-Crystal Displays

We investigated the threshold voltage shifts (ΔVT) of inverted-staggered hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs) induced by steady-state (dc) and pulsed (ac) gate bias-temperature-stress (BTS) conditions. Our study showed that, for an equivalent effective-stress-time, ΔVT has an apparent pulse-width dependence under negative BTS conditions–the narrower the pulse width, the smaller the ΔVT. This gate-bias pulse-width dependence is explained by an effective-carrier-concentration model, which relates ΔVT for negative pulsed gate-bias stress to the concentration of mobile carriers accumulated in the conduction channel along the a-Si:H/gate insulator interface. In addition, our investigation of the methodology of a-Si:H TFT electrical reliability evaluation indicates that, instead of steady-state BTS, pulsed BTS should be used to build the database needed to extrapolate ΔVT induced by a long-term display operation. Using these experimental results, we have shown that a-Si:H TFTs have a satisfactory electrical reliability for a long-term active-matrix liquid-crystal display (AMLCD) operation.