Model For Bias Temperature Instability Research Articles

Physics-informed machine learning model for bias temperature instability

A new machine learning model is presented to predict the dynamic behavior of threshold voltage shifts induced by bias temperature instability (BTI) in CMOS devices. The model is constructed by combining physical theories with machine learning such as an artificial neural network and a Gaussian mixture model (GMM). To enlarge the capture–emission energy (CEE) window and to perform independent estimations of two distinct components of CEE distribution, the GMM with soft clustering is utilized, enabling full lifetime modeling of BTI. By training the CEE map with the consideration of the occupancy probability of traps and then executing the integration along the CEE, the threshold voltage shifts are obtained. This approach forms data-driven modeling that naturally encodes underlying physical theories as prior information. The resulting model exhibits a good performance for predicting the dynamic characteristics of BTI under various stress-recovery conditions.

On the Physical Meaning of Single-Value Activation Energies for BTI in Si and SiC MOSFET Devices

Bias temperature instability (BTI) has been shown to be the collective response of an ensemble of defects to a gate voltage signal. Each defect can be described using first-order reactions for either charge trapping or defect creation with a broad distribution of time constants. Consequently, the temperature dependence of BTI has to be determined by a distribution of activation energies reflecting the variety of available defects. Commonly employed single-value apparent activation energy-based modeling of BTI can therefore be at best a very rough approximation and its apparent activation energy is consequently a model parameter without physical justification. This study investigates the impact of measurement parameters, such as the extraction point in the drift curve and the recovery time, on these apparent activation energies that can be extracted either by threshold voltage shift increase (vertical method) or by stress time acceleration (horizontal method). The framework of activation energy maps enables an analytical mathematical approach to calculate the dependence of extracted apparent activation energies on the measurement parameters. A comparison between Si and SiC MOSFET devices is employed, and nonphysical negative apparent activation energies are explained. Since apparent activation energies have been repeatedly employed to justify physics-based descriptions of BTI, their physical (in)significance is discussed.

Design and Development of BTI Model and 3D InGaAs HEMT-Based SRAM for Reliable and Secure Internet of Things Application

It is broadly accepted that the silicon-based CMOS has touched its scaling limits and alternative substrate materials are needed for future technology nodes. An Indium-Gallium-Arsenide ( I n G a A s )-based device is well situated for further technology nodes. This material also has better mobility of the electrons and holes for the high performance and real-time system design. The improved mobility helps to increase the operating frequency of the device which is useful for Internet of Things (IoT) applications. However, I n G a A s -based High Electron Mobility Transistors (HEMT) limits the reliability of the device due to the presence of dangling bonds at the channel–gate insulator interfaces. Weak dangling-bonds get broken under electric stress, and positive hydrogen atoms are trapped into the oxide. This charge trapping depends on the material parameters and device geometry. In this paper, the existing Bias-Temperature-Instability (BTI) model is modified based on the material parameters and device geometry. Charge trapping and annealing constants are the most critical BTI model parameters that are modeled and evaluated based on different HEMT material parameters. The proposed model was compared to experimental and TCAD simulation results. The proposed model has been used for lifetime prediction of the InGaAs HEMT-based Static Random-Access Memory (SRAM) cell because it is used to store and process the information in the IoT applications.

Modeling and Evaluating the Gate Length Dependence of BTI

Bias temperature instability (BTI) is a major reliability concern in the current and upcoming technologies. Current mitigation techniques mainly target circuit and system levels through reducing the stimuli that govern BTI. Such mitigation techniques typically come with non-negligible overheads, which might not be acceptable—especially in smaller technology nodes where the available design margins are tighter. Semiconductor vendors report different BTI degradations in their technology and hence circuit designers need to consider such technology features when designing for reliability. Recently, TSMC reported that BTI strongly depends on the gate length ( ${L}$ ) of transistors in their 10nm technology node. In this brief, we are the first to investigate the role that gate length dependence of BTI may play as a new degree of freedom in the design for reliability. Based on the reported data from TSMC, we propose to incorporate the gate length dependency into a state-of-the-art physics-based BTI model. Then, we propose a new method of transistor stacking that optimizes circuits (e.g., SRAM cells) with respect to on/off current ratios in which ${L}$ -dependency of BTI is taken into account. Compared to state of the art, our approach results in BTI-hardened SRAM cells with 50% better on/off current ratio along with $3\times$ better reliability at the cost of a 20% area overhead.

Modeling the Interdependences Between Voltage Fluctuation and BTI Aging

With technology scaling, the susceptibility of circuits to different reliability degradations is steadily increasing. Aging in transistors due to bias temperature instability (BTI) and voltage fluctuation in the power delivery network of circuits due to IR-drops are the most prominent. In this paper, we are reporting for the first time that there are interdependences between voltage fluctuation and BTI aging that are nonnegligible. Modeling and investigating the joint impact of voltage fluctuation and BTI aging on the delay of circuits, while remaining compatible with the existing standard design flow, is indispensable in order to answer the vital question, “what is an efficient (i.e., small, yet sufficient) timing guardband to sustain the reliability of circuit for the projected lifetime?” This is, concisely, the key goal of this paper. Achieving that would not be possible without employing a physics-based BTI model that precisely describes the underlying generation and recovery mechanisms of defects under arbitrary stress waveforms. For this purpose, our model is validated against varied semiconductor measurements covering a wide range of voltage, temperature, frequency, and duty cycle conditions. To bring reliability awareness to existing EDA tool flows, we create standard cell libraries that contain the delay information of cells under the joint impact of aging and IR-drop. Our libraries can be directly deployed within the standard design flow because they are compatible with existing commercial tools (e.g., Synopsys and Cadence). Hence, designers can leverage the mature algorithms of these tools to accurately estimate the required timing guardbands for any circuit despite its complexity. Our investigation demonstrates that considering aging and IR-drop effects independently , as done in the state of the art, leads to employing insufficient and thus unreliable guardbands because of the nonnegligible (on average 15% and up to 25%) underestimations. Importantly, considering interdependences between aging and IR-drop does not only allow correct guardband estimations, but it also results in employing more efficient guardbands.

On the Impact of the Gate Work-Function Metal on the Charge Trapping Component of NBTI and PBTI

We investigate bias temperature instability (BTI) charge trapping trends in high-k metal gate (HKMG) stacks with a variety of work function metals (WFMs). Most BTI models suggest charge trapping in oxide defects is modulated by the applied oxide electric field, which controls the energy barrier for the capture process, irrespective of the gate work function. However, experimental data on capacitors show enhanced or reduced charge trapping at a constant oxide electric field for different WFM stacks. We ascribe this to a different chemical interaction of the metals with the dielectric, which yields different defect profiles depending on the process thermal budget, and not to the gate work function per se. This observation is confirmed by comparing BTI degradation in nMOS and pMOS replacement gate planar transistors with three selected WFM stacks (representative of high-, standard-, and low-Vth device flavors), and two different process thermal budgets. Furthermore, by employing the imec/T.U. Wien physics-based BTI simulation framework “Comphy,” we also show that, on top of the unavoidable chemical interaction of different metals with the underlying SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> dielectric stack, different gate work functions within a typical range of relevance (4.35-4.75 eV) can yield a different charge state of the deep high-k defects, and can therefore have an impact on charge trapping kinetics during BTI stress, particularly in nMOSFETs.

On the Prediction of the Threshold Voltage Degradation in CMOS Technology Due to Bias-Temperature Instability

Currently, researchers face new challenges in order to compensate or even reduce the noxious phenomenon known as bias-temperature instability (BTI) that is present in modern metal-oxide-semiconductor (MOS) technologies, which negatively impacts the performance of semiconductor devices. BTI remains a mystery in the way that it evolves in time, as well as the responsible mechanisms for its appearance and the further degradation it produces on MOS devices. The BTI phenomenon is usually associated with an increase of MOS transistor’s threshold voltage; however, this work also addresses BTI as a change in MOSFET’s drain current, transconductance, and the channel’s resistivity. In this way, we detail a physics-based model to get a better insight into the prediction of threshold voltage degradation for aging ranges going from days to years, in 180-nm MOS technology. We highlight that a physics-based BTI model improves accuracy in comparison to lookup table models. Finally, simulation results for the inclusion of such a physics-based BTI model into BSIM3v3 are shown in order to get a better understanding of how BTI impacts the performance of MOS devices.

Voltage-Dependent Activation Energy Maps for Analytic Lifetime Modeling of NBTI Without Time Extrapolation

To enable MOSFETs lifetime extrapolation of up to 10 years, bias temperature instability (BTI) is commonly accelerated via increased stress voltage and increased temperature. We demonstrate that BTI can be described by a unique activation energy map including the voltage and temperature dependence of stress and recovery and use capture and emission time maps to model the time dynamics responsible for the threshold voltage shift of BTI. Based on this approach, we present a new measurement technique, further called temperature-accelerated measure-stress-measurements (TA-MSM) enabling lifetime modeling of BTI without any time extrapolation. We show the application of this technique to simulate standard qualification measurements, fast wafer-level reliability measurements as well as the degradation after ac and dc burn-in stress. In addition, we show that the TA-MSM technique is a valuable tool for the study of the permanent component and the recently discovered reverse recovery effect.

Bias temperature instability model using dynamic defect potential for predicting CMOS aging

This paper describes a new approach for modeling bias-temperature instability (BTI) in nanoscale transistors. The model uses non-iterative surface potential solvers enhanced with dynamic defect potential equations to enable accurate, physics-based circuit level simulations that incorporate BTI effects. Defect maps constructed from experimental data reported on high-k-metal-gate bulk complementary metal-oxide-semiconductor devices are used to parameterize the defect potential equation. By implementing the enhanced surface potential model in Verilog-A, both DC and AC BTI aging effects in combinational circuits are simulated and the results compared conventional threshold voltage shift methods for BTI modeling.

Reliability in Super- and Near-Threshold Computing: A Unified Model of RTN, BTI, and PV

Near-threshold computing (NTC) poses stringent constraints on designing reliable circuits, as degradations have a magnified impact at lower supply voltages ( $V_{\text {dd}}$ ) compared with super-threshold supply voltages. While phenomena, such as bias temperature instability (BTI) scale down with $V_{\text {dd}}$ , mitigate their magnified impact with reduced degradations and, thus, have little impact on NTC reliability. Process variation (PV) and random telegraph noise (RTN) do not scale with $V_{\text {dd}}$ and, therefore, become key reliability challenges in NTC. On the other hand, in super-threshold computing (STC), PV and BTI are the dominant phenomena, as BTI induces considerable degradations at nominal $V_{\text {dd}}$ and PV imposes large enough shifts to matter at any supply voltage. Therefore, to allow $V_{\text {dd}}$ -scaling from super-to near-threshold, we need to consider all of BTI, RTN, and PV. Ergo, we present a unified RTN and BTI model that models their shared physical origin and is validated against experimental data across a wide voltage range. Our unified model and PV model capture the joint impact of RTN, BTI, and PV within a probabilistic reliability estimation for NTC and STC circuits. We employed our proposed model to analyze the reliability of SRAM cells showing how taking error correction codes into account is able to mitigate the deleterious effects of BTI, RTN, and PV by 36% compared with unprotected circuits.

Modeling and simulation of the charge trapping component of BTI and RTS

Charge trapping phenomena is known to be a major reliability concern in modern MOSFETS, playing a significant role in aging through Bias Temperature Instability (BTI) and dominating low-frequency noise behavior. An electrical level modeling and simulation approach, valid at DC, AC and transient operation conditions is presented. Detailed statistical analysis is provided, aiming at proper modeling of BTI and noise variability, as well as to facilitate the understanding of physical mechanisms behind BTI and noise that are difficult to obtain otherwise. Case studies relevant for practical applications and understanding of the basic mechanisms are presented and critically discussed.

Online Measurement of Degradation Due to Bias Temperature Instability in SRAMs

A method is proposed to detect failing cells due to bias temperature instability (BTI) in Static Random Access Memories (SRAMs) en route to failure. If potentially failing cells are detected prior to failure, SRAMs can be operated without failures, since the detection of potentially failing cells can trigger reconfiguration, given available memory redundancy. Using an experimentally verified BTI model, we study the performances of conventional 6T SRAM cells as a function of BTI degradation, in the presence of process variations. An on-chip monitoring scheme is presented that can be embedded within conventional SRAM designs without affecting normal device operation and with minimal overhead.

System-level variation-aware aging simulator using a unified novel gate-delay model for bias temperature instability, hot carrier injection, and gate oxide breakdown

A framework is proposed to analyze system-level reliability and evaluate the lifetimes of state-of-art microprocessors considering the impact of process–voltage–temperature (PVT) variations and device wearout mechanisms, including bias temperature instability (BTI), hot carrier injection (HCI), and gate oxide breakdown (GOBD). This work studies not only the system performance degradation due to each wearout mechanism individually, but also the performance degradation while all these wearout mechanisms happen simultaneously. A unified gate-delay model is developed to combine PVT variations and the aging effect, and then a statistical timing engine is constructed to analyze performance degradations and system lifetimes.

Use of SSTA Tools for Evaluating BTI Impact on Combinational Circuits

This paper presents an extensive statistical study on the impact of bias temperature instability (BTI) on digital circuits. A statistical framework for the evaluation of BTI at the electrical (SPICE) level, enhanced by an atomistic model for BTI, is introduced. This framework is then employed to perform the timing analysis of different combinational paths using cells from a given library, aiming to statistically model BTI at the higher abstraction level. A statistical static timing analysis (SSTA) method is then performed and the results are compared to detailed simulations using atomistic models based on experimental data. The comparison between the two methods shows that for large paths both methods converge to the same distribution for the delay while for short paths the delay distributions are different causing the SSTA method to generate misleading results. An analysis is then performed in order to understand and formalize the results.

Impact of duty factor, stress stimuli, gate and drive strength on gate delay degradation with an atomistic trap-based BTI model

In deeply scaled CMOS technologies, Bias Temperature Instability (BTI) is one of the most critical degradation mechanisms impacting the device reliability. This study presents the BTI evaluation of gates covering both the PMOS and NMOS degradation in a workload dependent, atomistic trap-based, stochastic BTI model. The gate propagation delay depends on the gate intrinsic delay, the input signal characteristics, and the output load. In this paper, the impact of (1) duty factor, (2) periodic clock-based and non-periodic random input sequences, (3) gate, and (4) drive strength to the BTI degradation are investigated. Statistical studies show a mean degradation of 3% and a worst-case of 27%. Moreover, the near-critical paths with lower drive strength cells are 3.7× more susceptible to BTI degradation than the critical paths with higher drive strength cells. Next, the relative degradations of the propagation delays for the well-known gates (i.e. INV, NAND, NOR, AOI) are presented. Under the same stress stimuli, degradations of the gate propagation delays differ by 4.5×.

The Impact of BTI Variations on Timing in Digital Logic Circuits

A new framework for analyzing the impact of bias temperature instability (BTI) variations on timing in large-scale digital logic circuits is proposed in this paper. This approach incorporates both the reaction-diffusion model and the charge-trapping model for BTI and embeds these into a temporal statistical static timing analysis framework capturing process variations and path correlations. Experimental results on 32-, 22-, and 16-nm technology models, which were verified through Monte Carlo simulation, confirm that the proposed approach is fast, accurate, and scalable and indicate that BTI variations make a significant contribution to circuit-level timing variations.

(Invited) Random Telegraph Noise: From a Device Physicist's Dream to a Designer's Nightmare

An overview is given on Random Telegraph Noise (RTN) in MOS-based devices. First, the basic properties and physics are briefly outlined, emphasizing the stochastic nature of its main parameters: the capture and emission time constant, while its amplitude is fixed and specific for each trap. Different techniques exist to characterize RTN in MOS devices, either by time or frequency domain measurements. A distinction can also be made between dynamic equilibrium methods like noise spectroscopy or transient measurements, based on a Deep-Level Transient Spectroscopy approach. While single-device based RTN measurements are still of high value, for modern circuit applications, techniques are being developed allowing a fast assessment of RTN in a large number of transistors. The scaling of CMOS technologies to the 32 nm and below raises the issue of variability induced either by random dopant fluctuations or in general, by random charge fluctuations, both spatially and in time. As will be seen, the presence of traps responsible for RTN brings about an additional source of variability which may become dominant in future memories. Finally, it will be shown that RTN is not only a fundamental component of 1/f noise but the same oxide traps are also largely responsible for the Bias Temperature Instability (BTI) in scaled MOSFETs. This leads to a self-consistent model for BTI and a stochastic approach towards the reliability prediction of deep submicron CMOS technologies.

Compact Negative Bias Temperature Instability Model for Silicon Nanowire MOSFET (SNWT) and Application in Circuit Performance Simulation

Compact Negative Bias Temperature Instability Model for Silicon Nanowire MOSFET (SNWT) and Application in Circuit Performance Simulation

Bias temperature instability in metal-oxide-semiconductor field-effect transistors with atomic-layer-deposited Si-nitride/SiO2 stack gate dielectrics

Bias temperature instability (BTI) in p+ poly-Si gated metal-oxide-semiconductor field-effect transistors (MOSFETs) with atomic-layer-deposited (ALD) Si-nitride/SiO2 stack gate dielectrics was systematically studied using drain current-gate voltage (Id-Vg) and modified direct-current current-voltage (DCIV) measurements. They exhibited quite unique behaviors as compared to the conventional SiON counterpart: turnaround of the threshold voltage shift (ΔVth) during stressing and significant positive BTI in nMOSFETs. The observed phenomena were consistently explained within the framework of conventional reaction-diffusion model for BTI but with two additional assumptions: (1) there exist pre-existing traps in the ALD Si-nitride/SiO2 stack dielectrics and (2) it is the inversion carriers (electrons or holes) rather than the accumulation carriers which effectively dissociate the SiH bonds at the SiO2∕Si interface during BTI stressing. Owing to the absence of nitrogen near the SiO2∕Si interface and the compensation effect on ΔVth between the charge trapping in the pre-existing traps and the dissociation of the SiH bonds under small voltage stress, the ALD Si-nitride/SiO2 stack dielectrics at the operating voltage may have similar or even longer BTI lifetime than the pure SiO2.

Negative bias temperature instability modeling for high-voltage oxides at different stress temperatures

The temperature bias instability of high-voltage oxides is analyzed. For the investigation of negative bias temperature instability (NBTI) we present an enhanced reaction–diffusion model including trap-controlled transport, the amphoteric nature of the P b centers at the Si/SiO 2 interface, Fermi-level dependent interface charges, and fully self-consistent coupling to the semiconductor device equations. Comparison to measurement data for a stress/relaxation cycle and a wide range of temperatures shows excellent agreement.