Bias Supply Research Articles

High-Frequency Magnetic Pulse Generator for Low-Intensity Transcranial Magnetic Stimulation

This paper presents a high-frequency (HF) magnetic pulse generator designed for low-intensity transcranial magnetic stimulation (LI-TMS) applications. HF pulse stimulation can induce a strong electric field with minimal current and enhance the penetration depth of the electric field in human tissue. The HF magnetic pulse generator was designed and fabricated using a microcontroller unit, gate driver, full-bridge coil driver, and stimulation coil. Measurements with a full-bridge circuit supply voltage of 10 V demonstrated an electric field intensity of 6.8 Vpp/m at a frequency of 1 MHz with a power dissipation of 2.45 W. Achieving a similar electric field intensity at a frequency of 100 kHz required approximately ten times the coil current. Additionally, a quasi-resonant LC load was introduced by connecting a capacitor in series with the stimulation coil, which set the resonant frequency to approximately 10% higher than the frequency of 1 MHz. This approach reduced the coil impedance, achieving higher current with the same bias supply voltage. Experimental results showed an enhanced electric field intensity of 19.1 Vpp/m with a supply voltage of only 1.8 V and reduced power dissipation of 1.11 W. The proposed HF pulse train with quasi-resonant coil system is expected to enable a low-power LI-TMS system.

Second order frequency selective surface design multi-functional at two bands

This paper proposes an active frequency selective surface which furnishes three bands of higher order filtering characteristics. It controls multi-functional features, at two bands (centered at 2 GHz and 4 GHz), namely electromagnetic response and polarization of plane wave. Nine discrete filtering outputs are independently controlled through switching in bias supply to four PIN diodes embedded in two layers of AFSS unit cell. Two multifunctional bands hold stability upto 45° angles under all polarizations of wave. Passive band at around 5.9 GHz contributed by all the independent binary combinations exhibits stability upto 45° angles of TE wave only. The equivalent circuit method is used to explain and verify the designed structure. Finally, the AFSS structure is fabricated and reliability of the simulation results is verified through experiments.

Gate Driver Design in 180 nm SOI CMOS Process for Heterogeneous Integration Inside SiC Power Module

This paper presents the design and test results of a non-isolated single-channel gate driver for heterogeneous integration inside a SiC power module. The driver is designed on a 180 nm silicon-on-insulator (SOI) CMOS process that can safely operate up to 175 degrees C, most likely even beyond this figure, to survive at the expected junction temperature. The gate driver consists of four pull–up (PMOS) slices and four pull-down (NMOS) slices placed in parallel as the current sourcing and sinking components. Each slice can be activated individually through a controller block, making the gate driver’s drive strength variable. To mitigate the parasitic turn-on effect due to the Miller capacitor, an active Miller clamping circuit is integrated with the driver without overly compromising the device’s switching performance. Under-voltage lockout (UVLO) is another key feature of this driver that ensures the system is protected against bias supply failure. A desaturation detection scheme is also integrated with the gate driver as a system protection feature to detect excessive current flowing through the power devices. The gate driver die area is approximately 5.4 mm x 3.3 mm with a pad area of 100 μm x 100 μm suitable for wire bonding inside the module.

Low-cost and miniaturized temperature compensation system for nuclear applications

Facilities using nuclear radiation and detectors require stability of detector response irrespective of the ambient conditions. This stability of radiation detector output is crucial for applications requiring precise monitoring of radiation. The paper presents the development and performance validation of an analogue feedback circuit designed to compensate for the effect of temperature variations in Silicon Photomultiplier (SiPM) based detectors and measurement systems. The presented circuit uses feedback from a temperature sensor to enable a linear compensation to control the bias voltage for the charge pump-based bias supply. The circuit was tested using a scintillator coupled to a 2 × 2 array of SiPMs and tested using a Caesium-137 radioactive source for checking the stability of the detector output. The system was tested over a temperature range from 5 to 55 °C. Considering this broad range, this circuit was calibrated for different temperature ranges allowing the user to set the compensation depending on the temperature range of interest.

A 16-channel programmable SiPM bias supply system for Cherenkov telescope imaging camera

In recent years, the Silicon Photomultipliers (SiPMs) have emerged as a promising photodetector in various applications such as high energy physics, nuclear physics and medical instruments. One such application is in the pixelated camera of Imaging Atmospheric Cherenkov Telescopes (IACTs). IACTs are used to detect very high-energy celestial gamma rays using Atmospheric Cherenkov Technique. The SiPM gain is proportional to the overvoltage which is the difference between applied bias voltage and breakdown voltage. As the SiPM breakdown voltage increases with temperature, the overvoltage and hence the gain decreases proportionally (2-3%/°C) at a constant applied bias voltage. Also, the actual bias voltage across the SiPM changes with load current due to voltage drop across a series resistor in SiPM bias circuit, thus causing a change in overvoltage and gain. To maintain a constant gain of the SiPM, the applied bias voltage need to be adjusted to compensate for the changes in temperature and load. We are developing a 256-pixel imaging camera with SiPM as its photo-sensor. The camera will be placed at the focal point of telescope and will be operated during night in outdoor environment at Hanle, Ladakh, India. The night temperature at Hanle typically varies by ∼ 10°C overnight and ∼ 40°C (-20°C to +20°C) over the year. Thus, gain of SiPMs, exposed to the environment, may vary considerably during observations. A prototype 8-channel bias supply board with real time temperature & load compensation is developed to operate the camera SiPMs at fixed gain throughout the observation night.The voltage range of the bias supply for each channel is from 10 V to 80 V with 5 mV resolution and current upto 4 mA. The output voltage and current can be monitored with a resolution of ∼ 5 mV and ∼ 0.3 μA respectively. The single board computer, Raspberry Pi, is connected to the bias supply board over a 7-wire Customized Serial Peripheral Interface (CSPI) for control and monitoring. A multi-channel SiPM bias supply system is realized by daisy-chaining 8-channel boards through CSPI to cater bias voltage to all the pixels of the camera. The system is operated remotely using Ethernet interface of Raspberry-Pi. This paper discusses the design, development and performance of the prototype 16-channel closed-loop, programmable bias supply system with built-in compensation for changes in temperature and load.

Focus on software, data acquisition, and instrumentation

Focus on software, data acquisition, and instrumentation

The role of the cosmic web in the scatter of the galaxy stellar mass–gas metallicity relation

The large-scale structure of the Universe can be understood in terms of features such as filaments, nodes and walls, which we collectively term the cosmic web. Galaxies evolve within the cosmic web, naturally raising the question of its impact on that process. There are two main mechanisms by which the cosmic web can influence galaxies: one is by modulating the growth of haloes, and the other is by regulating the gas ecosystem around galaxies. Disentangling the two is difficult, but key to deriving a holistic picture of galaxy formation and observational constraints on the growth of haloes. Here we report a detection of the effect of the cosmic web on the galaxy stellar mass–gas-phase metallicity relation of low-redshift star-forming galaxies using data from the Sloan Digital Sky Survey. The proximity of a galaxy to a node, independently of stellar mass and overdensity, influences its gas-phase metallicity, with galaxies closer to nodes displaying higher chemical enrichment than those farther away. We find a similar, but notably weaker, effect with respect to filaments. We find qualitative agreement in the cosmological hydrodynamical simulation IllustrisTNG (TNG300). Using IllustrisTNG, our results can be explained by both halo assembly bias and gas supply combining in nodes in a way that markedly modulates the metallicity of the gas, contributing to the scatter of this fundamental relation in galaxy evolution.

A linear wide‐angle scanning phased array based on pattern reconfigurable elements

AbstractA wide‐angle scanning phased array based on pattern reconfigurable elements is proposed. There are seven metallic cylinders arranged on both sides of each unit separately to improve the isolation. The design of metallic cavities instead of a ground plate and cooperating with cylinders ingeniously solved the inconvenience of DC bias supply, significantly reducing the size of the antenna element and the entire system, and also the coupling between elements. The 3 dB beamwidth of the joint pattern generated by the pattern reconfigurable technology covers 217° in H‐plane at 5GHz. The phased array can scan from −75° to 75° in H‐plane, with gain fluctuation within 1 dB. The phased array processes a high‐aperture efficiency of 75.76%. The measured results of the phased array prototype agree with the simulation.

Influence of PECVD features of SiNx deposition processes on electrical parameters of SiNx/AlGaN/GaN structures

In this work, we studied the influence of the processes of plasma-chemical deposition of SiNx films on the electrical parameters of the dielectric/AlGaN/GaN structure. The effect of the composition of the formed films, the effect of additional surface treatment of heterostructures in nitrogen plasma prior to dielectric deposition, as well as the effect of the RF bias supply during this treatment on the C-V and I-V characteristics of the SiNx/AlGaN/GaN structures were analyzed. It was found that for films with a ratio of nitrogen and silicon concentrations of 60 % and 40 %, as well as with an increased oxygen content, a decrease in the value of a fixed positive charge in these structures is characteristic, but the appearance of current pulsations is observed on the I-V characteristics of the structures. It was revealed how the modes of the plasma chemistry process affect such parameters of oscillations as the period, amplitude, length of the section of the I-V characteristic, where oscillations are observed. A possible explanation of the reasons for the appearance of characteristic pulsations is proposed. It has been established that the additional action of nitrogen plasma on the surface of the heterostructure before the monosilane is introduced into the chamber leads to a change in the magnitude and sign of the fixed charge and to a decrease in the concentration of free carriers in the channel of a two-dimensional gas of SiNx/AlGaN/GaN heterostructures. It is shown experimentally how the technological features of the deposition and surface preparation processes can affect the electrical parameters of the formed heterostructures.

Experimental investigation on the degradation of SiGe LNAs under different bias conditions induced by 3 MeV proton irradiation

The 3 MeV proton irradiation effects on SiGe low noise amplifier (LNA) (NXP BGU7005) performance under different voltage supply VCC (0 V, 2.5 V) conditions were firstly experimental studied in this present work. The S parameters including S11, S22, S21, 1 dB compression point and noise figure (NF) of the test samples under different bias voltage supply were measured and compared before and after 3 MeV proton irradiation. The total proton irradiation fluence was 1 × 1015 protons/cm2. The maximum degradation quantities of the gain S21 and NF of the test samples under zero bias are measured respectively 1.6 dB and 1.2 dB. Compared with the samples under 2.5 V bias supply, the maximum degradation of S21 and NF are respectively 1.1 dB and 0.8 dB in the whole frequency band. It is noteworthy that the gain and NF of SiGe LNAs under zero-bias mode suffer enhanced degradation compared with those under normal bias supply. The key influence factors are discussed based on the correlation of the SiGe device and the LNA circuit. Different process of the ionization damage and displacement damage under zero-bias and 2.5 V bias voltage supply contributed to the degradation difference. The underlying physical mechanisms are analyzed and investigated.

Charge-coupling effect in a Hall field element based on thin-film SOI-MOS transistor

The influence of the coupling effect on the parameters of field Hall elements based on thin-film MOS transistors has been studied. Analysis of the development of today’s microelectronics shows the necessity of developing the element base for high performance sensors based on silicon technologies. One way to significantly improve the performance of sensing elements including magnetic field sensors is the use of thin-film transistors on the basis of silicon on insulator (SOI) structures. It has been shown that field Hall sensors (FHS) may become the basis of high-performance magnetic field sensors employing the coupling effect occurring in the double gate vertical topology of these sensing elements. Electrophysical studies of FHS have been conducted for different gate bias and power supply modes. The results show that the coupling effect between the gates occurs in FHS if the thickness of the working layer between the gates is 200 nm. This effect leads to an increase in the effective carrier mobility and hence an increase in the magnetic sensitivity of the material. Thus field Hall elements based on thin-film transistors fabricated using silicon technologies provide for a substantial increase in the magnetic sensitivity of the elements and allow their application in highly reliable magnetic field sensors.

Coupling effect in field Hall elements based on thin-film SOI MOS transistors

The influence of the coupling effect on the parameters of field Hall elements based on thin-film MOS transistors has been studied. Analysis of the development of today’s microelectronics shows the necessity of developing the element base for high performance sensors based on silicon technologies. One way to significantly improve the performance of sensing elements including magnetic field sensors is the use of thin-film transistors on the basis of silicon on insulator (SOI) structures. It has been shown that field Hall sensors (FHS) may become the basis of high-performance magnetic field sensors employing the coupling effect occurring in the double gate vertical topology of these sensing elements. Electrophysical studies of FHS have been conducted for different gate bias and power supply modes. The results show that the coupling effect between the gates occurs in FHS if the thickness of the working layer between the gates is 200 nm. This effect leads to an increase in the effective carrier mobility and hence an increase in the magnetic sensitivity of the material. Thus field Hall elements based on thin-film transistors fabricated using silicon technologies provide for a substantial increase in the magnetic sensitivity of the elements and allow their application in highly reliable magnetic field sensors.

A 2-Transistor Sub-1V Low Power Temperature Compensated CMOS Voltage Reference: Design and Application

This paper presents the design and application of a CMOS sub-1V voltage reference using a 2-transistor Self-Cascode MOSFET (SCM) structure able to get low power consumption, temperature compensation, and small area. An efficient design procedure applied to this simple topology relying on NMOS transistors with different threshold voltages allows attaining large immunity against bias current and supply voltage variations. The two transistors can operate in weak, moderate, or strong inversion making the design flexible in terms of area and power consumption. Implemented in a > 0.18mm standard CMOS technology, the circuit provides a 400mV voltage reference with a variation of ±0.18% from -20°C to 75°C (or less than 15ppm/°C), operates from 3.6V down to 800mV while biased with a 5nA resistor-less PTAT current source that varies ±30% over PVT, and consumes less than 20nA with an area of 0.01mm2. The same concept was used to create a temperature compensated voltage drop with regard to a monitored power supply voltage but using a 2-PMOS SCM structure with transistors of different threshold voltages. These two circuits were adopted as part of a Power Management (PM) system for RFID tag applications. The PM includes a LDO voltage regulator and a low voltage detector that require both the voltage reference and the low voltage monitor. The LDO regulated output voltage and the trip-point of the voltage detector vary +/-5.5% and +/-3.3%, respectively, over temperature, without trimming.

Design of Low-Power Low-noise CMOS ECG Amplifier for Smart Wearable Device

The artificial intelligence health care devices have focused on the portability and accuracy and the most trending area of wearable biomedical application has become the electrocardiogram (ECG) recording device. The ECG signals have the characteristic of low amplitude, prone to be influenced by Power Line Interference (PLI), so it is essential to achieve high gain and high common-mode rejection ratio (CMRR),while the input-referred noise and power consumption need to be low to realize the cardiac screening system on chip (Soc).In this paper, a low-noise low-power analog front end (AFE) amplifier which based on Driven-Right-Leg circuit(DRL) has been proposed. It was implemented in CMOS 180 nm with bias current and supply voltage of 12µA and 0.7V, respectively. The simulation results showed that this front-end circuit can achieve a low input referred noise of 4.11µV/Hz and high common mode rejection ratio of 135dB. It also gave voltage gain of 41.8 dB with the bandwidth from 0.1Hz to 100Hz and the total power consumption was 4.32µW. Compared with recently relevant whole circuit design, we believe that it is suitable to be used in smart wearable device.

Low-power Bulk-driven Subthreshold OTA and CCII+ Cells based Instrumentation Amplifier for LF Applications

This paper at onset describes a low-power, bulk-driven, folded cascode (FC-OTA) and second generation positive current conveyor (CCII+) operating in weak inversion region with ± 0.35 V DC bias supply. The designed 2 or 3 numbers of CCII+ cells are utilized to compose an instrumentation amplifier (IA), which dissipates a total power of 3.847 µW or 5.768 µW. The OTA cell as the input core in CCII+ circuitry consumes a power of 287 nW, whereas the CCII+ cell consumes total power of 1918 nW. The CCII+ cell uses an OTA which is followed by two-CMOS class AB inverters to realize the X and Z terminals of CCII+ cell. Further, these CCII+ cells are utilized to get low power IA usable in analog front ends of DSP processor for amplifying sensed signal with very high-common mode rejection ratio (CMRR) and high-power supply rejection ratio (PSRR). This IA is simulated using tanner EDA tool of version 16.1 in 180 nm n-tub standard CMOS process technology. This IA consumes less power and is usable as variable gain amplifier for low- frequency bio-signal as well as sub-audio frequency range signal processing.

A Power Management System for Electromagnetic Energy Harvesters in Battery/Batteryless Applications

This article presents a miniaturized and cost-effective power management system (PMS) for low-voltage electromagnetic energy harvesters (EMEHs) operating in both battery-powered and batteryless applications. The PMS consists of two converters and their associated controllers. The first converter converts EMEH’s ac voltage into a dc one in a single step and provides a maximum efficiency point tracking (MEPT) feature to maximize the harvested energy and can be used alone in battery-powered applications. The second converter provides tight output voltage regulation for batteryless applications. The MEPT converter utilizes a topology that uses a single inductor shared between the positive and negative half cycles of the EMEH voltage, unlike the majority of existing solutions, hence achieving system’s cost and size reductions. In addition, its control architecture is based on low-power comparators and does not require zero-crossing detection (ZCD) block, in contrast to many existing solutions, allowing for further reduction in cost, losses, and size. Moreover, the shared inductor is not only used by the power stage but also as a key element of the bias supply scheme allowing for voltage stepping up and hence providing sufficient voltage to supply the control circuits. The voltage regulation converter features a highly integrated dc–dc converter where the power inductor serves as normal inductor and a substrate for the converter. Experimental results show the effectiveness of the PMS with an EMEH that has a damped ac voltage characteristics ranging from 1.0 V to 10 mV for battery and batteryless applications. The presented MEPT converter, switching at 40 kHz, achieves 32.3-mm3 magnetics volume, which is the biggest contributor to the real estate of the PMS. Also, it can harvest up to 17 mJ out of 20 mJ available energy while achieving a BOM cost less than 0.7€. Moreover, the highly integrated buck converter, switching at 4 MHz, provides a tight regulated voltage of 1.2 V at 5 mA for a group of wireless sensors while achieving efficiency of 80% for load currents between $100~\mu \text{A}$ and 200 mA.

Novel self-biasing circuit for dielectric elastomer generator and its parameter optimization

In order to solve the problem that a dielectric elastomer generator (DEG) requires an external high voltage bias supply to improve the autonomy and security of the power generation system so that it could adapt to a changeable environment, and to improve the efficiency of power generation, based on the simulation research and analysis of three traditional self-biasing circuits, a new self-biasing circuit integrated with a self-supplementary circuit has been proposed in this paper. Under the same input conditions, the maximum output potential of the new self-biasing circuit is 2.23 times that of the traditional circuit. The pumping capability of the self-biasing circuit is greatly improved. At the same time, based on this circuit, in order to explore the factors affecting the energy conversion of the DEG, the overall electromechanical parameters of the circuit are compared and optimized by simulation experiments in this paper. The simulation and experimental results show that the capacitance-to-strain ratio of DEG and the mechanical frequency should be as large as possible within the safe range to obtain larger output potential, and the capacitance of charge pump should be 0.75 times of the capacitance of DEG in the initial state to improve efficiency.

The Complete Switching Circuit Design for CPU Joint Body Biasing and Supply Voltage Scaling

The modern CPU technology scaling with increasing transistor density causes an exponential growth of both dynamic and static power dissipations that affecting the microprocessor’s performance. The body bias voltage (VBB) and supply voltage (VDD) extent to decrease to maintain the low power requirements. Joint body biasing and voltage scaling is an efficient technique that reduces the power dissipation of CPUs and high performance digital devices when peak performance is unneeded. Switching networks have become an essential component in the design of digital ICs that require the ability to control and select a specified threshold voltage/body-bias and supply voltages (VTH/VBB-VDD) for the microprocessor chip. This paper presents a complete design of a switching network for joint body biasing and supply voltage scaling (VBB-VDD), which is consistent in allowing compact low power consumption and low temperatures in the core of high-performance processors. The results show the roles and effectiveness of the switching network that adaptively selects the VTH/VBB-VDD sets for different workloads and simulation environments and all temperature ranges.

Selective Flip-Flop Optimization for Reliable Digital Circuit Design

Runtime variability sources, such as bias temperature instability (BTI) and supply voltage fluctuation affect both timing and functionality of the flip-flops inside a VLSI circuit. In this paper, we propose a method to improve the timing and reliability of the VLSI circuits by optimizing the flip-flops for resiliency against aging and supply voltage fluctuation. In the proposed selective reliability optimization method, we first extend the standard cell libraries by adding optimized versions of the flip-flops designed for better resiliency against severe BTI impact and/or supply voltage fluctuation. Then, we optimize the VLSI circuit by replacing the aging-critical and voltage-drop-critical flip-flops (VC) of the circuit with the reliability-optimized versions to improve the timing and the reliability of the entire circuit in a cost-effective way. The simulation results show that incorporating the optimized flip-flops in a processor can prolong the lifetime of the processor by 36.9% compared to the original design, which translates into better reliability. This is achieved with negligible leakage overhead (less than 0.1% on the processor) and no area overhead which facilitates the integration of the proposed method in the standard VLSI design flow.

Circuit Design for Thermal Compensation of Avalanche Photodiode

It has been observed that the breakdown voltage of the avalanche photodiode (APD) changes with the change in the ambient temperature. This situation may result in a poorer signal to noise ratio and sometimes to permanent damage to the APD. In order to overcome these problems, various considerations may be taken into account, including maintaining the temperature of the APD permanently or the design of a bias system, which would be self-adjusting according to any changes in the temperature. The latter technique was adopted and the design of a bias supply is presented in this article.