Bilayer Passivation Research Articles

Fabrication of Ge Metal–Oxide–Semiconductor Capacitors with High-Quality Interface by Ultrathin SiO2/GeO2Bilayer Passivation and Postmetallization Annealing Effect of Al

A novel method of electrical passivation of a Ge surface by an ultrathin SiO2/GeO2 bilayer is proposed as an effective method for fabricating metal–oxide–semiconductor (MOS) structures, which can be processed through the thermal etching of GeO2 by vacuum annealing and subsequent SiO2 deposition. We demonstrated the feasibility of this passivation technique by performing interface state density (Dit) measurements of MOS capacitors, which were fabricated using several surface preparations and subsequent gate insulating film deposition. A Dit of 4×1011 cm-2 eV-1 was obtained at around midgap. We also investigated the effect of postmetallization annealing after Al deposition (Al-PMA). Al-PMA was found to be very effective for decreasing Dit, which was 9.4×1010 cm-2 eV-1 at around midgap for a capacitor with PMA at 400 °C. The role of Al as a defect terminator was discussed.

Reduced surface leakage current and trapping effects in AlGaN/GaN high electron mobility transistors on silicon with SiN/Al2O3 passivation

The surface leakage currents and the surface trapping effects of the AlGaN/GaN high electron mobility transistors (HEMTs) on silicon with different passivation schemes, namely, a 120 nm plasma enhanced chemical vapor deposited SiN, a 10 nm atomic layer deposited (ALD) Al2O3 and a bilayer of SiN/Al2O3 (120/10 nm) have been investigated. After SiN passivation, the surface leakage current of the GaN HEMT was found to increase by about six orders; while it only increased by three orders after the insertion of Al2O3 between SiN and AlGaN/GaN. The surface conduction mechanism is believed to be the two-dimensional variable range hopping for all the samples. The leakage current in the etched GaN buffer layer with SiN/Al2O3 bilayer passivation was also much smaller than that with only SiN passivation. The pulse measurement shows that the bilayer of SiN/Al2O3 passivation scheme can effectively reduce the surface states and suppress the trapping effects.

Fabrication of Ge-MOS capacitors with high quality interface by ultra-thin SiO 2/GeO 2 bi-layer passivation combined with the subsequent SiO 2-depositions using magnetron sputtering

Ge-MOS capacitors were fabricated by a novel method of ultra-thin SiO 2/GeO 2 bi-layer passivation (BLP) for Ge surface combined with the subsequent SiO 2-depositions using magnetron sputtering. For the Ge-MOS capacitors fabricated by BLP with O 2, to decrease oxygen content in the subsequent SiO 2 deposition is helpful for improving interface quality. By optimizing process parameters of the Ge surface thermal cleaning, the BLP, and the subsequent SiO 2 deposition, interface states density of 4 × 10 11 cm −2 eV −1 at around mid-gap was achieved, which is approximately three times smaller than that of non-passavited Ge-MOS capacitors. On the contrary, for the Ge-MOS capacitors fabricated by BLP without O 2, interface quality could be improved by an increase in oxygen contents during the subsequent SiO 2 deposition, but the interface quality was worse compared with BLP with O 2.

Bi-layer SixNy passivation on AlGaN/GaN HEMTs to suppress current collapse and improve breakdown

SixNy deposited at low temperature was found to improve the breakdown voltage of AlGaN/GaN HEMTs at the expense of current collapse due to the presence of a high density of charge trapping states. On the other hand, stoichiometric Si3N4 film deposited at high temperature was effective in mitigating current slump but no improvement in the breakdown voltage was observed. Combining the benefit of both films, a bi-layer stacked passivation has been employed on the HEMTs. Gate lag measurements revealed that the current collapse was mitigated and the breakdown voltage of the devices was found to increase from 120 V to 238 V upon passivation.

A DLTS Study of SiO2 and SiO2/SiNx Bi-Layer Surface Passivation of Silicon

Deep Level Transient Spectroscopy (DLTS) has been applied to Metal-Oxide-Semiconductor (MOS) capacitors fabricated on crystalline silicon n- and p-type substrates, with a SiO2 or a SiO2/SiNx bi-layer passivation stack, covered by an Al gate. It is shown that similar interface state distributions are obtained in both cases, from which it is concluded that the SiNx deposition does not degrade the interface. It is also shown that a rather large density of dangling bond defects is present at the Si/SiO2 interface, which is related to the absence of a post metallization forming gas annealing.

High Efficiency Silicon Solar Cells with Bilayer Passivation Structure

The effects of passivation on monocrystalline silicon solar cells were investigated. Al 2 O 3 and SiO 2 films, prepared by atomic layer deposition and thermal oxidation, respectively, were used as passivation layers. Passivation using a monolayer (SiO 2 ) yielded a cell efficiency of 17.5%. However, the Al 2 O 3 /SiO 2 bilayer structure drastically increased cell efficiency to 20.1%. Quantum efficiency results revealed a significant improvement in the IR range, suggesting that bilayer passivation was effective on the back of a solar cell in providing a high energy conversion efficiency.

Electrochemical Measurements Demonstrate Performance of BTAH and Alternative Passivating Agents on Copper in a Hydroxylamine CMP System

Organic passivating agents have been measured by a galvanostatic method during abrasive free Chemical Mechanical Planarization (CMP) of copper coated silicon wafers. CMP process steps include (a) removal of the passivation layer to expose the metal surface, (b) wet chemical oxidation of the metal surface and (c) mechanical removal of the oxidation products by means of the pad with a colloidal polishing aid such as silica or alumina1. CMP of necessity seeks to establish a unique equilibrium between little or no metal removal due to corrosion effects and rapid metal removal resulting from a mechanically aided chemical oxidation or polishing. Chemical oxidizing agents can corrode the metal surface during polishing and non-polishing steps alike so protective passivation agents are necessary to inhibit or block surface corrosion. Historically, benzotriazole (BTAH) has been the copper protective agent of choice because it performed well at concentrations of 50 to 500ppm, however BTAH can scratch copper. Self-assembly of monolayers was reported by Sung et al2 demonstrating a tendency toward organizational energy of molecular surface protection. Cho et al3 have reported formation of a flat, well ordered BTAH based monolayer on copper supporting a three dimensional BTAH stack above it. Metrikos-Hukovic et al4 reported evidence for a monolayer of a CuBTA compound and additional adsorption/crystallization layers of 7nm thickness5 were measured. Discussions in this work refer to the combined adsorption/chelation layers on copper as passivation providing measurements that distinguish between them. It will be shown that addition of BTAH forms a thin layer of CuBTA covered by a second layer creating a protective film with relatively high electrical resistance. The purpose of this electrochemical effort is to measure the effect of BTAH during a non-Prestonian, slurry free CMP process, to affect a direct measure of bi-layer passivation and to identify other organic compounds that may also provide protection of the copper surface against corrosion.

Infant feeding and tile development of schizophrenia

We investigated the electrical properties and stability of short-channel half-Corbino amorphous In–Ga–Zn–O (a-IGZO) thin-film transistors (TFTs). In the linear region, the fabricated half-Corbino a-IGZO TFT with a channel length of 4.5 μm achieves a geometrical factor (fg) of ∼2.7, a threshold voltage (VT) of ∼2.4 V, a field-effect mobility (μeff) of ∼15 cm2/Vs, a subthreshold swing (SS) of ∼320 mV/dec and an off-current (IOFF) < 10−13 A. In the saturation region, asymmetric electrical characteristics such as drain current were observed under different drain bias conditions. The electrical properties asymmetry of half-Corbino a-IGZO TFTs was explained by various geometrical factors owing to the short-channel effect. The reduced VT and increased SS at VDS = 15 V is explained by the drain-induced Schottky barrier lowering. In addition, the bias-temperature stress (BTS) was performed for half-Corbino a-IGZO TFTs with both amorphous silicon oxide (a-SiOx) single layer and a-SiOx/amorphous silicon nitride (a-SiNx) bilayer passivation (PV) structures. The device with bilayer PV shows a threshold voltage shift (ΔVT) of +2.07 and −0.5 V under positive (PBTS = +15 V) and negative BTS (NBTS = −15 V) at 70 °C for 10 ks, respectively. The origins of ΔVT during PBTS and NBTS for half-Corbino a-IGZO TFTs with single and bilayer PV structures were studied. To improve the device electrical stability, the bilayer PV structure should be used.