Bilayer Passivation Research Articles

Broad range refractive index engineering of SixNy and SiOxNy thin films and exploring their potential applications in crystalline silicon solar cells

Silicon nitride (SixNy) and silicon oxynitride (SiOxNy) are materials that can find multifarious application in solar cells by tuning their microstructure and optical properties. In this work we have investigated a series of SixNy and SiOxNy films deposited by rf-PECVD at a low temperature of 200 °C having different compositional and optical properties by changing the gas mixture ratio during deposition resulting in varying refractive index materials. The effect of varying gas ratio on the composition of these materials has been investigated comprehensively by X-ray Photoelectron Spectroscopy (XPS) and the bond analysis using Fourier Transform Infrared Spectroscopy (FTIR) thereby creating a material library to select materials of desired properties and bond composition for specific applications in solar cells. The structural and optical properties were also analysed using Micro-Raman spectroscopy, X-ray Diffraction (XRD), UV-VIS-NIR spectrophotometer and ellipsometry. The films were found to be amorphous, hydrogenated, compact, presents high deposition rates and needs lesser thermal budget. In order to demonstrate their multifaceted application potential, we have fabricated multilayer anti-reflection coatings (ARC), novel Rugate ARC, dielectric Bragg mirrors using SiOxNy/SixNy multi layers as back reflectors for thin crystalline silicon (c-Si) wafers as well as the passivation of c-Si. The novel bilayer passivation stack over CZ p-type c-Si wafers using SiOxNy/SixNy presented a minority carrier lifetime of 169 μs with an implied Voc of 673 mV.

Investigation of <italic>In Situ</italic> SiN as Gate Dielectric and Surface Passivation for GaN MISHEMTs

In this paper, we present a systematic investigation of metal–organic chemical vapor deposition-grown in situ SiN as the gate dielectric and surface passivation for AlGaN/GaN metal insulator semiconductor high electron mobility transistors (MISHEMTs). The dielectric constant and breakdown field of the in situ SiN were extracted from devices with varied gate dielectric thicknesses. Using frequency-dependent capacitance–voltage and parallel conductance methods, we obtained a low trap density of $\sim 3\times 10^{12}$ cm $^{-2}$ eV $^{-1}$ at the SiN/AlGaN interface. The MISHEMTs with a source–drain distance of $3~\mu \text{m}$ show a maximum drain current of 1560 mA/mm and a high on/off current ratio of $10^{9}$ . The device threshold voltage ( ${V}_\textsf {th}$ ) stability was assessed by means of both negative and positive gate stress measurements, as well as temperature-dependent $ {I}_\textsf {D}$ – ${V}_\textsf{G}$ measurements. We observed a minimal $ {V}_\textsf{th}$ shift of ~0.4 V under both 3000 s gate stress of ${V}_\textsf {GS}= 4$ V and up to 200 °C thermal stimulation. Furthermore, combining the in situ SiN with plasma-enhanced chemical vapor deposition SiN, we developed a bilayer passivation scheme for effective suppression of current collapse. Employing the high-quality in situ SiN, we have demonstrated large-area GaN MISHEMTs on Si with a gate width of 20 mm, showing a low off-state leakage of $2~\mu \text{A}$ /mm at 600 V and a low dynamic/static ON-resistance ratio. The device results show great advantages of employing in situ SiN in D-mode GaN MISHEMTs for high-efficiency power switching applications.

Substrate and Passivation Techniques for Flexible Amorphous Silicon-Based X-ray Detectors.

Flexible active matrix display technology has been adapted to create new flexible photo-sensing electronic devices, including flexible X-ray detectors. Monolithic integration of amorphous silicon (a-Si) PIN photodiodes on a flexible substrate poses significant challenges associated with the intrinsic film stress of amorphous silicon. This paper examines how altering device structuring and diode passivation layers can greatly improve the electrical performance and the mechanical reliability of the device, thereby eliminating one of the major weaknesses of a-Si PIN diodes in comparison to alternative photodetector technology, such as organic bulk heterojunction photodiodes and amorphous selenium. A dark current of 0.5 pA/mm2 and photodiode quantum efficiency of 74% are possible with a pixelated diode structure with a silicon nitride/SU-8 bilayer passivation structure on a 20 µm-thick polyimide substrate.

Half-Corbino short-channel amorphous In–Ga–Zn–O thin-film transistors with a-SiOx or a-SiOx/a-SiNx passivation layers

We investigated the electrical properties and stability of short-channel half-Corbino amorphous In–Ga–Zn–O (a-IGZO) thin-film transistors (TFTs). In the linear region, the fabricated half-Corbino a-IGZO TFT with a channel length of 4.5μm achieves a geometrical factor (fg) of ∼2.7, a threshold voltage (VT) of ∼2.4V, a field-effect mobility (μeff) of ∼15cm2/Vs, a subthreshold swing (SS) of ∼320mV/dec and an off-current (IOFF)<10−13A. In the saturation region, asymmetric electrical characteristics such as drain current were observed under different drain bias conditions. The electrical properties asymmetry of half-Corbino a-IGZO TFTs was explained by various geometrical factors owing to the short-channel effect. The reduced VT and increased SS at VDS=15V is explained by the drain-induced Schottky barrier lowering. In addition, the bias-temperature stress (BTS) was performed for half-Corbino a-IGZO TFTs with both amorphous silicon oxide (a-SiOx) single layer and a-SiOx/amorphous silicon nitride (a-SiNx) bilayer passivation (PV) structures. The device with bilayer PV shows a threshold voltage shift (ΔVT) of +2.07 and −0.5V under positive (PBTS=+15V) and negative BTS (NBTS=−15V) at 70°C for 10ks, respectively. The origins of ΔVT during PBTS and NBTS for half-Corbino a-IGZO TFTs with single and bilayer PV structures were studied. To improve the device electrical stability, the bilayer PV structure should be used.

Effects of metal/Ge contact and surface passivation on direct band gap light emission and detection for asymmetric metal/Ge/metal diodes

Direct band gap electroluminescence (EL) and light detection were studied at room temperature for n-type bulk germanium (Ge) by using fin-type asymmetric lateral metal/Ge/metal diodes. HfGe/Ge and PtGe/Ge contacts were used for injecting holes. Electron cyclotron resonance plasma oxidation and physical vapor deposition bilayer passivation (BLP) methods were employed for passivating the surface of the active region. A high EL intensity and a low dark current intensity were observed for the sample with PtGe/Ge contact and BLP, owing to the small/large barrier height of holes/electrons for PtGe/Ge contact, respectively, and the low density of interface states for the active region with BLP. The local-heating-induced redshift of the EL peak for the sample with PtGe/Ge contact is smaller than that for the sample with HfGe/Ge contact, owing to the lower parasitic resistance of PtGe/Ge contact. The diode with PtGe/Ge contact and BLP shows an on/off ratio of ∼104 and a responsivity of 0.70 A/W, corresponding to an external quantum efficiency of 56.0% under a wavelength of 1.55 µm.

Improvement in reliability of amorphous indium–gallium–zinc oxide thin-film transistors with Teflon/SiO2 bilayer passivation under gate bias stress

The reliability of amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistors (TFTs) with Teflon/SiO2 bilayer passivation prepared under positive and negative gate bias stresses (PGBS and NGBS, respectively) was investigated. Heavier electrical degradation was observed under PGBS than under NGBS, indicating that the environmental effects under PGBS are more evident than those under NGBS. The device with bilayer passivation under PGBS shows two-step degradation. The positive threshold voltage shifts during the initial stressing period (before 500 s), owing to the charges trapped in the gate insulator or at the gate insulator/a-IGZO active layer interface. The negative threshold voltage shift accompanies the increase in subthreshold swing (SS) for the continuous stressing period (after 500 s) owing to H2O molecules from ambience diffused within the a-IGZO TFTs. It is believed that Teflon/SiO2 bilayer passivation can effectively improve the reliability of the a-IGZO TFTs without passivation even though the devices are stressed under gate bias.

Teflon/SiO₂ Bilayer Passivation for Improving the Electrical Reliability of Oxide TFTs Fabricated Using a New Two-Photomask Self-Alignment Process.

This study proposes a two-photomask process for fabricating amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistors (TFTs) that exhibit a self-aligned structure. The fabricated TFTs, which lack etching-stop (ES) layers, have undamaged a-IGZO active layers that facilitate superior performance. In addition, we demonstrate a bilayer passivation method that uses a polytetrafluoroethylene (Teflon) and SiO2 combination layer for improving the electrical reliability of the fabricated TFTs. Teflon was deposited as a buffer layer through thermal evaporation. The Teflon layer exhibited favorable compatibility with the underlying IGZO channel layer and effectively protected the a-IGZO TFTs from plasma damage during SiO2 deposition, resulting in a negligible initial performance drop in the a-IGZO TFTs. Compared with passivation-free a-IGZO TFTs, passivated TFTs exhibited superior stability even after 168 h of aging under ambient air at 95% relative humidity.

Effect of SiO&lt;sub&gt;2&lt;/sub&gt; and SiO&lt;sub&gt;2&lt;/sub&gt;/SiN&lt;sub&gt;&lt;italic&gt;x&lt;/italic&gt;&lt;/sub&gt; Passivation on the Stability of Amorphous Indium-Gallium Zinc-Oxide Thin-Film Transistors Under High Humidity

We studied the environmental stability of amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs) with single-layer (SiO2) and bilayer (SiO2/SiN x ) passivation under high-humidity (80%) storage. During the 30 days of investigation, all single-layer passivated TFTs showed negative turn-ON voltage shifts ( $\Delta V_{\mathrm{{\scriptstyle ON}}}$ ), the size of which increased with storing time. The negative $\Delta ~V_{\mathrm{{\scriptstyle ON}}}$ is attributed to donor generation inside the active a-IGZO caused by the diffusion of ambient hydrogen/water molecules passing through the SiO2 passivation layer. The X-ray photoelectron spectroscopy depth profile for the SiO2 passivated structures confirms that the concentration of oxygen vacancies, which is initially larger at the a-IGZO/SiO2 interface, compared with the bulk a-IGZO, decreases after 30 days of storage under high humidity. This can be explained as the passivation of oxygen vacancies by diffused hydrogen. On the other hand, all bilayer passivated TFTs showed good air stability at room temperature and high humidity (80%).

Low Current Collapse and Low Leakage GaN MIS-HEMT Using AlN/SiN as Gate Dielectric and Passivation Layer

Gallium nitride-based high-electron-mobility transistors (HEMTs) have demonstrated outstanding performance for high-power and high-frequency applications for defense and communication systems. However, there are many undesirable effects such as current collapse and increase in dynamic ON-resistance due to the surface donor states and the high polarization nature of the material [1], [2]. Nitride-based materials are more desirable for GaN passivation because the oxide-based materials have many oxygen contaminations on GaN. SiN has been proved as an effective passivation dielectric to reduce the surface states and can efficiently suppress current collapse in the GaN HEMTs [3]. However, the bandgap of SiN (∼5 eV) is not high enough to suppress leakage current. AlN has a large bandgap (∼6.2 eV) can effectively reduce leakage current as passivation layer [4]. In this work, we demonstrate GaN MIS-HEMT using AlN/SiN bilayer gate dielectric and passivation layer which combine the advantages of SiN and AlN. For comparing the performance of GaN MIS-HEMT with AlN/SiN bilayer gate dielectric, we also prepared reference devices with single layers dielectric. The wafer was divided into three samples after mesa and ohmic contact process. The dielectric and passivation layer were prepared differently for each sample: sample A with 5-nm SiN, sample B with 1-nm AlN/5-nm SiN, sample C with 5-nm AlN. Fig. 1 shows the I D-V D characteristics, where the drain current curves were measured at V G = 0 V. The SiN first passivated devices have higher I D and lower R ON as compared to AlN first passivated device. The R ON were 0.3 mΩ‧cm2, 0.3 mΩ‧cm2, and 0.33 mΩ‧cm2 for sample A, sample B, and sample C, respectively. For gate leakage shown in Fig. 2, GaN MIS-HEMTs using AlN as gate dielectric have lower gate leakage current. It means AlN can effectively suppress leakage current. Fig. 3 shows the percent degradation of R ON,DYN versus time. The OFF-state quiescent stress bias were set at V DSQ = 100 V and V GSQ = -10 V. The ON-state R ON,DYN is extracted at a gate voltage of 0 V and a drain voltage of 2 V. R ON,DYN degradation reflects the passivation quality including surface, interface, and barrier traps. GaN MIS-HEMT with AlN/SiN obviously suppresses R ON,DYN degradation compared to the single layer samples. Also, the SiN first passivated devices have slight R ON,DYN degradation. It indicates SiN has low interface trapping density on GaN surface and AlN can reduce trapping electrons charged through gate leakage. In conclusion, SiN was been proved that it has many good effects for GaN passivation such as decreasing of channel resistance, low surface state, low interface trapping density and low current collapse effect. AlN with high bandgap nature can suppress the leakage current. However, it would increase channel resistance, and cause severe current collapse effect. In this study, an effective AlN/SiN bilayer dielectric and passivation layer have been demonstrated for reducing current collapse effect and leakage current in GaN MIS-HEMT.Fig. 1 I D–V D characteristics of GaN HEMTs with different surface passivation layers.Fig. 2 Gate leakage current comparison in MIS-HEMTs structure.Fig. 3 Percent degradation of R ON,DYN versus time.[1] S. Binari, K. Ikossi, J. A. Rousos, et al., “Trapping effects and microwave power performance in AlGaN/GaN HEMTs,” IEEE Trans. Electron Devices, vol. 48, no. 3, pp. 465–471, Mar. 2001.[2] D. Jin and J. A. Alamo, “Methodology for the Study of Dynamic ON-Resistance in High-Voltage GaN Field-Effect Transistors,” IEEE Trans. Electron Devices, vol. 60, no. 10, pp. 3190–3196, Oct. 2013.[3] B. Green and K. Chu, “The effect of surface passivation on the microwave characteristics of undoped AlGaN/GaN HEMTs,” IEEE Device Lett., vol. 21, no. 6, pp. 268–270, Jun. 2000.[4] Z. Tang, S. Huang, Q. Jiang, S. Liu, C. Liu, and K. J. Chen, “High-Voltage (600-V) Low-Leakage Low-Current-Collapse AlGaN/GaN HEMTs With AlN/SiNx Passivation,” IEEE Device Lett., vol. 34, no. 3, pp. 366–368, Mar. 2013.

Silicon Nanowires Based Solar Cell Using Native Oxide and Silicon Nitride Bi-Layer Passivation

Silicon nanowires (SiNWs) based solar cells are passivated by native oxide and SiNx bi-layer. In comparison with cells passivated by SiNx single layer, bi-layer passivation exhibits higher effective minority lifetime, illustrating a better surface passivation effect, which leads to a gain of internal quantum efficiency in the short wavelength range, a better output performance with an increase of 0.16% in efficiency. The data obtained from this work is fundamental and has some reference value for future studies.

Teflon/SiO2 bilayer passivation for improving the electrical reliability of pentacene-based organic thin-film transistors

We demonstrate a bilayer passivation method using a Teflon and SiO2 combination layer to improve the electrical reliability of pentacene-based organic thin-film transistors (OTFTs). The Teflon was deposited as a buffer layer using a thermal evaporator that exhibited good compatibility with the underlying pentacene channel layer, and can effectively protect the OTFTs from plasma damage during the SiO2 deposition process, resulting in a negligible initial performance drop in OTFTs. Furthermore, because of the excellent moisture barrier ability of SiO2, the OTFTs exhibited good time-dependent electrical performance, even after 168h of aging in ambient air with 60–80% relative humidity.

(Invited) Gate Stack and Source/Drain Junction Formations for High-Mobility Ge MOSFETs

Ge is of great interest as a candidate channel material for future CMOS devices due to its high intrinsic carrier mobility. To translate this potential into CMOS, high-quality gate-stack and source/drain (S/D) junction formations are essential. We fabricated Ge n- and p-MOSFETs using the gate-stack formation by bilayer (SiO2/GeO2) passivation and using S/D junction formations by thermal diffusion of P and ion implantation of B. The electron and hole channel mobilities of the fabricated MOSFETs were 1097 and 376 cm2V-1s-1, respectively, despite the very thin GeO2 thickness. We will present the detailed fabrication method and device performance.

Rear surface protection and front surface bi-layer passivation for silicon nanostructure-textured solar cells

Silicon nanostructure arrays were synthesized via Ag-catalysed chemical etching on solar cells. In contrast to the traditional etching in HF/AgNO3, the new technique used in this work produced nanostructure textures located only on the front surface of the cells. Furthermore, a SiO2/SiNX bi-layer was used to passivate the surface of the cells. By these optimizations, nanostructure-textured cells' performance was improved. The data obtained from this work are fundamental and has some reference value for future studies.

Optimal hydrogenated amorphous silicon/silicon nitride bilayer passivation of n-type crystalline silicon using response surface methodology

This study reports the highest quality surface passivation achieved with hydrogenated amorphous silicon and amorphous silicon nitride (SiNx) bilayer stack deposited using plasma enhanced chemical vapour deposition on 1–2 Ωcm n-type crystalline silicon. The SiNx deposition conditions were investigated using response surface methodology (RSM). Optimized deposition parameters obtained from the RSM study yielded a low surface recombination velocity (SRV) of 3.5 cm/s. Interface defect and charge densities, inferred using the interface dangling bond recombination model, revealed a strong influence of charge on the SRV reduction. The model predicts a lower SRV of 1.5 cm/s for the bilayer passivation scheme.

An accurate characterization of interface-state by deep-level transient spectroscopy for Ge metal-insulator-semiconductor capacitors with SiO2/GeO2 bilayer passivation

For Ge metal-insulator-semiconductor (MIS) capacitors with a GeO2 interfacial layer, interface-state density (Dit) was accurately characterized using deep-level transient spectroscopy. Elimination of the influence of slow-traps in the gate dielectric film on Dit characterization is described in detail. This was achieved by optimizing the injection pulse and quiescent reverse-bias voltages at each temperature. Dit values of approximately 5 × 1010 cm−2 eV−1 were observed at around mid-gap for both the n- and p-Ge-MIS capacitors with a TiN-gate, for which an asymmetric U-shape energy distribution in Dit was also observed. Furthermore, the effects of post-metallization annealing (PMA) on Dit improvement and slow-trap passivation were also investigated for Al-gated p-Ge-MIS capacitors, on which the defect passivation mechanism in Al-PMA is discussed. A reasonable correspondence was also observed between gate-film quality for Al-gated p-Ge-MIS capacitors and channel mobility in Ge-p-MIS field effect transistors with the gate fabricated by the same process as for p-Ge-MIS capacitors.

Research on the surface passivation of nanostructure-textured crystalline silicon solar cell

Nanostructure-textured solar cell owns unique properties but has some shortages especially in its fabrication and passivation. In this paper, nanostructures for crystalline silicon solar cell have been synthesized by controllable method based on silver catalyzed chemical etching. In this way, only the front surface of cell is etched and rear surface is protected. It was found that cells textured via the new method obtained equally excellent optical while superior electrical properties compared with those textured via traditional HF/AgNO3 etching. The V OC and I SC of the cell were improved by 6% and 11%, respectively. Then the cells were passivated via a bi-layer passivation (SiO2 & SiN x ), in contrast to traditional SiN x passivation. It was also found that cells with new passivation exhibited improved V OC and I SC by 4% and 25%, respectively. The encouraging results can provide fundamental data for developing the nanostructure-textured crystalline silicon solar cell in following researches.

Thermally Evaporated SiO Thin Films As a Versatile Interlayer for Plasma-Based OLED Passivation

Silicon monoxide (SiO) thin films were introduced as an efficient interlayer for achieving plasma-based organic light-emitting diode (OLED) surface passivation. The SiO thin films could be consecutively formed via thermal evaporation, without breaking the vacuum, after deposition of the OLED cathode. The plasma resistivity and UV-blocking characteristics of the SiO interlayer protected the OLED devices against electrical and optical degradation during the plasma-enhanced atomic layer deposition (PEALD) and plasma-enhanced chemical vapor deposition (PECVD) passivation processes. In addition, the nonconformal deposition and hydroxyl group-rich surface characteristics of the SiO thin films yielded enhanced surface pinhole coverage and a higher initial film density in the subsequently deposited PEALD-based Al2O3 barrier film. As a result, the OLEDs with a SiO/Al2O3 bilayer passivation layer displayed a remarkably increased device shelf life compared to devices prepared using Al2O3-only passivation. A MOCON test showed that the water vapor transmission rate (WVTR) of the SiO/Al2O3 bilayer film was 0.0033 g/(m(2) day), 2.3 times lower than the rate of a single Al2O3 barrier film. The results of our study demonstrated the multipurpose role of a SiO interlayer in plasma-based OLED passivation. The layer acted as a damage-free protective layer for the underlying OLED devices and an assistant layer to improve the upper barrier film performance.

Nanostructure Formation and Passivation of Large‐Area Black Silicon for Solar Cell Applications

Nanoscale textured silicon and its passivation are explored by simple low-cost metal-assisted chemical etching and thermal oxidation, and large-area black silicon was fabricated both on single-crystalline Si and multicrystalline Si for solar cell applications. When the Si surface was etched by HF/AgNO(3) solution for 4 or 5 min, nanopores formed in the Si surface, 50-100 nm in diameter and 200-300 nm deep. The nanoscale textured silicon surface turns into an effective medium with a gradually varying refractive index, which leads to the low reflectivity and black appearance of the samples. Mean reflectance was reduced to as low as 2% for crystalline Si and 4% for multicrystalline Si from 300 to 1000 nm, with no antireflective (AR) coating. A black-etched multicrystalline-Si of 156 mm × 156 mm was used to fabricate a primary solar cell with no surface passivation or AR coating. Its conversion efficiency (η) was 11.5%. The cell conversion efficiency was increased greatly by using surface passivation process, which proved very useful in suppressing excess carrier recombination on the nanostructured surface. Finally, a black m-Si cell with efficiency of 15.8% was achieved by using SiO(2) and SiN(X) bilayer passivation structure, indicating that passivation plays a key role in large-scale manufacture of black silicon solar cells.

Postmetallization annealing effect of TiN-gate Ge metal-oxide-semiconductor capacitor with ultrathin SiO2/GeO2 bilayer passivation

The postmetallization annealing (PMA) effect was investigated for a TiN-gate Ge metal-oxide-semiconductor capacitor with an ultrathin SiO2/GeO2 bilayer passivation. PMA at 450 °C led to the incorporation of nitrogen atoms into the gate stack. Consequently, the flat band voltage shifted from −0.79 to +0.23 V, resulting from a decrease in the dipole at the SiO2/GeO2 interface and the accompanying creation of a negative charge. The hysteresis decreased from 98 to 27 mV and the interface state density decreased from 6×1011 to 2.5×1011 cm−2 eV−1, as results of the nitrogen termination of defects at the SiO2/GeO2 interface and/or in the GeO2 interlayer.

Fabrication of Ge Metal–Oxide–Semiconductor Capacitors with High-Quality Interface by Ultrathin SiO2/GeO2 Bilayer Passivation and Postmetallization Annealing Effect of Al

A novel method of electrical passivation of a Ge surface by an ultrathin SiO2/GeO2 bilayer is proposed as an effective method for fabricating metal–oxide–semiconductor (MOS) structures, which can be processed through the thermal etching of GeO2 by vacuum annealing and subsequent SiO2 deposition. We demonstrated the feasibility of this passivation technique by performing interface state density (Dit) measurements of MOS capacitors, which were fabricated using several surface preparations and subsequent gate insulating film deposition. A Dit of 4×1011 cm-2 eV-1 was obtained at around midgap. We also investigated the effect of postmetallization annealing after Al deposition (Al-PMA). Al-PMA was found to be very effective for decreasing Dit, which was 9.4×1010 cm-2 eV-1 at around midgap for a capacitor with PMA at 400 °C. The role of Al as a defect terminator was discussed.