Benchmark Traces Research Articles

Electro‐field alignment in a novel metal–organic framework for benchmark separation of ethylene from a ternary gas mixture

AbstractOne‐step separation of C2H4 from ternary gas mixtures containing acetylene (C2H2), ethylene (C2H4), and carbon dioxide (CO2) represents a great challenge in chemical industry. Herein, we report the electro‐field alignment in a novel anion‐pillared MOF (SIFSIX‐TEPE‐Cu) for benchmark C2H4 separation from C2H2/CO2/C2H4 gas mixtures. The semi‐cage cavities featuring capped facets generated negative potentials along anion pillars and compensatory positive‐charged electro‐fields along organic ligands (TEPE) that facilitate specific recognitions of C2H2 and CO2 over C2H4. As a result, SIFSIX‐TEPE‐Cu exhibits high adsorption capacities for C2H2 (123 cm3 g−1) and CO2 (65 cm3 g−1) at 1.0 bar and 298 K. Notably, the record‐high C2H2 uptake (78 cm3 g−1) at 0.01 bar and remarkable C2H2/C2H4 selectivity (615.2) renders benchmark trace C2H2 removal ability. Dynamic breakthrough experiments demonstrate the benchmark productivity for high‐purity C2H4 (>99.995%) of 194.7 mol kg−1 and 5.96 mol kg−1 from binary C2H2/C2H4 (1/99, v/v) and ternary C2H2/CO2/C2H4 (1/9/90, v/v/v) gas mixtures.

Programmed fluorine binding engineering in anion-pillared metal-organic framework for record trace acetylene capture from ethylene.

Porous physisorbents are attractive candidates for selective capture of trace gas or volatile compounds due to their low energy footprints. However, many physisorbents suffer from insufficient sorbate-sorbent interactions, resulting in low uptake or inadequate selectivity when gases are present at trace levels. Here, we report a strategy of programmed fluorine binding engineering in anion-pillared metal-organic frameworks to maximize C2H2 binding affinity for benchmark trace C2H2 capture from C2H4. A robust material (ZJU-300a) was elaborately designed to provide multiple-site fluorine binding model, resulting in an ultrastrong C2H2 binding affinity. ZJU-300a exhibits a record-high C2H2 uptake of 3.23 millimoles per gram (at 0.01 bar and 296 kelvin) and one of the highest C2H2/C2H4 selectivity (1672). The adsorption binding of C2H2 and C2H4 was visualized by gas-loaded ZJU-300a structures. The separation capacity was confirmed by breakthrough experiments for 1/99 C2H2/C2H4 mixtures, affording the maximal dynamic selectivity (264) and C2H4 productivity of 436.7 millimoles per gram.

FRDS: An efficient unique on-Chip interconnection network architecture

Networks-on-Chip (NoC) is an impending research area for designing future System-on-Chip (SoC). NoC futures are allied with intellectual property (IP) reusability, parallel communication within IPs and scalability against standard interconnection NoC topology. In this paper, we introduce a new hybrid topology namely Four Regular Dense Spidergon (FRDS) based deterministic NoC architecture with 64 cores. We propose cluster and generic heuristic based approach For mapping of applications onto FRDS topology. Genetic algorithm (GA) ＋ simulated annealing (SA) have been considered under generic heuristic approach for successful mapping of core into topology and fair comparison of the performance of the proposed FRDS. Under normalized condition with respect to Mesh, experimental findings of proposed FRDS against real benchmark traces provide an average improvement on execution time with 1.20% and 4.81% over DMesh and ZMesh. Further, an average improvement on energy consumption was obtained 8.13% and 5.35% over DMesh and ZMesh. We adopt constant geometric traffic and the synthetic traffic pattern to measure the performance of proposed FRDS. The experimental results clearly indicates an improvement in power latency product under geometric traffic by 16.27% and 12.23% over DMesh and ZMesh. Similarly under synthetic traffic pattern, the proposed FRDS offers an improvement up to 22.51% and 45.53% over DMesh and ZMesh respectively. To realize the effectiveness of the link usage, brief evaluation of link utilization has been carried out with balanced load.

A novel method for victim block selection for NAND flash-based solid state drives based on scoring

The NAND flash memories have endurance issues in a high-performance computing (HPC) environment because of their blocks’ limited lifetime. Hence, the NAND flash block allocation and reclamation policies have a significant impact on its lifetime improvement. To address this problem, the scoring-based method is proposed in this paper, which employs priority-based victim block and active block selection methods. The priority of a block is estimated based on both of the score and a time factor. The comprehensive experiments using both realistic and synthetic benchmark traces are performed. The SSDsim simulation environment is extended to implement this method. The results reveal that in comparison with other methods, the proposed method improves endurance by at least 38%.

Estimating the Parameters of Mixed Shifted Negative Binomial Distributions via an EM Algorithm

Discrete phase-type (DPH) distributions have one property that is not shared by continuous phase-type (CPH) distributions, i.e., representing a deterministic value as a DPH random variable. This property distinguishes the application of DPH in stochastic modeling of real-life problems such as stochastic scheduling where service time random variables should be compared with a deadline that is usually a constant value. In this paper, we consider a restricted class of DPH distributions, called Mixed Shifted Negative Binomial (MSNB) and show its flexibility in producing a wide range of variances as well as its adequacy in fitting fat-tailed distributions. These properties render MSNB applicable to represent data on certain types of service time. Therefore, we adapt an expectation-maximization (EM) algorithm to estimate the parameters of MSNB distributions that accurately fit trace data. To present the applicability of the proposed algorithm, we use it to fit real operating room times as well as a set of benchmark traces generated from continuous distributions as case studies. Finally, we illustrate the efficiency of the proposed algorithm by comparing its results to that of two existing algorithms in the literature. We conclude that our proposed algorithm outperforms other DPH algorithms in fitting trace data and distributions.

Adaptive weight-based: an exclusive bypass algorithm for L3 cache in a three level cache hierarchy

Cache memory plays a decisive role in recent day processors. Current processors use multi-level cache hierarchy to avoid the capacity misses. Still processors have to pay high cost due to conflict misses. To avoid such misses, several replacement techniques are used in the cache memory. Whereas, in a multi-level cache, where enormous applications are running simultaneously, a bypass replacement technique in the last level cache is found significant from the reduced miss cost, CPU performance point of view. This paper presents a similar solution of bypassing in the L3 cache, called adaptive weight-based (AWB) bypass algorithm which shows better performance assessment compared to LRU with different benchmark traces from SPEC.

Adaptive weight-based: an exclusive bypass algorithm for L3 cache in a three level cache hierarchy

Cache memory plays a decisive role in recent day processors. Current processors use multi-level cache hierarchy to avoid the capacity misses. Still processors have to pay high cost due to conflict misses. To avoid such misses, several replacement techniques are used in the cache memory. Whereas, in a multi-level cache, where enormous applications are running simultaneously, a bypass replacement technique in the last level cache is found significant from the reduced miss cost, CPU performance point of view. This paper presents a similar solution of bypassing in the L3 cache, called adaptive weight-based (AWB) bypass algorithm which shows better performance assessment compared to LRU with different benchmark traces from SPEC.

Budgeting and Public Debt within a System of Cooperative Democracy

This paper is the penultimate draft of the fourth of six chapters of a book titled Public Debt: An Illusion of Democratic Political Economy. This essay establishes an analytical benchmark of a democratic system in which political outcomes reflect genuine consensus among the participants. This benchmark traces to Antonio de Viti de Marco’s construction of contrasting models of democratic action. The theory of a wholly cooperative democratic regime provides a benchmark against which to examine actual democratic processes and arrangements. In this respect, and looking ahead, de Viti recognized that democratic regimes were not passive reflectors of individual preference orderings because they entailed relationships of domination-and-subordination.

Efficient Victim Block Selection for Flash Storage Devices

Motivated by the needs to enhance the performance of garbage collection in low-cost flash storage devices, we propose a victim block selection design to efficiently identify the blocks for erases and reclaim the space of invalid data without extensively scanning flash memory for the data status stored in the storage, so as to improve the garbage collection performance on reclaiming the space of invalid data. Moreover, this design could easily identify and reclaim the space released by file systems. Experiments based on benchmark traces show significant performance improvement of garbage collection with limited system overheads.

HAT: an efficient buffer management method for flash-based hybrid storage systems

Flash solid-state drives (SSDs) provide much faster access to data compared with traditional hard disk drives (HDDs). The current price and performance of SSD suggest it can be adopted as a data buffer between main memory and HDD, and buffer management policy in such hybrid systems has attracted more and more interest from research community recently. In this paper, we propose a novel approach to manage the buffer in flash-based hybrid storage systems, named hotness aware hit (HAT). HAT exploits a page reference queue to record the access history as well as the status of accessed pages, i.e., hot, warm, and cold. Additionally, the page reference queue is further split into hot and warm regions which correspond to the memory and flash in general. The HAT approach updates the page status and deals with the page migration in the memory hierarchy according to the current page status and hit position in the page reference queue. Compared with the existing hybrid storage approaches, the proposed HAT can manage the memory and flash cache layers more effectively. Our empirical evaluation on benchmark traces demonstrates the superiority of the proposed strategy against the state-of-the-art competitors.

Extending the Energy Efficiency and Performance With Channel Buffers, Crossbars, and Topology Analysis for Network-on-Chips

Network-on-chips (NoCs) have emerged as a scalable solution to the wire delay constraints, thereby providing a high-performance communication fabric for future multicores. Research has shown that power, area, and performance of the NoC architecture are tightly integrated with the design and optimization of the link, router (buffer and crossbar), and topology. Recent work has shown that adaptive channel buffers (on-link storage) can considerably reduce power consumption and area overhead by reducing or replacing the power-hungry router buffers. However, channel buffer design can lead to head-of-line (HoL) blocking, which eventually reduces the throughput of the network. In this paper, we design channel buffers and router crossbars to improve the performance (latency, throughput) while reducing the power consumption. In addition, we implement the proposed channel buffers and crossbar organizations in a concentrated torus (CTorus) topology which is a dual network without the additional area overhead. We compare other dual networks with leading topologies such as mesh2X, concentrated mesh2X (CMesh2X), and flattened butterfly2X (FBfly2X), each implemented with channel buffers. Our proposed designs analyze the power-performance-area tradeoff in designing channel buffers for NoC architectures while alleviating HoL blocking through buffer organizations and crossbar optimizations. Results using Synopsys design compiler showed that the buffer and crossbar organizations for an 8 × 8 mesh architecture can reduce power consumption by 25%-40%, improve throughput and reduce latency by 525%, while occupying 4%-13% more area when compared to the baseline architecture for both synthetic as well as real benchmark traces such as Princeton Application Repository for Shared-Memory Computers (PARSEC) and Standard Performance Evaluation Corporation (SPEC). CPU2006. When the energy-efficient buffer and crossbar organization was inserted into our CTorus topology, we further reduced energy dissipation by 32% and area by 53%, on average, over mesh2X, CMesh2X, and FBfly2X.

CNoC: High-Radix Clos Network-on-Chip

Many high-radix network-on-chip (NoC) topologies have been proposed to improve network performance with an ever-growing number of processing elements (PEs) on a chip. We believe high-radix Clos network-on-chip (CNoC) is the most promising with its low average hop counts and good load-balancing characteristics. In this paper, we propose: 1) a high-radix router architecture with virtual output queue (VOQ) buffer structure and packet mode dual round-robin matching (PDRRM) scheduling algorithm to achieve high speed and high throughput in CNoC; 2) the design of hierarchical round-robin arbiter for high-radix high-speed NoC routers; and 3) a heuristic floor-planning algorithm to minimize the power consumption caused by the long wires. Experimental results show that the throughput of a 64-node three-stage CNoC under uniform traffic increases from 62% to 78% by replacing the baseline virtual channel routers with PDRRM VOQ routers. We also compared the delay, power, and area performance of the 64-node CNoC with other NoC topologies under various synthetic traffic patterns and SPLASH-2 benchmark traces. The simulation results show that in general CNoC improves the throughput, low-load delay, and energy efficiency over the compared NoC topologies.

Power Delivery Design for 3-D ICs Using Different Through-Silicon Via (TSV) Technologies

3-D integrated circuits promise high bandwidth, low latency, low device power, and a small form factor. Increased device density and asymmetrical packaging, however, renders the design of 3-D power delivery a challenge. We investigate in this paper various methods to improve 3-D power delivery. We analyze the impact of through-silicon via (TSV) size and spacing, of controlled collapse chip connection (C4) spacing, and of dedicated power delivery TSVs. In addition to considering typical cylindrical or square metal-filled TSVs (core TSVs), we also investigate using coaxial TSVs for power delivery resulting in reduced routing blockages and added coupling capacitance. Our 3-D evaluation system is composed of a quad-core chip multiprocessor, a memory die, and an accelerator engine, and it is evaluated using representative SPEC benchmark traces. This is the first detailed architectural-level analysis for 3-D power delivery. Our findings provide clear guidelines for 3-D power delivery design. More importantly, we show that it is possible to achieve 2-D-like, or even better, power quality by increasing C4 granularity and by selecting suitable TSV size and spacing.

Post-processing in wireless sensor networks: Benchmarking sensor trace files for in-network data aggregation

Wireless sensor network research usually focuses on the reliable and efficient collection of data. In this paper we target on the next step in the lifetime of traces: we aim at investigating and evaluating, by qualitative and quantitative means, data repositories of already collected measurements. Concerning the collected datasets, several important topics arise like the need of exchanging traces between researchers using a common representation of the traces and the need for common classification of the traces based on a commonly agreed set of statistical characteristics for in retrospect utilization. In order to qualitatively address these issues, we propose the use of a novel set of metrics focusing on the in-network data-aggregation problem class. These metrics enable reliable evaluation of algorithms using the same benchmark traces (both in average cases and “stressful” setups) removing the need for running algorithms in a real testbed, at least in the initial development stage. We present the results of our research as a first approach for addressing this problem, and in order to confirm our method, we characterized several traces with the proposed metrics. We validate the metrics by predicting the performance of three data-aggregation schemes using the available traces and checking the results by actually running the algorithms.

NON-UNIFORM "FAT-MESHES" FOR CHIP MULTIPROCESSORS

This paper studies the traffic hot spots of mesh networks in the context of chip multiprocessors. To mitigate these effects, this paper describes a non-uniform fat-mesh extension to mesh networks, which are popular for chip multiprocessors. The fat-mesh is inspired by the fat-tree and dedicates additional links for connections with heavy traffic (e.g. near the center) with fewer links for lighter traffic (e.g. near the periphery). Two fat-mesh schemes are studied based on the traffic requirements of chip multiprocessors using dimensional ordered XY routing and a randomized XY-YX routing algorithms, respectively. Analytical fat-mesh models are constructed by theoretically presenting the expressions for the traffic requirements of personalized all-to-all traffic for both the raw message numbers and their normalized equivalents. We demonstrate how traffic scales for a traditional mesh compared to a non-uniform fat mesh. Simulation results demonstrate that using same number of physical links the non-uniform fat-mesh can achieve better performance than a uniform fat-mesh mesh using both synthetic traffic patterns and splash-2 benchmark traces.

Express virtual channels

Due to wire delay scalability and bandwidth limitations inherent in shared buses and dedicated links, packet-switched on-chip interconnection networks are fast emerging as the pervasive communication fabric to connect different processing elements in many-core chips. However, current state-of-the-art packet-switched networks rely on complex routers which increases the communication overhead and energy consumption as compared to the ideal interconnection fabric. In this paper, we try to close the gap between the state-of-the-art packet-switched network and the ideal interconnect by proposing express virtual channels (EVCs), a novel flow control mechanism which allows packets to virtually bypass intermediate routers along their path in a completely non-speculative fashion, thereby lowering the energy/delay towards that of a dedicated wire while simultaneously approaching ideal throughput with a practical design suitable for on-chip networks. Our evaluation results using a detailed cycle-accurate simulator on a range of synthetic traffic and SPLASH benchmark traces show upto 84% reduction in packet latency and upto 23% improvement in throughput while reducing the average router energy consumption by upto 38% over an existing state-of-the-art packet-switched design. When compared to the ideal interconnect, EVCs add just two cycles to the no-load latency, and are within 14% of the ideal throughput. Moreover, we show that the proposed design incurs a minimal hardware overhead while exhibiting excellent scalability with increasing network sizes.

Efficient phase-type fitting with aggregated traffic traces

Approximating the empirical distribution of a measured data trace by a phase-type (PH) distribution has significant applications in the analysis of stochastic models. For phase-type fitting, a large number of different methods and tools exist. One drawback of all these methods is that the fitting effort strongly depends on the size of the data trace to be fitted. Since large data traces are necessary to capture rare events, which have a strong impact on system performance, current fitting procedures are very time consuming. In this paper, we introduce a method to generate an aggregated trace from the original trace, and we show how to effectively use the aggregated trace within a PH fitting approach, called G-FIT. In particular, we show that elements of a large traffic trace can be aggregated to a smaller number of 50–200 weighted elements, while fitting accuracy remains the same compared to the case of fitting the original trace. As a result, CPU time requirements for fitting PH distributions can be decreased by about four orders of magnitude, such that traces with ten million elements can be accurately fitted in a few seconds. The effectiveness of the proposed method is demonstrated on a set of benchmark traces and two real traffic traces as well as quantitative results from queuing analysis.

A Novel Approach for Phase-Type Fitting with the EM Algorithm

The representation of general distributions or measured data by phase-type distributions is an important and nontrivial task in analytical modeling. Although a large number of different methods for fitting parameters of phase-type distributions to data traces exist, many approaches lack efficiency and numerical stability. In this paper, a novel approach is presented that fits a restricted class of phase-type distributions, namely, mixtures of Erlang distributions, to trace data. For the parameter fitting, an algorithm of the expectation maximization type is developed. This paper shows that these choices result in a very efficient and numerically stable approach which yields phase-type approximations for a wide range of data traces that are as good or better than approximations computed with other less efficient and less stable fitting methods. To illustrate the effectiveness of the proposed fitting algorithm, we present comparative results for our approach and two other methods using six benchmark traces and two real traffic traces as well as quantitative results from queuing analysis

Performance of the KORA-2 cache replacement scheme

In this paper, we propose a new strategy (KORA-2) for the replacement of lines in cache memories. The algorithm is efficient and easily implementable. It is basically an extension of our previous work presented in [1]-[5]. Key to our algorithm is to identify and discard inactive lines relatively quickly as opposed to the conventional replacement algorithms. Trace-driven simulations were performed for 42 different cache configurations using benchmark programs from SPEC92 (Standard performance Evaluation Corporation) benchmark suites. Simulation results illustrate that our algorithm can provide a peak value of approximately 8.71% improvement in the miss ratio over the best performing conventional algorithm (LRU) for the selected benchmark trace files generated from SPEC programs. This translates to a savings of hundreds of thousands of misses for typical programs referencing well over 100 million addresses.

The unconventional replacement algorithms

This work proposes several new schemes for the replacement of cache lines/blocks in high performance computer systems. Our algorithms rely on judiciously chosen neural networks for accurate real-time statistical predictions. These algorithms, therefore, provide better cache performance as compared to the conventional LRU (Least Recently Used) algorithm. Simulation results indicate that the proposed set of replacement strategies can provide a performance improvement of as much as 16.4711% over the LRU algorithm for our selected benchmark trace files. The results are based on an experimentation involving 6 neural network paradigms and 21 different cache configurations. Excellent performance of the neural network-based replacement strategies means that this new approach can be studied as an alternative to the existing page replacement and prefetching algorithms in virtual memory systems.