BCH Decoder Research Articles

Efficient Decoding of LDM Core Layer at Fixed Receivers in ATSC 3.0

In order to decode an enhanced layer (EL) signal for a layered-division multiplexing (LDM) system at fixed receivers in ATSC 3.0, low-density parity-check (LDPC)/BCH decoding and successive interference cancellation should be performed to eliminate the core layer (CL) signal. For a high signal-to-noise ratio environment and sufficient low injection level of the EL signal, the CL bit-interleaved coded modulation decoder can easily achieve quasi error free for the whole LDPC codeword. However, for high injection levels, there may be still many erroneous bits in the parity part even after LDPC/BCH decoding since the ATSC 3.0 LDPC codes have the characteristic of unequal error protection due to the unequal weight distributions in their parity-check matrices. Therefore, ATSC 3.0 receivers should include re-encoding module for CL LDPC codes to completely recover the CL signal for LDM system. In this paper, we propose an efficient method to reconstruct CL signal in ATSC 3.0 LDM systems, which can be realized by a modified re-encoding after LDPC decoding of the CL signal. It significantly reduces the computational complexity and worst case latency without any loss of coding performance.

Adaptive Multi-path BCH Decoder to Alleviate Hotspot-induced DRAM Bit Error Variation in 3D Heterogeneous Processor

Adaptive Multi-path BCH Decoder to Alleviate Hotspot-induced DRAM Bit Error Variation in 3D Heterogeneous Processor

Low-Complexity Non-Iterative Soft-Decision BCH Decoder Architecture for WBAN Applications

This paper presents a low-complexity non-iterative soft-decision Bose-Chaudhuri-Hocquenghem (SD-BCH) decoder architecture and design technique for wireless body area networks (WBANs). A SDBCH decoder with test syndrome computation, a syndrome calculator, Chien search and metric check, and error location decision is proposed. The proposed SD-BCH decoder not only uses test syndromes, but also does not have an iteration process. The proposed SD-BCH decoder provides a 0.75~1 ㏈ coding gain compared to a hard-decision BCH (HD-BCH) decoder, and almost similar coding gain compared to a conventional SD-BCH decoder. The proposed SD-BCH (63, 51) decoder was designed and implemented using 90-㎚ CMOS standard cell technology. Synthesis results show that the proposed non-iterative SD-BCH decoder using a serial structure can lead to a 75% reduction in hardware complexity and a clock speed 3.8 times faster than a conventional SD-BCH decoder.

On the GF(p) linear complexity of Hall’s sextic sequences and some cyclotomic-set-based sequences

Klapper (1994) showed that there exists a class of geometric sequences with the maximal possible linear complexity when considered as sequences over GF(2), but these sequences have very low linear complexities when considered as sequences over GF(p) (p is an odd prime). This linear complexity of a binary sequence when considered as a sequence over GF(p) is called GF(p) complexity. This indicates that the binary sequences with high GF(2) linear complexities are inadequate for security in the practical application, while, their GF(p) linear complexities are also equally important, even when the only concern is with attacks using the Berlekamp-Massey algorithm [Massey, J. L., Shift-register synthesis and bch decoding, IEEE Transactions on Information Theory, 15(1), 1969, 122–127]. From this perspective, in this paper the authors study the GF(p) linear complexity of Hall’s sextic residue sequences and some known cyclotomic-set-based sequences.

MLC 낸드 플래시 메모리 오류정정을 위한 고속 병렬 BCH 복호기 설계

MLC 낸드 플래시 메모리 오류정정을 위한 고속 병렬 BCH 복호기 설계

센서네트워크 활용을 위한 경량 병렬 BCH 디코더 설계

Abstract This paper presents a new byte-wise BCH (4122, 4096, 2) decoder, which treats byte-wise parallel operations so as to enhance itsthroughput. In particular, we evaluate the parallel processing technique for the most time-consuming components such as syndrome gen-erator and Chien search owing to the iterative operations. Even though a syndrome generator is based on the conventional LFSR archi-tecture, it allows eight consecutive bit inputs in parallel and it treats them in a cycle. Thus, it can reduce the number of cycles that areneeded. In addition, a Chien search eliminates the redundant operations to reduce the hardware complexity. The proposed BCH decoderis implemented with VHDL and it is verified using a Xilinx FPGA. From the simulation results, the proposed BCH decoder can enha ncethe throughput as 43% and it can reduce the hardware complexity as 67% compared to its counterpart employing parallel processingarchitecture.Keywords: BCH code, Parallel BCH decoder, Syndrome generator, Chien search

A Single and Adjacent Symbol Error-Correcting Parallel Decoder for Reed–Solomon Codes

This paper presents a novel high-speed Reed–Solomon (RS) decoder. The proposed decoder corrects in parallel adjacent and single-symbol errors; moreover, it serially corrects multiple-symbol errors other than adjacent errors. Its operation is based on a novel scheme that extends an existing binary BCH decoder such that a nonbinary RS code can be targeted. The proposed scheme, however, differs from previous schemes in the algorithm and construction of the parallel decoder; the proposed decoder is efficient for multilevel memory systems such as those utilizing phase change memory devices. Simulation results show that the proposed scheme requires a significantly smaller area and lower power than a traditional fully parallelized RS decoder capable of correcting any double-symbol errors in parallel. Furthermore, it is also shown that it requires a smaller area than a parallel error correction scheme using a nonbinary double-error-correcting orthogonal Latin square code.

Before convergence early stopping criterion for inner LDPC code in DVB standards

This letter presents a before convergence early stopping criterion for the LDPC decoder defined in the second generation of DVB standards. The idea is to stop the decoding process once the estimated number of remaining errors is below the maximum capacity correction of the outer BCH decoder used in the DVB-S2, T2 and C2 standards. Simulations show that the average number of iterations is reduced by up to 26% compared with classical early stopping criterion up to a frame error rate of 10^-6.

Design of a Fault Tolerant Digital Communication System, by means of RBF Networks.Comparison Simulations with the Encoding and Decoding Algorithms BCH (7,4,1)

This paper presents the design of a BCH encoder (7,4,1) and BCH decoder (7,4,1) with Radial Basis Neural Network as error correction technique for fault tolerant systems, applied in digital communications. The neural network model is exported to Matlab Simulink to test different scenarios, to achieve results equivalent to those described by the BCH algorithm, in an empirical and scalar way.

A 5.4 <formula formulatype="inline"><tex Notation="TeX">$\mu{\rm W}$</tex></formula> Soft-Decision BCH Decoder for Wireless Body Area Networks

This paper presents an IEEE 802.15.6 compliant soft-decision BCH decoder for energy-constrained wireless body area networks. The proposed soft-decision decoder (SDD) provides a 1 dB coding gain compared to the hard-decision decoder (HDD). The improvement in BER performance can translate into power savings at the transmitter. The energy dissipation and area of the soft-decision BCH decoder is minimized by jointly considering the algorithm, architecture, and circuit parameters. An early termination strategy is proposed to reduce the number of redundant test patterns. Probabilistic sorting is proposed to determine the test patterns, and its hardware complexity is only 54.7% of the conventional sorting method. The HDD kernel is implemented by adopting the Peterson rule, reducing the area by 44.2%. A pass-transistor logic based Chien search circuit consumes 33.3% less energy compared to the standard-cell based implementation. The chip is designed to operate at the minimum energy point of 0.29 V, yielding an energy reduction of 94% compared to a direct-mapped SDD at SNR=5 dB. Fabricated in 90 nm CMOS, the chip dissipates 5.4 μW at 500 kHz, achieving a throughput of 6.38 Mbps.

Hardware Implementation of (63, 51) Bch Encoder and Decoder for Wban Using LFSR and BMA

Error Correcting Codes are required to have a reliable communication through a medium that has an unacceptable bit error rate and low signal to noise ratio. In IEEE 802.15.6 2.4GHz Wireless Body Area Network (WBAN), data gets corrupted during the transmission and reception due to noises and interferences. Ultra low power operation is crucial to prolong the life of implantable devices. Hence simple block codes like BCH (63, 51, 2) can be employed in the transceiver design of 802.15.6 Narrowband PHY. In this paper, implementation of BCH (63, 51, t = 2) Encoder and Decoder using VHDL is discussed. The incoming 51 bits are encoded into 63 bit code word using (63, 51) BCH encoder. It can detect and correct up to 2 random errors. The design of an encoder is implemented using Linear Feed Back Shift Register (LFSR) for polynomial division and the decoder design is based on syndrome calculator, inversion-less Berlekamp-Massey algorithm (BMA) and Chien search algorithm. Synthesis and simulation were carried out using Xilinx ISE 14.2 and ModelSim 10.1c. The codes are implemented over Virtex 4 FPGA device and tested on DN8000K10PCIE Logic Emulation Board. To the best of our knowledge, it is the first time an implementation of (63, 51) BCH encoder and decoder carried out.

A Single-Bit and Double-Adjacent Error Correcting Parallel Decoder for Multiple-Bit Error Correcting BCH Codes

This paper presents a novel high-speed BCH decoder that corrects double-adjacent and single-bit errors in parallel and serially corrects multiple-bit errors other than double-adjacent errors. Its operation is based on extending an existing parallel BCH decoder that can only correct single-bit errors and serially corrects double-adjacent errors at low speed. The proposed decoder is constructed by a novel design and is suitable for nanoscale memory systems, in which multiple-bit errors occur at a probability comparable to single-bit errors and double-adjacent errors occur at a higher probability (nearly two orders of magnitude) than other multiple-bit errors. Extensive simulation results are reported. Compared with the existing scheme, the area and delay time of the proposed decoder are on average 11% and 6% higher, but its power consumption is reduced by 9% on average. This paper also shows that the area, delay, and power overheads incurred by the proposed scheme are significantly lower than traditional fully parallelized BCH decoders capable of correcting any double-bit errors in parallel.

High-Throughput and Low-Complexity BCH Decoding Architecture for Solid-State Drives

This paper presents a high-throughput and low-complexity BCH decoder for NAND flash memory applications, which is developed to achieve a high data rate demanded in the recent serial interface standards. To reduce the decoding latency, a data sequence read from a flash memory channel is re-encoded by using the encoder that is idle at that time. In addition, several optimizing methods are proposed to relax the hardware complexity of a massive-parallel BCH decoder and increase the operating frequency. In a 130-nm CMOS process, a (8640, 8192, 32) BCH decoder designed as a prototype provides a decoding throughput of 6.4 Gb/s while occupying an area of 0.85 mm2.

FPGA IMPLEMENTATION OF (15,7) BCH ENCODER AND DECODER FOR TEXT MESSAGE

In a communication channel, noise and interferences are the two main sources of errors occur during th e transmission of the message. Thus, to get the error free communication error con trol codes are used. This paper discusses, FPGA imp lementation of (15, 7) BCH Encoder and Decoder for text message using Verilog Hardware Description Language. Initially each chara cter in a text message is converted into binary data of 7 bits. These 7 bits are encoded into 15 bit codeword using (15, 7) BCH encoder. If any 2 bit error in any position of 15 bit codeword, is detected and co rrected. This corrected data is converted back into an ASCII character. The decoder is implemented using the Peterson algorithm and Chine’s search algorithm. Simulation was carri ed out by using Xilinx 12.1 ISE simulator, and verified results for an arbitrar ily chosen message data. Synthesis was successfully done by using the RTL compiler, power and area is estimated for 180nm Technology. F inally both encoder and decoder design is implement ed on Spartan 3E FPGA.

Design and FPGA implementation of parallel high-efficiency BCH decoder

Design and FPGA implementation of parallel high-efficiency BCH decoder

Construction and decoding of BCH codes over chain of commutative rings

Abstract In this paper, we present a new construction and decoding of BCH codes over certain rings. Thus, for a nonnegative integer t, let A 0 ⊂ A 1 ⊂ ⋯ ⊂ A t − 1 ⊂ A t be a chain of unitary commutative rings, where each A i is constructed by the direct product of appropriate Galois rings, and its projection to the fields is K 0 ⊂ K 1 ⊂ ⋯ ⊂ K t − 1 ⊂ K t (another chain of unitary commutative rings), where each K i is made by the direct product of corresponding residue fields of given Galois rings. Also, A i ∗ and K i ∗ are the groups of units of A i and K i , respectively. This correspondence presents a construction technique of generator polynomials of the sequence of Bose, Chaudhuri, and Hocquenghem (BCH) codes possessing entries from A i ∗ and K i ∗ for each i, where 0 ≤ i ≤ t. By the construction of BCH codes, we are confined to get the best code rate and error correction capability; however, the proposed contribution offers a choice to opt a worthy BCH code concerning code rate and error correction capability. In the second phase, we extend the modified Berlekamp-Massey algorithm for the above chains of unitary commutative local rings in such a way that the error will be corrected of the sequences of codewords from the sequences of BCH codes at once. This process is not much different than the original one, but it deals a sequence of codewords from the sequence of codes over the chain of Galois rings.

High-speed and parallel approach for decoding of binary BCH codes with application to Flash memory devices

In this article, we propose a high-speed decoding algorithm for binary BCH codes that can correct up to 7 bits in error. Evaluation of the error-locator polynomial is the most complicated and time-consuming step in the decoding of a BCH code. We have derived equations for specifying the coefficients of the error-locator polynomial, which can form the basis for the development of a parallel architecture for the decoder. This approach has the advantage that all the coefficients of the error locator polynomial are computed in parallel (in one step). The roots of error-locator polynomial can be obtained by Chien's search and inverting these roots gives the error locations. This algorithm can be employed in any application where high-speed decoding of data encoded by a binary BCH code is required. One important application is in Flash memories where data integrity is preserved using a long, high-rate binary BCH code. We have synthesized generator polynomials for binary BCH codes (error-correcting capability, s) that can be employed in Flash memory devices to improve the integrity of information storage. The proposed decoding algorithm can be used as an efficient, high-speed decoder in this important application.

Implementation of the Chien search algorithm on a baseband processor

In this paper, we discuss the implementation of the BCH decoder Chien search algorithm on a SIMD style programmable baseband processor with minimum memory footprint and processing time degradation. Due to the emergence of long BCH codes, the computational efficiency of the Chien search algorithm becomes a major implementation issue for BCH decoders. We minimize the memory usage and processing time of the BCH decoders by deriving a computation rule, which is used to efficiently generate the power terms of primitive elements upon the SIMD datapath, instead of storing all pre-computed terms in the memory.

Implementation of 10-Gb/s Parallel BCH Decoder Based on Virtex-5 FPGA

This paper presents a design of 10Gb/s BCH decoder which is compatible with the protocol of G.975 and can be applied in optical fiber communication. The main blocks of this decoder include syndrome calculator, key-equation solver, Chien search and error correction. In order to achieve high speed, 8-bit parallel syndrome calculator and Chien search block are adopted. By sharing the key-equation solver, the numb er of key-equation solver is reduced and the hardware resources are saved. This decoder has been implemented in Virtex-5 FPGA and the verification results show that the decoder can work properly under the clock of 166MHz and the data rate can be up to 10Gb/s.

40nm CMOS 0.35V-Optimized Standard Cell Libraries for Ultra-Low Power Applications

Ultra-low voltage is now a well-known solution for energy constrained applications designed using nanometric process technologies. This work is focused on setting up an automated methodology to enable the design of ultra-low voltage digital circuits exclusively using standard EDA tools. To achieve this goal, a 0.35V energy-delay optimized library was developed. This library, fully compliant with standard library design flow and characterization, was verified through the design and fabrication of a BCH decoder circuit, following a standard front-end to back-end flow. At 0.33V, it performs at 600 kHz with a dynamic energy consumption reduced by a factor 14x from nominal 1.1V. Based on this design, experiments, and preliminary silicon results, two additional libraries were developed in order to enhance future ultra-low voltage circuit performance.