Baud Rate Generator Research Articles

Universal Asyncronous Receiver Transmitter

Abstract: This project focuses on the Verilog-based design and implementation of a Universal Asynchronous ReceiverTransmitter (UART) communication module. The UART is a fundamental component in digital systems, facilitating serial data transmission between devices. Our objective is to develop a robust and efficient Verilog description of the UART module, emphasizing simplicity, modularity, and ease of integration. The baud rate generator allows for flexible communication speeds, accommodating diverse applications. The module ensures accurate framing of transmitted and received data through the proper generation of start and stop bits. Error-detection mechanisms are implemented to enhance data integrity. The project enhances the digital design field by delivering a Verilog implementation of a UART communication module that is both dependable and efficient.

Design, refinement, and enhancement of FPGA-implemented UART circuitry

This article provides an overview of the universal asynchronous receiver/transmitter, commonly referred to as Universal Asynchronous Receiver/Transmitter (UART). The UART stands as a noteworthy exemplar of a serial communication protocol, facilitating the exchange of data within a serial connection while accommodating full-duplex communication. The architecture of the UART hinges upon three principal constituents: the transmitter, the receiver, and the baud rate generator, the latter essentially a frequency divider. Each of these elements is meticulously crafted using the Verilog hardware description language, thereby ensuring distinct and efficient design. Furthermore, this discourse delves into refined iterations of these implementations. For instance, it introduces the concept of a baud rate self-adaptive function and expounds upon multibyte transmission techniques. In a concerted effort to streamline circuit design and curtail the electro circuit's footprint, a deliberate decision is made to forgo the integration of a parity check module. Consequently, the chosen data format is the widely adopted 8N1 (8 data bits, 1 stop bit and no parity bit) configuration.

Design and Implementation of Power-Efficient FSM based UART

The remarkable innovations in technology are driven mainly by the high-speed data communication requirements of the modern generation. The Universal Asynchronous Receiver Transmitter (UART) is one of the most sought-after communication protocols. This work mainly focuses on implementing and analysing the UART for data communication. The Finite State Machine (FSM) implements the baud rate generator, transmitter, and receiver modules. Cadence NCSIM was utilized for simulation, and Cadence RTL Compiler was used during synthesis using the 45 nm and 90 nm General Process Design Kit (GPDK) library files. The baud rate of 9600 bps and 50 MHz clock frequency was used to design UART. The increased speed and complexity of the VLSI chip designs has resulted in a significant increase in power consumption. The comparative analysis of power and delay for different clock periods shows an improvement in the total power and the Power Delay Product (PDP) with increasing clock periods. Better results were observed using 45 nm in comparison to the 90 nm library.

Design and Verification of UART using System Verilog

The main objective of this paper is to design and verify a full duplex UART module using System Verilog (SV). It is a serial communication protocol which provides communication between the systems without using clock signal. It converts parallel data into serial format and transmits the same. Once the data in serial format is received it is converted into parallel format. Designing of UART includes designing of baud rate generator, receiver, transmitter, interrupt and FIFO modules. Verification involves verifying the design by creating verification environment which allows to reuse the testbench and reduces the code complexity. Randomization is used to check the corner conditions which are hard to reach. 100% assertion and 100% functional coverage is achieved. UART operation is simulated using Questasim software.

Fault Test Equipment of Launcher Control System Based on Embedded System

The fault test equipment of mine launcher system is developed. This equipment is divided into two functional parts: master controller, an industrial processing computer and corresponding application software, which mainly engages in human-machine interactions, controlling the testing process, diagnosing the fault as well as display the output, and slave controller that performs data acquisition, signal conditioning, connection and transformation. Its hardware is composed of main control circuit with two complex programmable logic device (CPLD) chips, signal conditioning circuit, serial interface module and dedicated interface adapter unit. In addition, the application software of master controller is modular and object-oriented and developed by LabWIEW. The slave controller software is developed in VHDL that performs sampling and configuration of firing control and configuration signals. And the software consists of the five key modules: baud rate generator, enable module, pulse signal count module, data acquisition module of high level signals and communication module. Thus the equipment actually provides effective technical method in improving the repair and support skills for the mine launcher control system.

Implementation and Application between High Stability PC and FPGA Serial Communication

In this paper, we mainly introduce the serial communication between PC and FPGA and adopt the design principles of DDS phase accumulator to achieve small error of baud rate generator and provide the reliable data transmission. On PC, we use the Labview software to design control interface, which is responsible for sending the control command. The experimental results indicate that the communication is feasible, high stability. This design is applied to the control unit of waveform generator based on FPGA by inputting relevant data on PC such as waveform selection, frequency control, range control and phase control to realize the function of waveform selection, amplitude modulation, phase modulation and frequency modulation.