Design and Verification of UART using System Verilog

Yamini R,Mtech Student, Electronics And Communication Department, Jssstu, Mysuru, Karnataka, India ,Ramya M V,Assistant Professor, Electronics And Communication Department, Jssstu, Mysuru, Karnataka, India

doi:10.35940/ijeat.e1135.069520

Yamini R, Mtech Student, Electronics And Communication Department, Jssstu, Mysuru, Karnataka, India + Show 2 more

Open Access

https://doi.org/10.35940/ijeat.e1135.069520

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Abstract

The main objective of this paper is to design and verify a full duplex UART module using System Verilog (SV). It is a serial communication protocol which provides communication between the systems without using clock signal. It converts parallel data into serial format and transmits the same. Once the data in serial format is received it is converted into parallel format. Designing of UART includes designing of baud rate generator, receiver, transmitter, interrupt and FIFO modules. Verification involves verifying the design by creating verification environment which allows to reuse the testbench and reduces the code complexity. Randomization is used to check the corner conditions which are hard to reach. 100% assertion and 100% functional coverage is achieved. UART operation is simulated using Questasim software.

Highlights

Universal Asynchronous Receiver Transmitter – UART is a universal serial communication protocol that transmits data serially between systems
UART receives data in parallel format converts it into serial data in transmitter section and sends it to the receiver
Data stored in sequence is randmozied in sequencer and is driven to Design Under Test (DUT)

Summary

Introduction

Universal Asynchronous Receiver Transmitter – UART is a universal serial communication protocol that transmits data serially between systems. It is a computer hardware or a built in IC in microcontroller to control computer interface. UART can be used for both transmission and reception. Clock is not required for data transmission as it is asynchronous communication. The data format and transmission speed can be configured, the name Universal Asynchronous Receiver Transmitter. Most of the peripherals uses parallel data format for communication. UART receives data in parallel format converts it into serial data in transmitter section and sends it to the receiver. Receiver should convert the serial data to parallel format before sending it to the peripheral devices. SV is extended version of Verilog which includes more features than Verilog and reduces code complexity

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