Battery-operated Mobile Devices Research Articles

On-chip static and dynamic monitors for low power applications

Due to the increasing demand for battery-operated mobile devices in the market, low power consumption inside the chip is an essential ingredient during the chip design. Static and dynamic monitors are needed to achieve low power in modern chips. The static or process monitor provides information about global and local process variation inside the chip. The dynamic or in situ monitor provides information about the global, local, and environmental variation on the critical path of the design inside the chip. In this work, a static monitor is discussed using a reconfigurable ring oscillator which extracts the threshold voltage information. A dynamic monitor using warning flip-flop is discussed which can be used for dynamic voltage and frequency scaling to achieve low power consumption. Both static and dynamic monitors are experimentally validated in a test chip, that is implemented in CMOS 130 nm technology node.

LEoNIDS: A Low-Latency and Energy-Efficient Network-Level Intrusion Detection System

Over the past decade, design and implementation of low-power systems has received significant attention. While it started with data centers and battery-operated mobile devices, it has recently branched to core network devices such as routers. However, this emerging need for low-power system design has not been studied for security systems, which are becoming increasingly important today. Toward this direction, we aim to reduce the power consumption of network-level intrusion detection systems (NIDS), which are used to improve the secure operation of modern computer networks. Unfortunately, traditional approaches to low-power system design, such as frequency scaling, lead to a disproportionate increase in packet processing and queuing times. In this paper, we show that this increase has a negative impact on the detection latency and impedes a timely reaction. To address this issue, we present a low-latency and energy-efficient NIDS (LEoNIDS): an architecture that resolves the energy-latency tradeoff by providing both low power consumption and low detection latency at the same time. The key idea is to identify the packets that are more likely to carry an attack and give them higher priority so as to achieve low attack detection latency. Our results indicate that LEoNIDS consumes power comparable to a state-of-the-art low-power design, while, at the same time, achieving up to an order of magnitude faster attack detection.

A middleware framework for application-aware and user-specific energy optimization in smart mobile devices

Mobile battery-operated devices are becoming an essential instrument for business, communication, and social interaction. In addition to the demand for an acceptable level of performance and a comprehensive set of features, users often desire extended battery lifetime. In fact, limited battery lifetime is one of the biggest obstacles facing the current utility and future growth of increasingly sophisticated “smart” mobile devices. This paper proposes a novel application-aware and user-interaction aware energy optimization middleware framework (AURA) for pervasive mobile devices. AURA optimizes CPU and screen backlight energy consumption while maintaining a minimum acceptable level of performance. The proposed framework employs a novel Bayesian application classifier and management strategies based on Markov Decision Processes and Q-Learning to achieve energy savings. Real-world user evaluation studies on Google Android based HTC Dream and Google Nexus One smartphones running the AURA framework demonstrate promising results, with up to 29% energy savings compared to the baseline device manager, and up to 5×savings over prior work on CPU and backlight energy co-optimization.

Revisiting QRS Detection Methodologies for Portable, Wearable, Battery-Operated, and Wireless ECG Systems

Cardiovascular diseases are the number one cause of death worldwide. Currently, portable battery-operated systems such as mobile phones with wireless ECG sensors have the potential to be used in continuous cardiac function assessment that can be easily integrated into daily life. These portable point-of-care diagnostic systems can therefore help unveil and treat cardiovascular diseases. The basis for ECG analysis is a robust detection of the prominent QRS complex, as well as other ECG signal characteristics. However, it is not clear from the literature which ECG analysis algorithms are suited for an implementation on a mobile device. We investigate current QRS detection algorithms based on three assessment criteria: 1) robustness to noise, 2) parameter choice, and 3) numerical efficiency, in order to target a universal fast-robust detector. Furthermore, existing QRS detection algorithms may provide an acceptable solution only on small segments of ECG signals, within a certain amplitude range, or amid particular types of arrhythmia and/or noise. These issues are discussed in the context of a comparison with the most conventional algorithms, followed by future recommendations for developing reliable QRS detection schemes suitable for implementation on battery-operated mobile devices.

The low power architecture approach towards exascale computing

Abstract Energy efficiency is a first-order concern when deploying any computer system. From battery-operated mobile devices, to data centers and supercomputers, energy consumption limits the performance that can be offered. We are exploring an alternative to current supercomputers that builds on low power mobile processors. We present initial results from our prototype system based on ARM Cortex-A9, which achieves 120 MFLOPS/W, and discuss the possibilities to increase its energy efficiency.

Toward energy-efficient error control in 3G broadcast video

Energy use is a key issue in battery-operated mobile devices. In order to extend battery life, mobiles showing video often allow a controlled drop in quality, which is tolerable when the shortcomings of a small screen are combined with the imperfections of visual perception. Both energy consumption and video quality are affected by the Reed-Solomon codes and interleaving levels used in 3G video broadcast services. We explore the effect of these elements of MAC-layer error control, and show how they can be manipulated to save energy while maintaining acceptable video quality through a controlled reduction in the number of parity symbols in the Reed-Solomon code and the level of interleaving.

Reduced Complexity FSD Algorithm for MIMO Detection

Detection is a major challenge for the utilization of multiple-input multiple-output (MIMO) system. Even the fixed sphere decoding (FSD), which is known for its simplicity in calculation, requests too much computation in high order modulation and large number antenna system especially for mobile battery-operated devices. In this paper, a reduced FSD algorithm is proposed to simplify the calculation complexity of the FSD while maintaining the performance at the same time. Simulation results in a 4×4, 16-QAM system show that up to 89% calculation can be saved while the performance drop is less than 0.1dB when SNR=24.

Reduced complexity FSD algorithm based on noise variance

multiple-input multiple-output (MIMO) system has very high spectrum efficiency. However, detection is a major challenge for the utilization of MIMO system. But even the fixed sphere decoding (FSD), which is known for its simplicity in calculation, requests too much computation in high order modulation and large number antenna system, especially for mobile battery-operated devices. In this paper, a reduced FSD algorithm is proposed to simplify the calculation complexity of the FSD while maintaining the performance at the same time. Simulation results show the effect of the proposed algorithm. Especially the results in a 4×4 64QAM system show that up to 81.2% calculation can be saved while the performance drop is less than 0.1dB when SNR=30.

Architectural Optimizations for Low-Power $K$-Best MIMO Decoders

Maximum-likelihood (ML) detection for higher order multiple-input-multiple-output (MIMO) systems faces a major challenge in computational complexity. This limits the practicality of these systems from an implementation point of view, particularly for mobile battery-operated devices. In this paper, we propose a modified approach for MIMO detection, which takes advantage of the quadratic-amplitude modulation (QAM) constellation structure to accelerate the detection procedure. This approach achieves low-power operation by extending the minimum number of paths and reducing the number of required computations for each path extension, which results in an order-of-magnitude reduction in computations in comparison with existing algorithms. This paper also describes the very-large-scale integration (VLSI) design of the low-power path metric computation unit. The approach is applied to a 4times4, 64-QAM MIMO detector system. Results show negligible performance degradation compared with conventional algorithms while reducing the complexity by more than 50%.

CMOS tuners for mobile TV

Digital video reception is emerging as the latest feature toward multimedia-enriched handheld devices. Mobile battery-operated devices require small-size tuners that consume low power and are amenable to single-chip integration with the baseband demodulator. Following an overview of the system and circuit-level implementation challenges of mobile TV standards such as DVB-H and T-DMB, this article presents a dual-band direct conversion tuner for DVB-H. Architecture and circuit trade-offs are discussed, and detailed measurements are presented. The tuner occupies 9.7 mm2 and achieves a 4 dB NF at both UHF and L-band, eliminating the need for an external LNA. By using a fractional-TV synthesizer both 470-890 MHz and 1.4-1.8 GHz bands are supported, while achieving an integrated phase noise of less than -41 dBc. Sixth-order low-pass filters support channel bandwidths from 4 to 10 MHz

Quality and Power Efficient Architecture for the Discrete Cosine Transform

In recent years, the demand for multimedia mobile battery-operated devices has created a need for low power implementation of video compression. Many compression standards require the discrete cosine transform (DCT) function to perform image/video compression. For this reason, low power DCT design has become more and more important in today's image/video processing. This paper presents a new power-efficient Hybrid DCT architecture which combines Loeffler DCT and binDCT in terms of special property on luminance and chrominance difference. We use Synopsys PrimePower to estimate the power consumption in a TSMC 0.25-μm technology. Besides, we also adopt a novel quality assessment method based on structural distortion measurement to measure the quality instead of peak signal to noise rations (PSNR) and mean squared error (MSE). It is concluded that our Hybrid DCT offers similar quality performance to the Loeffler, and leads to 25% power consumption and 27% chip area savings.

Compiler-directed high-level energy estimation and optimization

The demand for high-performance architectures and powerful battery-operated mobile devices has accentuated the need for power optimization. While many power-oriented hardware optimization techniques have been proposed and incorporated in current systems, the increasingly critical power constraints have made it essential to look for software-level optimizations as well. The compiler can play a pivotal role in addressing the power constraints of a system as it wields a significant influence on the application's runtime behavior. This paper presents a novel Energy-Aware Compilation (EAC) framework that estimates and optimizes energy consumption of a given code, taking as input the architectural and technological parameters, energy models, and energy/performance/code size constraints. The framework has been validated using a cycle-accurate architectural-level energy simulator and found to be within 6% error margin while providing significant estimation speedup. The estimation speed of EAC is the key to the number of optimization alternatives that can be explored within a reasonable compilation time. As shown in this paper, EAC allows compiler writers and system designers to investigate power-performance tradeoffs of traditional compiler optimizations and to develop energy-conscious high-level code transformations.

Performance-directed energy management for storage systems

Energy consumption has become an important issue in the design of battery-operated mobile devices and sophisticated data centers. The storage hierarchy, which includes memory and disks, is a major energy consumer in such systems; especially for high-end servers at data centers. Much work has focused on energy control algorithms for storage systems that transition a device into a low power mode when a certain usage function exceeds a specified threshold. These algorithms are difficult to use in real systems, however, because designers must painstakingly and manually tune threshold values, and even then a performance guarantee is difficult. To address these limitations, we develop three algorithms: 1) a performance guarantee technique that designers can use with any underlying energy-control algorithm 2) a performance-directed control algorithm that periodically assigns a static configuration to different devices by solving an optimization problem 3) another performance-directed control algorithm that dynamically self-tunes according to an optimal set of thresholds

Partitioned instruction cache architecture for energy efficiency

The demand for high-performance architectures and powerful battery-operated mobile devices has accentuated the need for low-power systems. In many media and embedded applications, the memory system can consume more than 50% of the overall system energy, making it a ripe candidate for optimization. To address this increasingly important problem, this article studies energy-efficient cache architectures in the memory hierarchy that can have a significant impact on the overall system energy consumption.Existing cache optimization approaches have looked at partitioning the caches at the circuit level and enabling/disabling these cache partitions (subbanks) at the architectural level for both performance and energy. In contrast, this article focuses on partitioning the cache resources architecturally for energy and energy-delay optimizations. Specifically, we investigate ways of splitting the cache into several smaller units, each of which is a cache by itself (called a subcache ). Subcache architectures not only reduce the per-access energy costs, but can potentially improve the locality behavior as well.The proposed subcache architecture employs a page-based placement strategy, a dynamic page remapping policy, and a subcache prediction policy in order to improve the memory system energy behavior, especially on-chip cache energy. Using applications from the SPECjvm98 and SPEC CPU2000 benchmarks, the proposed subcache architecture is shown to be very effective in improving both the energy and energy-delay metrics. It is more beneficial in larger caches as well.

Active capacitor multiplier in Miller-compensated circuits

A technique is presented whereby the compensating capacitor of an internally compensated linear regulator, Miller-compensated two-stage amplifier, is effectively multiplied. Increasing the capacitance with a current-mode multiplier allows the circuit to occupy less silicon area and to more effectively drive capacitive loads. Reducing physical area requirements while producing the same or perhaps better performance is especially useful in complex systems where most, if not all, functions are integrated onto a single integrated circuit. Die area in such systems is a luxury. The increasing demand for mobile battery-operated devices is a driving force toward higher integration. The enhanced Miller-compensation technique developed in this paper helps enable higher integration while being readily applicable to any process technology, be it CMOS, bipolar, or BiCMOS. Furthermore, the technique applies, in general, to amplifier circuits in feedback configuration. Experimentally, the integrated linear regulator (fabricated in a 1-/spl mu/m BiCMOS process technology) proved to be stable for a wide variety of loading conditions: load currents of up to 200 mA, equivalent series resistance of up to 3 /spl Omega/, and load capacitors ranging from 1.5 nF to 20 /spl mu/E The total quiescent current flowing through the regulator was less than 30 /spl mu/A during zero load-current conditions.