Hole Barrier Height Research Articles

String-level compact modeling of erase operations in the body-floated vertical channel of 3D charge trapping flash memory

In this study, we examined the use of string-level compact modeling as an effective framework for circuit simulation focusing on erase operation in 3D charge trapping flash (CTF) memory devices. We analyzed the behaviors of the accumulated hole from p-type bulk (p-well) and the corresponding difference of channel electrostatic potential in the CTF cell string, which is attributed to the variation in hole barrier height in the channel of the ground select line (GSL) transistor during erase operation. We derived a formula for the hole current delivering positive potential from the p-well to the channel region and established a modeling procedure. Technology computer-aided design (TCAD) simulation results were used to extract model parameters and analyze channel electrostatic potential during the erase operation. Additionally, experimental data for erase speed were verified using simulation program with integrated circuit emphasis (SPICE) results. Because the erase efficiency is strongly related to hole behaviors based on the conditions of the GSL transistor, the proposed compact modeling is an effective tool for circuit designers and system architects to achieve better performance in erase execution and optimizing the design of 3D CTF memory devices.

(Invited) Electron Transport in Nanocarbon Networks for Energy Conversion and Storage Applications

Carbon nanostructures have attracted great attention in recent years as novel electrode materials in batteries with increased capacity and conductivity as well as enhanced material stability. In these nanostructures, nanocarbons such as carbon nanotubes and graphene nanoplatelets are interconnected to construct their three-dimensional networks around the host materials for Li deposition. This work focuses on the study of electron transport phenomena in these nanocarbon networks with two model material systems: (1) single-walled carbon nanotube (SWCNT) networks co-embedded with silica microparticles (Fig. (a)), and (2) free-standing three-dimensional graphene (3DG) structures with polymeric surface modifications (Fig. (b)). We characterize the materials for electrical conductivity and thermopower with varying material contents in the composites to reveal several key factors determining their energy-dependent carrier transport characteristics. It is found that in these three-dimensional nanocarbon networks, carrier tunneling at the junctions between nanocarbons along with the network morphology predominantly determines the transport properties. Simultaneous increase in electrical conductivity and thermopower is achieved for SWCNT networks co-embedded with silica microparticles by increasing silica content up to 40 w.t.% at a fixed CNT content. The enhanced electron transport is attributed to the reduced junction distances due to the intimate network formation on the surface of silica particles with a polymer binder. Our transport theory based on the Landauer formalism for junction tunneling reveals that the junction modification with polymer can alter the potential barrier heights for both electrons and holes at the junction to significantly change the transport properties of the composite. Doping of nanocarbons is also investigated for their impacts on the junction transport and the geometric factor of the networks. Finally, we also investigate the use of these carbon nanostructures in solid-state thermoelectric (TE) energy harvesters and ionic TE capacitors to harvest thermal energy from temperature gradients and fluctuations. Figure 1

Understanding the Electronic Transport of Al-Si and Al-Ge Nanojunctions by Exploiting Temperature-Dependent Bias Spectroscopy.

Understanding the electronic transport of metal-semiconductor heterojunctions is of utmost importance for a wide range of emerging nanoelectronic devices like adaptive transistors, biosensors, and quantum devices. Here, we provide a comparison and in-depth discussion of the investigated Schottky heterojunction devices based on Si and Ge nanowires contacted with pure single-crystal Al. Key for the fabrication of these devices is the selective solid-state metal-semiconductor exchange of Si and Ge nanowires into Al, delivering void-free, single-crystal Al contacts with flat Schottky junctions, distinct from the bulk counterparts. Thereof, a systematic comparison of the temperature-dependent charge carrier injection and transport in Si and Ge by means of current-bias spectroscopy is visualized by 2D colormaps. Thus, it reveals important insights into the operation mechanisms and regimes that cannot be exploited by conventional single-sweep output and transfer characteristics. Importantly, it was found that the Al-Si system shows symmetric effective Schottky barrier (SB) heights for holes and electrons, whereas the Al-Ge system reveals a highly transparent contact for holes due to Fermi level pinning close to the valence band with charge carrier injection saturation due to a thinned effective SB. Moreover, thermionic field emission limits the overall electron conduction, indicating a distinct SB for electrons.

Modeling polarization effects on internal quantum efficiency of micro-LEDs at low current density

This study investigates the optoelectronic properties of blue micro-light-emitting diodes (µ-LEDs) by modeling the semipolar single quantum well (QW) at low current density. Through simulation analyses, the influences of the eight selected crystal orientations and different QW thicknesses on the internal quantum efficiency (IQE) and forward voltage are investigated for low current density LEDs. The simulation results of the energy band diagram show that reversed polarization increases the band tilt in the same direction as the built-in electric field, resulting in IQE poorer than that of LEDs whose polarization is of the same magnitude but positive. However, reversed polarization also reduces the hole barrier height, resulting in lower forward voltage at the same current density. Finally, it is found that weakly positive-polarized (101̄2) LEDs have the highest IQE and maximum allowed thickness at low current density, which is due to the flat energy band with a reduced band tilt caused by weakly positive polarization.

Simultaneously improved hole injection and current uniformity in 293 nm AlGaN-based deep ultraviolet light-emitting diodes

Insufficient hole injection and current nonuniformity caused by the nature of the p-AlGaN hole injection layer (HIL) are two issues impeding the advances in the optical and electrical properties of AlGaN-based deep ultraviolet light-emitting diodes (DUV LEDs). To simultaneously improve the hole injection efficiency and current uniformity, an Al-linearly-decreasing AlGaN PN junction (ALD AlGaN PN junction) is proposed to replace the conventional p-AlGaN HIL with a constant Al component. The barrier height for holes at the interface between the p-type electron blocking layer (p-EBL) and HIL as well as the hole concentration and resistance in the p-AlGaN HIL can be modulated at the same time by the proposed ALD AlGaN PN junction. As a result, the hole injection efficiency is enhanced due to the reduced barrier height at the p-EBL/HIL interface and the polarization-induced three-dimensional hole gas (3DHG) induced in the proposed ALD AlGaN PN junction HIL. In addition, the lateral current uniformity is improved by the properly regulated resistance in the p-AlGaN HIL, which can be ascribed to the additional barrier for holes in the valence band because of the incorporated ALD AlGaN PN junction. The proposed DUV LED with ALD AlGaN PN junction exhibits enhanced EQE by a factor of 39.2% at 100 A/cm2 and simultaneously improved current uniformity in the active region. This designed ALD AlGaN PN junction structure provides a promising strategy for achieving high-performance DUV LEDs.

Grain boundary passivation via balancing feedback of hole barrier modulation in HfO2-x for nanoscale flexible electronics

Flexible electronics has attracted considerable attention owing to its enormous potential for practical applications in various fields. However, the massive strain produced during bending degrades the device. Especially at grain boundaries, due to the accumulation of defects, this degradation is exacerbated in flexible electronic devices. The importance of electrically inactivated grain boundaries increases as devices scale down to the nanoscale. Here, we propose an HfO2-x thin film that can be used as an excellent material for flexible electronics with versatile functionality, especially for grain boundary passivation. Various electrical phases of HfO2-x thin films with conducting to insulating behavior, which originates from oxygen deficiency, have been fabricated on flexible substrates. Furthermore, owing to the most stable charge state of oxygen vacancies, oxygen-deficient HfO2-x shows p-type conductivity. Current mapping by conductive atomic force microscopy reveals that current flow is hindered at grain boundaries due to the formation of potential barriers. This phenomenon is also observed in bent flexible thin films on convex and concave molds, leading to tensile and compressive strains, respectively. Although the defect concentration increases because of lattice deformation during bending, more holes are trapped at the grain boundaries, resulting in an increased hole barrier height. We believe that grain boundary passivation through hole barrier modulation during bending would pave the way for advances in hafnia-based nanoscale flexible electronics.

Alleviated built-in electric field in the active region of AlGaN deep-ultraviolet light-emitting diodes with locally embedded p-i-n junctions.

The strong polarization-induced electric field in the multi-quantum well region reduces the radiative recombination rates by separating the electron and hole wave functions, which is one of the most detrimental factors that is to blame for the low luminous efficiency of AlGaN deep-ultraviolet light-emitting diodes (DUV LEDs). In this work, we redesigned the active region by incorporating Si and Mg doping at the vicinity of the quantum wells, forming a series of embedded p-i-n junctions in the multi-quantum well region. The additional electric field induced by the fixed charges from the embedded doping-induced junctions can effectively compensate for the intrinsic polarization-induced electric fields in the quantum well region and give rise to the improved overlap of hole and electron wave function, hence enhancing the radiative recombination rates and the external quantum efficiency and optical power of DUV LEDs. The mechanism behind the alleviated polarization electric field is comprehensively discussed and analyzed. The embedded p-i-n junctions can also alter the band diagram structure of the active region, decrease the effective barrier heights for holes, and diminish the electron leakage into the p-type region. In addition, different thicknesses and doping concentrations of the embedded p- and n- layers were designed, and their influence on the performance of DUV LEDs was numerically analyzed. The proposed structure with embedded p-i-n junctions provides an alternative way to achieve efficient DUV LEDs.

Numerical Investigation of Charge Packet Dynamics in Polyethylene Assuming Barrier Height-Electric Field Hysteresis Hypothesis

Charge packet phenomenon is a sign of the impending breakdown of the dielectric materials. In order to discuss the formation mechanism of charge packets, space charge characteriscs in polyethylene under the electric field of 150kV/mm are simulated based on the bipolar transport model assuming hysteresis in the barrier height for holes. It is found that if hysteresis in the barrier height is not introduced, net charge densities in the vicinity of the electrodes increase with the increase of polarization time. However, charge packets could not be reproduced without hysteresis hypothesis. When hysteresis loop in the barrier height are incorporated, charge packets are generated and propagated with the velocity about 3μm/s. The dying away of charge packets is not observed, which disagrees with the experimental data.

Quantum barriers with a polarization self-screening effect for GaN-based VCSELs to increase the electron-hole stimulated recombination and output performance

Hole injection is one of the fundamental limitations that affect the lasing power for GaN-based vertical-cavity surface-emitting lasers (VCSELs). In this report, a GaN-based VCSEL with a composition gradient quantum barrier (CGQB) structure is proposed and investigated. The designed InxGa1-xN quantum barrier has a linear gradient level of InN composition along the [0001] orientation, which is effective in reducing the energy band barrier height for holes. Furthermore, the polarization-induced bulk charges that are generated in the proposed quantum barriers can reduce the electric field magnitude in quantum wells, which is known as the polarization self-screening effect. Therefore, the hole injection and the electron-hole stimulated recombination rate can be both enhanced. We also find that although the hole injection can be enhanced and the polarization induced electric field in the quantum wells can be reduced, an increased gradient level of the InN composition for the polarization self-screened quantum barriers is not always favored. The reduced quantum barrier height will redistribute the energy subbands and make peak gain not coupled with the cavity resonance wavelength, which will decrease the lasing power. Hence, to avoid the substantial variation of the subbands, we suggest that the polarization self-screened active region shall possess properly thick quantum wells for maximizing the lasing power. Moreover, the optimized active region design can increase the 3dB frequency.

Degradation mechanism of Schottky P-GaN gate stack in GaN power devices under neutron irradiation

In this Letter, the degradation mechanism of Schottky p-type GaN (P-GaN) gate stack in GaN power devices under neutron irradiation is studied. After 1-MeV neutron irradiation at fluences of 6 × 1013 and 1 × 1014 neutron/cm2, device threshold voltage VTH is positively shifted and gate leakage current is increased, which indicates the degradation of Schottky P-GaN gate stack. By analyzing the gate current with Frenkel–Poole emission model, barrier height of Schottky P-GaN gate stack is reduced due to the traps induced by neutron irradiation. By employing capacitance–voltage (C–V) and pulse current–voltage (I–V) measurements, we find that the electron and hole traps induced by displacement damages dominate the degradation of gate characteristics after neutron irradiation. Electron traps at EC- (0.38–0.55) eV and hole traps at EV+ (0.56–0.62) eV with a density of 1011–1012 cm−2 eV−1 are shown in irradiated devices. Ionizations of VGa and Gai induced by neutron radiation as well as their interaction with dislocations significantly alter the energy band of P-GaN/AlGaN/GaN heterostructure gate stack. The trapping and de-trapping processes of VGa-related electron traps lead to positive shifts in VTH. Passivation of dislocations by Gai effectively lowers the barrier height for holes and increases the gate leakage current. Measures to improve the quality of P-GaN/AlGaN/GaN heterostructure or raise the potential barrier height can be taken to make the device more resistant to neutron radiation. This work depicts the physical process and mechanism of degradations in Schottky P-GaN gate stack, which can provide deeper insights into the analysis and field application of GaN power devices under neutron irradiation.

Sheet Charge Engineering Towards an Efficient Hole Injection in 290 nm Deep Ultraviolet Light-Emitting Diodes

The hole injection efficiency is one of the bottlenecks that restrict the external quantum efficiency (EQE) and optical power of AlGaN-based deep ultraviolet light-emitting diodes (DUV LEDs). The polarization-induced positive sheet charges at the last quantum barrier (LQB)/electron blocking layer (EBL) interface reflect the holes back to the p-type layer and weaken the hole injection capability into the active region. In this work, we designed and incorporated a polarization-engineered Al_xGa_1-xN/Al_yGa_1-yN superlattice layer at the LQB/EBL interface. The positive sheet charges at the LQB/EBL interface can be inverted into negative charges with optimal Al compositions in the Al_xGa_1-xN/Al_yGa_1-yN superlattice layer. The electron confinement and hole injection efficiency can also be improved through increasing the effective barrier height for electrons and decreasing the effective barrier height for holes, resulting in an enhanced optical power by 29.4% and alleviated efficiency droop by 78.4% for the proposed device with an Al_0.67Ga_0.33N/Al_0.7Ga_0.3N superlattice insertion layer. The sheet charge engineering method by polarization provides an alternative approach to boost the hole injection efficiency towards an enhanced device performance for DUV LEDs.

X‐ray photoelectron spectroscopy characterization of band offsets of MgO/Mg2Si and SiO2/Mg2Si heterojunctions

MgO and SiO2 are the natural oxide layer on the surface of Mg2Si and the excellent gate dielectric layer materials. MgO/Mg2Si and SiO2/Mg2Si heterojunctions were successfully prepared by magnetron sputtering. The valence band offset (VBO) and conduction band offset (CBO) of the two heterojunctions were measured by X‐ray photoelectron spectroscopy (XPS) method, and the values were 2.64 and 3.90 eV for MgO/Mg2Si and 3.24 and 4.43 eV for SiO2/Mg2Si, respectively. Different degree of band bending occurs on the two interfaces. As a result, the band diagrams of the both interfaces are all Type‐I (Straddled) band alignment. Such high VBO and CBO can provide suitable barrier heights for both electrons and holes (>1 eV); therefore, both MgO and SiO2 can be suitable candidates for the preparation of Mg2Si‐based thin film transistors.

High‐Performance van der Waals Metal‐Insulator‐Semiconductor Photodetector Optimized with Valence Band Matching

AbstractThe vertical metal‐insulator‐semiconductor (MIS) photodetectors based on van der Waals heterostructures (vdWHs), fabricated by rationally stacking different layers without the limit of lattice‐match, have attracted broad interest due to their wide wavelength monitoring range, high responsivity, high detectivity, and fast response. Here, for the first time, the control of barrier height in vdWHs MIS photodetectors is systematically investigated. Optimizing semiconducting and insulating layers enables lowering the hole barrier height to achieve a high performance of the device. Graphene/hexagonal boron nitride (h‐BN)/SnS2 device shows the best photodetection performance compared to the other common 2D semiconductors. The lowest barrier height ensures that the photo‐induced holes transfer efficiently to the graphene electrode and the dark current is highly suppressed by the h‐BN layers. Consequently, the graphene/h‐BN/SnS2 MIS photodetectors have a high photoresponsivity of 2 A W−1, a high detectivity of 1013 Jones, and a photocurrent/dark current ratio of 5.2 × 105 at a low applied bias of −0.6 V. The highest detectivity reaches 9.6 × 1013 Jones which is 100–1000 times greater than previously reported vdWHs MIS photodetectors.

Reduction of efficiency droop by inserting superlattice quaternary-ternary electron blocking layer in GaN-based light-emitting diodes

We report a reduced the unwanted hole blocking of the electron blocking layer (EBL) by replacing the conventional EBL with a quaternary-ternary superlattice electron blocking layer. The effective barrier height for holes is reduced from ~ 348 meV to ~ 261 meV, thus, improving the concentration of holes by ~ 50% with respect to LED with conventional EBL. Similarly, the radiative recombination rate is also improved by ~ 79%. As a result, the overall droop ratio of internal quantum efficiency (IQE) of the proposed LED is reduced to ~ 23% at 100 A/cm2 in comparison to conventional LED.

(Invited) Schottky Barrier Height Control at Metal/Ge Interface by Insertion of Nitrogen Contained Amorphous Layer

1. IntroductionGe is attracted great attention as a candidate of channel material for future CMOS devices and near-infrared optical devices, owing to its high intrinsic carrier mobility and narrow bandgap. One of the difficulties to realize Ge-based devices is to control of Schottky barrier height (SBH) at metal/Ge interface. It is widely known any metal/Ge contact shows high electron barrier height (ΦBN > 0.5 eV) due to Fermi level pinning at metal/Ge interface. Our group found a method to alleviate the FLP, by which sputter-deposited TiN/Ge and ZrN/Ge contacts showed low ΦBN (< 0.10 eV) and high hole barrier height (ΦBP > 0.56 eV) [1]. From detailed structural analyses, it was clarified that the FLP alleviation was induced by a nitrogen-contained amorphous interlayer (a-IL) formed during TiN(ZrN) sputter-deposition. If we can change the kind of metal on a-IL, we may extend the control range of SBH. In this paper, we demonstrate the wide range SBH control for metal/a-IL/Ge contacts.2. Experimental, Results, and DiscussionsFigure 1 shows the fabrication procedure of the metal/a-IL/Ge structure. An a-IL was formed by the ZrN film sputter deposition and subsequent etching by dilute HF solution. Ag, Al, and Cu, were respectively deposited using thermal evaporation and patterned by the removal of photoresist. In figure 1, a dark field-STEM image of an Ag/a-IL/Ge contact is shown. An a-IL with dark contrast was clearly observed between the Ag and the Ge, implying that the ZrN film can be removed by a dilute HF solution while the a-IL can be retained on the Ge substrate.Figures 2 shows J–V characteristics at 200 K for Cu/a-IL/n-Ge contacts, respectively. Here, higher rf power during the ZrN deposition makes thicker a-IL. It was found that the insertion of the a-IL significantly modulated the J–V characteristics. The rectifying feature on n-Ge becomes weak with an increase in rf power. Other metals also show a similar tendency (data are not shown).Figure 3 represents the ΦBN versus work function of the metal (ΦM) plot. In this figure, slope factor (S) and effective charge neutrally level (ΦCNL,eff) are also indicated for each rf power. The weaker rf power leads to the larger S value. Interestingly, a S for contacts with a rf power of 50 W was around 0.26, which is close to S (0.27) of Si [2], suggesting that it is possible to widely control the SBH by forming contacts with N-contained a-IL.It is well known that the ΦCNL of metal/Ge interface is located near the E V edge, as shown in Fig. 4(a) [3]. To explain the dependences of S andΦCNL,eff in this study, two effects should be considered, which are the decrease in the intrinsic states and the creation of additional extrinsic states. We consider the decrease in the intrinsic states is dominated by the passivation of surface dangling bonds by a-IL. On the other hand, the creation of additional localized extrinsic states are associated with the interface dipoles related Ge-N bond [4], i.e., the extrinsic states cause a shift of ΦCNL to compensate the positively charged dipoles at the Ge side of the interface, causing the decrease in ΦCNL,eff. When the rf power was as low as 50 W (thin a-IL), the density of extrinsic states was low, as shown in Fig. 4(b). Therefore, the Fermi level can be modulated depending on the ΦM, as shown in Fig. 3 (50 W, blue line). In the case of a thick a-IL (rf power of 200 W), high-density extrinsic states could be generated. As a result, the modulation of ΦM became impossible, as shown in Fig. 4 (200 W, black line).3. ConclusionIn conclusion, we succeeded in wide controlling SBH of metal/Ge contacts with N-contained a-ILs. The SBH swing and CNL position were strongly depend on the rf power during ZrN sputter deposition, i.e., the thickness of a-IL. Under the low power condition, a S-value of 0.26 was achieved, which is comparable to that of Si. The dependences of S and ΦCNL on the rf power were explained by an extrinsic states model associated with N-related interfacial dipoles.

Probing the metal/conducting polymer interface and implications of the metal diffusion in two-terminal sandwich devices

In this article, we have investigated the role of polymer regio-regularity and film fabrication technique in reducing metal diffusion from top electrodes in sandwich type devices. Poly(3-hexyl thiophene)(P3HT) polymer of varying regio-regularity was chosen for investigation and its corresponding thin films were fabricated by spin-coating(SC) and floating film transfer method(FTM). Sandwich devices with a top interface between gold and i) FTM coated regio-regular (rr) P3HT, ii) FTM coated non-regiocontrolled (nr) P3HT, iii) SC nr-P3HT and iv) SC rr-P3HT were fabricated. The current density vs voltage (J-V) characteristics of the devices revealed non-ohmic characteristics. Estimation of interfacial hole barrier heights using Fowler Nordheim tunneling model revealed a small barrier of 1.12 eV for the isotropic spin-coated nr-P3HT film which increased to 1.37 eV with an increase in film anisotropy for the FTM nr-P3HT film. The barrier height also gradually declined from 1.37 eV to 1.05 eV with increase in regioregularity from FTM nr-P3HT to FTM rr-P3HT. These observations were confirmed through optical and structural characterizations along with depth profiling of metal diffusion using XPS. Pronounced Au diffusion to a higher depth was observed in the XPS results for the highly anisotropic FTM film that decreased subsequently with decrease in anisotropy from FTM to spin-coated film. It was thus deduced that a judicious selection of fabrication technique and polymer aids in reducing metal diffusion leading to improved device performance. The results hold crucial significance towards the fabrication of efficient organic photodetectors that have a sandwich type device architecture.

(Invited) Schottky Barrier Height Control at Metal/Ge Interface by Insertion of Nitrogen Contained Amorphous Layer

Ge is attracted great attention as a candidate of channel material for future CMOS devices and near-infrared optical devices, owing to its high intrinsic carrier mobility and narrow bandgap. One of the difficulties to realize Ge-based devices is to control of Schottky barrier height (SBH) at metal/Ge interface. It is widely known any metal/Ge contact shows high electron barrier height (ΦBN > 0.5 eV) due to Fermi level pinning at metal/Ge interface. Our group found a method to alleviate the FLP, by which sputter-deposited ZrN/Ge contacts showed low ΦBN (< 0.10 eV) and high hole barrier height (ΦBP > 0.56 eV). From detailed structural analyses, FLP alleviation was induced by a nitrogen-contained amorphous interlayer (a-IL) formed during ZrN sputter-deposition. If we can change the kind of metal on a-IL, we may extend the control range of SBH. In this paper, we demonstrate the wide range SBH control for metal/a-IL/Ge contacts.

Step-type quantum wells with slightly varied InN composition for GaN-based yellow micro light-emitting diodes.

In this work, we propose adopting step-type quantum wells to improve the external quantum efficiency for GaN-based yellow micro light-emitting diodes. The step-type quantum well is separated into two parts with slightly different InN compositions. The proposed quantum well structure can partially reduce the polarization mismatch between quantum barriers and quantum wells, which increases the overlap for electron and hole wave functions without affecting the emission wavelength. Another advantage is that the slightly decreased InN composition in the quantum well helps to decrease the valence band barrier height for holes. For this reason, the hole injection capability is improved. More importantly, we also find that step-type quantum wells can make holes spread less to the mesa edges, thus suppressing the surface nonradiative recombination and decreasing the leakage current.

Sn Doping Effects in Solid-Phase Crystallized Ge Thin-Film Transistors

Introduction Low-temperature synthesis of high carrier mobility thin films on insulating substrates is actively being conducted to dramatically improve the device performance of thin-film transistors (TFTs). Ge is one of the candidates for next-generation TFTs because of its high carrier mobility and good compatibility with Si. We recently reported that the densification of amorphous (a-) Ge precursor in solid-phase crystallization (SPC) significantly enlarged the grain size of polycrystalline (poly-) Ge and improved Hall effect hole mobility μ Hall [1]. The TFT using this Ge layer exhibited both high field effect mobility μ FE (170 cm2/Vs) and on/off current ratio I on/I off (~102) without minimizing the channel region (< 1 μm) [2]. The key technology was thinning the 100 nm thick Ge film with a large grain size (3.7 μm) enough to fully deplete the channel. Very recently, we further improved μ Hall by combining the precursor densification method with Sn incorporation in SPC [3,4]. In this study, we fabricate TFT using SPC-GeSn and further improve its performance. Experimental Procedure The a-Ge1−x Sn x (0 ≤ x ≤ 4.5%) precursors were deposited on SiO2 glass substrates using the Knudsen cell of a molecular beam deposition system (base pressure of 5 × 10−7 Pa). The deposition rate of Ge was fixed at 1.0 nm/min at room temperature, whereas that of Sn was adjusted to obtain the targeted GeSn composition. The deposition time was 100 min. The precursors were densified by heating the substrate at 125 °C during deposition [1,3,4]. The samples were then loaded into a conventional tube furnace in an N2 atmosphere annealed at 450 °C for 5 h to induce SPC. The grown layers were analyzed by the electron backscattering diffraction (EBSD) measurement and Hall effect measurement (van der Pauw method).We fabricated accumulation-mode metal source/drain (S/D) p-channel TFTs using SPC-GeSn. Pt and TiN were sequentially formed as a metal S/D and a capping layer, respectively. The PtGe/Ge contacts have low hole barrier height and are suitable for p-channel Ge-TFTs. We used Al/SiO2/Al2O3/SiO2/GeO2 for the gate stack with the equivalent oxide thickness of 17.7 nm. The channel width and length (W/L) were 55 and 5–10 μm, respectively. Here, all process including SPC were conducted below 450 °C. Results and Discussion First, we discuss the crystalline quality and electrical properties of the SPC-GeSn layer. Figure 1(a) shows that the crystal grain size dramatically varies with initial Sn concentration x and maximized at x = 1.6%. These results are roughly consistent with the solid solubility of Sn in Ge of approximately 1%–2%. We thinned x = 1.6% sample with the maximum grain size using chemical-mechanical polishing (CMP) to fabricate TFT for full depletion in poly-GeSn layer. As a reference, we also thinned x = 0% sample. Figure 1(b) shows that hole concentration p is constant in-depth direction although hole mobility μ Hall decreases by thinning. The Sn doping in Ge provides lower p.Finally, we discuss the TFT characteristics fabricated on the thinned SPC samples (55 nm for Ge and 50 nm for GeSn). Figure 2(a) shows that the typical p-channel transistor operation, i.e., drain current I D increases with increasing gate voltage V G. Figure 2(b) shows Sn doping reduces the off current I off significantly under keeping the on current I on. This reflects the electrical properties of the GeSn film obtained by the Hall effect measurement (Fig.1 (b)). Figure 3 summarizes the relationship between μ FE and I on/I off for different channel length (L = 5, 10, and 15 μm) in the same substrate. The experimental data show a clear increase in variability as the channel length decreases, which is in good agreement with the trends of poly-Si-TFTs. This is the first result showing such variability reflecting grain boundary at poly-Ge and GeSn. Furthermore, Sn doping improves I on/I off by roughly an order of magnitude although μ FE is almost identical. These results thus demonstrate the usefulness of Sn doping of polycrystalline Ge in TFT application. The current TFT performance will be further improved by the optimization of Sn concentration, film thickness, and channel dimensions (W/L). Reference [1] K. Toko, K. Moto et al., Sci. Rep. 7, 16981 (2017).[2] K. Moto et al., Appl. Phys. Lett. 114, 212107 (2019).[3] K. Moto et al., Sci. Rep. 8, 14832 (2018).[4] K. Moto et al., Appl. Phys. Lett. 114, 112110 (2019). Figure 1

Understanding the Charge Transport Mechanism in MoS2 Transistors with Graphene Electrodes

Two-dimensional transition-metal dichalcogenides (TMDs) have emerged as promising candidates for next-generation electronics owing to their excellent semiconducting properties. However, metal-TMDs junctions are of particular interest as they have become a major limiting factors to further improvements in TMD-based device performance. Here, we investigate the charge transport of MoS2 transistors contacted with Ti/Au and graphene electrodes. Compared to a conventional Ti/Au contact, the MoS2 devices with graphene electrodes exhibit improved electrical properties (field-effect mobility, subthreshold swing, and low off-state current). Such a device improvement could be attributed to efficient electron injection arising from the tunable graphene Fermi level as well as the high hole barrier height, which significantly reduces the off-state current caused by hole transport. Furthermore, a simple Schottky barrier model has been employed to explain the observed transfer characteristic of MoS2 transistors with two different contacts. Our finding provides significant insights into the understanding of charge transport in TMD-based transistors for future 2D electronics.