Capacitor Voltage Balancing Research Articles

A level enhanced voltage balancing method for modular multilevel converter without using sensors

SummaryThe intrinsic characteristics such as modular structure, filterless operation, and absence of DC‐link capacitor have made the modular multilevel converter (MMC) superior to the conventional multilevel converters. However, the submodule (SM) capacitor voltage balancing is crucial. This paper presents a voltage balance control method for MMC. The proposed method generates 2N + 1 levels (where N is the number of SMs per arm) which halves the step size of output voltage and improves the harmonic performance as compared to N + 1 level generation. It requires only one carrier per phase and no voltage and current measurements are needed for the implementation. Therefore, the proposed method makes the system cost‐effective and reduces the implementation issues related with carrier‐based methods substantially. It also alleviates the non‐uniform charge distribution problem with the phase disposition pulse width modulation (PDPWM) technique. Further, a detailed mathematical analysis is presented which enhances the understanding of balancing algorithm. In addition to this, the circulating current with 2N + 1 modulation is analyzed and a control technique is presented. The proposed voltage balancing method is simulated comprehensively in MATLAB/SIMULINK software and validated by the experimental results obtained from a laboratory prototype.

An improved four‐layer capacitor voltage control strategy combined with arm current control for transformerless modular multilevel converters

AbstractIn order to improve the performance of the transformerless modular multilevel converters (MMC) under AC and DC grid fault conditions, this paper proposes an improved four‐layer capacitor voltage control strategy combined with arm current control. The proposed control strategy consists of overall submodule capacitor voltage averaging control, leg‐balancing control with flexible weight factor W, arm‐balancing control with zero‐sequence suppression, and inner‐arm individual balancing control. The new concept of weight factor W for leg‐balancing control is also originated, considering negative‐sequence current and DC circulating current jointly from power point of view. The proposed approach effectively realizes the capacitor voltage balance, ac‐side current tracking, and unwanted circulating current elimination. The practical implementation of the proposed control strategy and the experimental results from a downscale three‐phase transformerless MMC prototype are presented to validate the performance of the proposed four‐layer capacitor voltage control strategy under grid faults.

An Improved DPWM Method for Single-Phase Five-Level ANPC Converters With Switching Loss Reduction and Capacitor Voltage Balance

Neutral-point (NP) voltage and flying capacitor (FC) voltage balance, and power loss reduction are important guarantees for the stable and high-efficiency operation of single-phase five-level active neutral-point clamped (5L-ANPC) converters. However, little reports about capacitor voltage balancing with the power loss reduction have been proposed for single-phase 5L-ANPC converters. In order to obtain the above merits, an improved discontinuous pulsewidth modulation (DPWM) method with capacitor voltage balance and power loss reduction is proposed. First, an optimized common-mode voltage is injected into the modulation waves to decrease the switching loss in each switching period. In particular, the calculation of the injected common-mode voltage is based on the analysis of the deviation of the NP voltage. Hence, a fast-dynamic response of the real-time NP voltage controlling is acquired in the meantime. Besides, in order to balance the FC voltage, the weight factors of NP voltage deviation and FC voltage deviation are compared to generate the selecting signals of redundant switching states. As a result, the capacitor voltage balance and power loss reduction are realized simultaneously. Finally, the simulation and experimental results validate the correctness and feasibility of the proposed DPWM method.

Capacitor voltages balancing method for buck modular DC/DC converter

The most critical problem of the modular DC-DC converter (MDCC) is the voltage balancing of the submodule (SM) capacitors, the MDCC with stepped 2-level modulation has been developed and presents a good solution, however, this type of modulation has many restrictions when there is a wide range of capacitance tolerance of the SM capacitors that results inaccurate capacitor voltages balancing. To solve this problem, this paper discusses a proposed method of capacitor voltage balancing. Compared with stepped 2-level modulation, the voltage balancing method using modified duty cycle modulation offers the merits: i) reduction in output voltage and SM capacitor voltages overshoot during dynamic operation and improvement in the time response of the system and; ii) accurate voltage balancing over wide range of capacitance tolerance of each SM capacitor; and iii) the sorting algorithm replaced with modified duty cycle modulation method for the SM capacitor voltages balancing which reduces the computation burden. The proposed method ensures a stable voltage balancing, improves the time response of the system, and decreases the voltage and current overshoot during the dynamic response compared with prior art of MDCCs, where the stepped 2-level modulation is adopted. An analytical simulation of the MDCC is presented using MATLAB/Simulink to explain the operation.

A Multilevel PFC Rectifier With Sensor-Less Voltage Balancing Capability

Most modern world appliances have an intermediate AC to DC rectifier, whether used for DC (LEDs, chargers) or applications with internal motors (refrigerator, washing machine). The conventional rectifiers distort the power factor and introduce harmonics in the grid. Multilevel rectifiers (MLR) with power factor correction (PFC) and high load handling capability have gained much research focus, and numerous topologies have been reported. However, most of them either fail to maintain the unity power factor (UPF) across the entire power range or to maintain UPF employ external circuitry and control. Further, capacitor voltage balancing is another major issue in MLR. In this regard, this brief proposes a sensor less self-balanced MLR topology that maintains UPF in all operating conditions. Experimental results have been presented for validation of the claims mentioned above of the implemented topology. A quantitative comparison with the recent literature has also been included.

A Robust Capacitor Voltage Balancing Method for CPS-PWM-Based Modular Multilevel Converters Accommodating Wide Power Range

Capacitor voltage balancing is one of the most important issues for the safe, reliable, and economical operation of the modular multilevel converter (MMC). This article proposes a modified individual capacitor voltage balancing method for MMCs with phase-shifted carrier pulsewidth modulation (PWM) (CPS-PWM) to solve the problem of the poor dynamic performance that the conventional individual voltage balancing methods suffer at low output power. In the proposed method, the information of arm current is incorporated into the balancing algorithm to cancel out the coupling effect of the output power on balancing control. Compared with conventional balancing methods, the proposed method shows better robustness against varying output power and maintains a good dynamic performance in a wider power range. The complete modeling process and parameter design are presented and considered for system stability. The effectiveness of the proposed method is verified with both MATLAB/Simulink simulation and experimental results.

A Single-Phase Switched-Capacitor Nine-Level Inverter With Reduced Capacitance

A novel nine-level switched-capacitor multilevel inverter (SCMLI) with reduced capacitance and balanced capacitor voltage is proposed in this article. Utilizing only two capacitors, the proposed SCMLI can boost the input voltage and realize nine output voltage levels under different kinds of load conditions. The controllable capacitor charging speed in the proposed SCMLI depends on the charging resonant inductor rather than the equivalent resistance of the devices in conventional topologies. The two capacitors can be charged or discharged independently by a dc source when their voltages deviate from the rated voltage. This makes the proposed SCMLI free of the capacitor voltage imbalance. The longest discharging time (LDT) of capacitors is reduced to twice the switching period, which contributes to reduced capacitance in the proposed SCMLI. With the required capacitor voltage ripple, the quality of output waveforms is also very high. A comprehensive comparison with previous SCMLIs in terms of capacitance, the voltage imbalance problem, the output voltage level, and so on is conducted to validate the merits mentioned above. The theoretical analysis, the simulation, and experiment results are accordant, confirming the feasibility of the proposed SCMLI.

A Novel Single-Stage Buck–Boost Inverter

Traditional nonisolated multilevel inverters based on the buck–boost principle usually have some disadvantage such as necessary dead time or capacitor precharging. To overcome these, a new transformerless single-stage buck–boost voltage source inverter topology and its control method are proposed. In addition, the proposed topology has greater advantages in cost and loss. In this letter, the topological characteristics and working mode of the inverter are analyzed, and a modulation scheme that can ensure the balance of the output capacitor voltage is designed. Finally, a hardware experimental prototype is built, and the proposed scheme is experimentally verified based on DSP TMS320F28335 and FPGA XC6SLX9-2TQG144C digital controller.

A Multilevel Inverter With Inherent Common Coupling Point Voltage Balancing of Stacked Capacitors Across a Single DC-Link for Induction Motor Drives

In this article, a nine-level multilevel topology is proposed by stacking of low voltage basic inverter cells and then cascading with H-bridges. The dc-link is split into four equal halves by series-connected capacitors from a common dc-link. Three common coupling points (CCPs) are formed due to the stacking of four capacitors, which are connected across the dc-link. The CCP voltage balancing is ensured by drawing or injecting zero instantaneous currents from each of these points at any instant. A six-phase symmetrical IM is used to generate equal and opposite instantaneous phase currents by applying exactly equal and opposite phase voltages for two opposite phases from the six-phase inverter. Simultaneously, the capacitor voltage balancing of H-bridge inverter cells is also achieved by proper selection of redundancies from the available pole voltage redundancies. The concept is verified with a nine-level inverter laboratory prototype, which consists of a five-level stacked inverter, and followed by two low voltage cascaded H-bridge inverters in each phase. Detailed experimental results of steady-state and transient conditions are included to validate the proposed scheme.

Cascaded Controller for Controlling DC Bus Voltage in Mismatched Input Powers

The lack of uniform production of panels in photovoltaic (PV) systems and snowball effects in fuel cell (FC) systems led us to use a separate dc–dc converter. In addition, in the PV and FC systems, the output voltage is low. Hence, dc–dc boost converters are commonly used in a series connection. Each small unit of a PV or FC operates independently. Therefore, another problem arises in the system that uses the series connection of the converter's output. Owing to the unequal electricity production of the cells, a voltage imbalance occurs at the output terminals. To create voltage balance, a modular structure grounded on a three-level boost converter was investigated. The main objective of this article is to design the control of a modular topology, allowing perfect control of the dc-bus voltage, even with mismatched input powers. The proposed control strategy ensures dynamical properties independent of the operating point, voltage balance, and robust control of the dc output voltage with respect to load perturbations. To ensure the balance of voltages and the control of currents, a sliding mode controller based on indirect synthesis was used. To control the dc–bus voltage, an energy controller is proposed that ensures dynamical performance independent of the operating conditions. The performance in terms of tracking and regulation, as well as its effect on the voltage balance of the output capacitors, was validated through simulations and experimental results. A comparison with a classical proportional integral (PI) approach for controlling the dc-bus voltage was performed.

A Switched Capacitor-Based 13-Level Inverter With Reduced Switch Count

In this article, a 13-level switched capacitor multilevel inverters (SC-MLI) based single-phase inverter is proposed in which desired levels of output ac voltage are realized with reduced number of switch counts. The proposed inverter requires 12 switches, three diodes, one input dc source, and three capacitors. The requirement of less number of switches reduces the requirement of gate drivers, which enhances power density of converter. The second challenge in SC-MLI is to maintain self-voltage balancing across the capacitors. The self-voltage balancing capability becomes poor at low values of modulation index. The capacitors connected in proposed SC-MLI are capable to maintain the self-voltage balancing without requiring auxiliary circuits or complex control strategies. The operation of capacitors is self-balanced at all regions of modulation index values. The comparison of the proposed SC-MLI is carried out with state-of-art SC-MLIs discussed in the literature using the parameters like peak inverse voltage and total standing voltage. The switches connected in the proposed 13-level SC-MLI undergoes less voltage stress as compared to the SC-MLI configurations discussed in the literature. The proposed SC-MLI is highly competent to achieve good power quality and is capable to ensure voltage balancing of capacitors even at low values of modulation index. The validation of the proposed inverter topology is carried out using a laboratory prototype. The efficiency of the converter claimed using the simulation results is observed to be 96.2% while the efficiency evaluated using the experimental results is 94.1% at 500 W.

Clamping Modulation Scheme for Low-Speed Operation of Three-Level Inverter Fed Induction Motor Drive With Reduced CMV

This article introduces a family of carrier-based pulse width modulation (PWM) schemes for three-level (3 L) inverter fed motor drive for low-speed operation. The proposed PWM in dual-inverter topology (DIT) simultaneously clamps two phases of each inverter throughout the fundamental cycle, which reduces the switching transition in the pole voltage and common-mode voltage (CMV). Four PWM variants in the family (i.e., PWM-1–PWM-4) are discussed and compared with conventional discontinuous PWM schemes. A mapping of the gating pulse is derived to extend the proposed PWM to a classical 3 L inverter fed star-connected motor drive. The gating pulses are generated using triangular carrier comparison with synchronous sampling. The steady-state and dynamic performances of PWM are validated both in DIT fed open-end winding induction motor (IM) drive and neutral point clamped (NPC) inverter fed star-connected IM drive. It is observed that the proposed PWM gives inherent capacitor voltage balance in the NPC topology. PWM-1 has a higher linear modulation range than conventional zero clamp PWM and leads to reduced CMV in the NPC topology. PWM-2 and PWM-3 give reduced CMV in DIT. PWM-4 has fault tolerance to single-phase open-switch and short-switch failure in DIT.

Switched Capacitor Based High Step-Up Multilevel Inverter with Self-Balancing Ability and Low Switching Stress

In this article, the switched capacitor (SC) based high step-up multilevel inverter is proposed with self-balancing capability. The proposed SC inverter topology is to step up the high output voltage from the very low input voltage without any bulky transformer. This proposed inverter generates single-phase AC voltage with a frequency of 50 Hz from a very low DC input voltage of 50 V with any intermediate DC-DC conversion stage. Hence, the proposed SC inverter is highly suitable for fuel cell, photovoltaic (PV) applications, and shunt active power filter (SAPF). To control the SC inverter, a multicarrier pulse width modulation (PWM) technique is engaged in the inverter. The high step-up voltage level can be achieved by the charging and discharging process of the SC. Furthermore, the stress voltage of the switches does not exceed the applied voltage and the total standing voltage of the inverter is greatly reduced without H-bridges. The comparative analysis of the proposed SC inverter is made for the components, peak inverse voltage (PIV), total standing voltage (TSV), boosting ability, and voltage balancing of capacitors. The main theme of the paper is producing a thirteen-level sinusoidal current with acceptable total harmonic distortion (THD) at different loads, low PIV, TSV, high boosting ability, and self-balancing of capacitors with fewer passive components. The whole system is examined by using MATLAB/Simulink.

Analysis of Capacitor Voltage Imbalance in Hybrid Converters and Inherently Balanced Operation Using Symmetric Architecture

This letter investigates the origin of the flying capacitor voltage imbalance in hybrid converters. An intuitive voltage–charge relationship is established to give a general explanation of the flying capacitor voltage balance in hybrid converters. The relationship is applied to devise a relatively simple and intuitive method to identify the behavior and performance difference of capacitor voltage and inductor current balancing performance in hybrid converters for <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$V_{\text{out}}&lt; \frac{V_{\text{in}}}{N}$</tex-math></inline-formula> cases. Conventional hybrid converters with an even number of inductor charging intervals are shown to be susceptible to flying capacitor voltage imbalance, while flying capacitors in hybrid converters with inductors having odd charging intervals have inherently balanced operations. As a direct result of the analysis, a new symmetric architecture and the operation of three-level buck converters are introduced to achieve an inherent balance of flying capacitor voltages, which can be applied to other flying capacitor multilevel converters. Hardware prototypes are implemented and measured for the verification of the analytical analysis and the new symmetric operation

Application of Three-Dimensional Unbalanced Coordinate Transformation to Stand-Alone Four-Leg Voltage-Source Inverter

Three-phase four-leg voltage-source inverter has been extensively investigated in recent years for its compactness, small size, and high efficiency, and it has been proved to be the best solution for providing transformer-less neutral connection to three-phase asymmetric loads. The main purpose of this article is to apply 3-D unbalanced coordinate transformation to the four-leg inverter, which supplies stand-alone asymmetric loads, to maintain the balance of the output capacitor voltages, and obtain simpler control structure and better control performance. First, a double closed-loop PI control structure can be designed based on the Clarke and Park transformations. Second, the phases and amplitudes of the capacitor voltages are locked based on the 3-D unbalanced coordinate transformation. Furthermore, the Clarke transformation oriented on the inductor currents is replaced by a 3-D unbalanced coordinate transformation, and the corresponding unbalance indices are continuously adjusted according to the unbalance indices of the capacitor voltages, so as to recover the capacitor voltages to the balanced condition. The simulation and experimental results of the whole control system for the four-leg inverter are provided in the end, so as to verify the feasibility and effectiveness of the 3-D unbalanced coordinate transformation for application to the power electronic systems.

A Flexible Reactive Power Injection Method for DC-Link Capacitors Voltage Balancing in Back-to-Back Multilevel Converters

The dc-link capacitor voltage drift is the key technical problem of the converters with multi-intermediate nodes. The back-to-back (BTB) configuration with voltage balancing control can achieve a certain operation range. Nevertheless, the challenge of voltage drift still remains, especially when both sides operate at high but different modulation indexes and high power factors. This article focuses on a BTB seven-level V-clamp multilevel converter (VMC). The balanced operation limits are presented, and the effect of the power factor on balancing capability is analyzed. To maintain the voltage balancing of the dc-link capacitor under different operation conditions of the load (inverter side), a reactive power injection control is proposed in this article. Suitable reactive power is injected into the rectifier according to the balancing situation. The proposed control method can actively adjust the power factor of the rectifier to provide the required balancing capability. In this way, the dc-link capacitor voltage balancing is maintained within a larger operation range. In this article, a 10-kVA laboratory prototype of BTB seven-level VMC is set up to verify the effectiveness of the proposed control.

Performance analysis of capacitor voltage balancing in modular multilevel converter by sorting algorithm

&lt;span lang="EN-US"&gt;Due to the modularity of modular multilevel converter (MMC), therefore it has been considered as a substitute for the diode-clamp multilevel inverter in applications of high-voltage high-power. Where it can obtain any level of voltage without imposing complexity on the control system. This study analyses in detail the operation principle and balances the capacitor voltage of sub-module (SM) in modular multilevel converter by sorting algorithm. The output voltage control and capacitor voltage balancing technique are confirmed by MATLAB/Simulink and the obtained result has been discussed, where the capacitor voltage of the sub-module has controlled within the acceptable deviation limit, which is 5-10%. In addition, the circulating current has been controlled and reduced.&lt;/span&gt;

A Multilevel Inverter for Instantaneous Voltage Balancing of Single Sourced Stacked DC-Link Capacitors for an Induction Motor Load

This article proposes a novel nine-level multilevel inverter topology with an instantaneous voltage balancing scheme of stacked dc-link capacitors for an induction motor (IM) drive application. Three neutral points (NPs, terminal joints of four series-connected capacitors) across a single dc-link are balanced instantaneously (within a sampling interval) by ensuring zero current at the NPs. The proper selection of pole voltage from the redundancies provides zero current at any NP during the pulsewidth modulation operation under a steady-state and transient operation. A five-level stacked inverter and three cascaded hybrid-bridge (CHB) inverter cells are used in each phase. Along with the balancing of dc-link capacitors, CHB capacitors’ voltage balancing is also achieved using the pole voltage redundancies at all modulation indexes for all power factor and load. It is also possible to increase more number of levels using more low-voltage switches, and a generalized form of the topology is presented. The concept is validated using a laboratory-developed nine-level inverter with a three-phase IM load, operated under “V/ <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</i> ” control. The detailed experimental results for the steady and transient condition, simulation studies for switching loss, and harmonic content in the phase voltage are also presented.

DC-Link Neutral Point Control for 3L-NPC Converters Utilizing Selective Harmonic Elimination–PWM

Selective harmonic elimination–pulsewidth modulation (SHE–PWM) is a modulation technique widely used to improve the efficiency and harmonic content in medium-voltage high-power converters. Among these converters, the three-level neutral-point-clamped (3L-NPC) converter is one of the most utilized topologies. However, the 3L-NPC converter requires a proper balancing of dc-link capacitor voltages. This article presents a control technique, based on pulse shifting method, to regulate the neutral point voltage when SHE-PWM is utilized. The proposed technique performs well with any power factor and it can also be directly applied to T-type converters and easily extrapolated to other multilevel topologies. The proposed method is experimentally validated in a scaled-down power converter and a full-scale medium-voltage 3L-NPC converter.

Circulating Current Suppression in DAB Assisted Low-Voltage Variable Frequency MMC

Modularity, scalability, and efficiency of modular multilevel converters (MMCs) have shown clear advantages among the multilevel topologies, being ideal for medium and high voltage applications. However, they require several control loops in order to achieve multivariable control, where the main challenge is the voltage balancing of the submodules capacitors, usually requiring large capacitances. To extend the MMC application to the low-voltage range, the arm link enhanced MMC solves this issues by adding dual active bridges (DABs) between the upper and lower submodules (SMs) in order to transfer the power ripple between each other. This allows the use of small capacitances in the SMs and greatly reduces the control and measurement complexity, while maintaining a low voltage ripple in an extended output frequency range. In this scenario, this work studies how the circulating current suppression control (CCSC) affects the DABs power transfer, as well as the overall effects in the converter and its performance. Considering the variable frequency operation of the converter, the effects at low and high frequencies are analyzed, as well as the consequences in the DABs high-frequency transformers. The main objective is to determine whether it is convenient or not to enable the circulating current suppression depending on the operation conditions of the converter.