Backside Of Substrate Research Articles

Incoherent partial superposition modeling for single-shot angle-resolved ellipsometry measurement of thin films on transparent substrates

Ellipsometric measurement of transparent samples suffers from substrate backside reflection challenges, including incoherent and partial superposition issues. The recently developed angle-resolved ellipsometry (ARE) can naturally eliminate the backside reflections of substrates with a micro-spot equivalent thickness or thicker; however, for thinner substrates, ARE working with general incoherent backside reflection models shows significant inaccuracy or measurement failure. In this paper, an incoherent partial superposition (IPS) model is proposed to characterize the optical superposition effect between the frontside and uncertain backside reflections from an unknown substrate. IPS introduces a cosine-like correction of the backside reflection, corresponding to the overlapping-area change of backside and frontside reflections along with incident angles. Benefiting from ARE’s wide-angle spectral imaging capability, IPS achieves single-shot measurement of thin film thicknesses on transparent substrates of unknown thickness. An ARE system was built and calibrated regarding the linear relationship between the cosine-corrected angular frequencies and substrate thicknesses. Then, commercial ITO films on glasses of different thicknesses ranging from 200 to 1000 µm were measured. Experimental results show that IPS-ARE results in a root-mean-square accuracy error of ∼1 nm in film thickness measurement and provides a ∼77% error reduction from general incoherent backside reflection models.

Si Substrate Backside -An Emerging Physical Attack Surface for Secure ICs in Flip Chip Packaging

Si Substrate Backside -An Emerging Physical Attack Surface for Secure ICs in Flip Chip Packaging

Impact of Oxygen on the Generation of Slip Lines and the Electronic Properties of Si-based Substrates

We focus on slip line formation and propagation on different types of Si and SOI substrates that underwent high temperature anneals during 65nm RFSOI device fabrication. Different parameters are found to contribute to slip line formation and dislocations propagation, mainly the substrate properties (thickness, layer and oxygen in silicon handle), the temperature gradients and the support between furnace carriers and backsides of substrates. Several parameters contribute to substrate deformation, e.g. the warpage increase. The warp degradation is found to be directly linked to low oxygen concentrations in silicon handle. This understanding is very helpful to introduce and process new substrates in advanced front-end process flows for MOS device fabrication.

Effect of Local Substrate Removal and Backside Al Heat Dissipation Layer on GaN-on-Si Device RF Performance

This study investigates the influence of local substrate removal and the implementation of a backside Al heat dissipation layer on the radio frequency (RF) performance of GaN-on-Si devices. To optimize the RF properties of these devices by mitigating the influence of the parasitic capacitance layer between the AlN nucleation layer and the Si substrate by the local substrate removal process. Nevertheless, this removal reduces the heat dissipation path, elevating channel temperatures and reducing drain current and transconductance (GM). To address this issue, an Al heat dissipation layer is deposited onto the device’s backside surface. Combining the LSR process and the Al heat dissipation layer improved power-added efficiency from 38.93% to 48.47% at a frequency of 3.5 GHz.

Fabrication of Efficient Perovskite Solar Minimodules with a High Geometric Fill Factor of 96% via a Nanosecond Laser

The low‐cost perovskite solar cell has become the next‐generation photovoltaic. However, compared to the high efficiency of the small‐area perovskite solar cells, the large‐area perovskite solar modules (PSMs) have still been struggling for the performance. In addition to preventing the decline in quality of each functional layer after upscaling, another key point is to construct a high geometric filling factor (GFF) for an efficient PSM. Herein, a “back‐scribing” technique is developed by using a low‐cost nanosecond laser scribing from the back side of substrates. The “back‐scribing” technology can clean up the scribing channels greatly, enabling an effective connection with a small damaged area. With precise control of the laser parameters for the scribing of P1, P2, and P3, a high GFF of 96% is achieved, resulting in a high power conversion efficiency of 19.97% with an aperture area of 16 cm2 for the PSM. By this means, the efficiency loss is minimized (<10%) when upscaling a small device to a large‐area solar module.

Highly Efficient Pyro-Phototronic Effect-Assisted Spectrum-Selective Colloidal Quantum Dot-Based Self-Powered Photodetector

This article presents a highly efficient pyro-phototronic effect-assisted filter-free spectrum-selective colloidal quantum dots (CQDs)-based self-powered photodetector. The reported work shows an enhanced pyro-phototronic effect and a selective response for full-width at half-maximum (FWHM) of 57 nm centered around 398 nm. The device exhibits the maximum external quantum efficiency (EQE) of 3.82% at ~400 nm under self-bias conditions, much higher than the previously reported works. The device structure consists of indium-tin oxide (ITO)-coated glass substrate/ZnO QDs/CdSe QDs/MoOx/Au, where ZnO QDs and MoOx act as charge transport layers. The device is illuminated from the backside (substrate side) to achieve the 100% illumination area. The effective pyroelectric coefficient of the device is also found to be 16.83 times higher than other works at a minimal temperature variation of 0.5 K. The device shows the maximum sensitivity <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${(}{I}_{\text {ph}}/{I}_{d}{)}$ </tex-math></inline-formula> of ~330 under the self-bias condition, indicating the device’s suitability for the self-powered photodetector.

Monolithic Integration of Gesn on Si for IR Camera Demonstration

Due to the development of cost-efficient detector technologies in the NIR (Near Infrared), new areas of application are constantly being addressed. This affects autonomous driving, where LiDAR (Light Detection and Ranging) systems with better eye safety are being developed, as well as low-cost night vision cameras. Another area of application is NIR spectroscopy, e.g. in the areas of food monitoring, environmental research or medical technology. The increasing need for portable, low-cost analysis devices, for example for "on-site" measurements or for everyday life, is driving the development of highly miniaturized and low-cost lab-on-a-chip systems. The NIR detectors and NIR cameras available on the market are primarily based on materials from group III/V compound semiconductors, e.g. InGaAs. However, the CMOS (Complementary Metal Oxide Semiconductor) standard process cannot be used for the production of this technology, which significantly increases the cost factor and thus limits its use on the market. A promising alternative is offered by group IV based detectors, in particular Ge and GeSn detectors, which can be monolithically integrated on a Si substrate. As a result, such detector systems can be processed much more cost-efficiently with CMOS compatible standard technology. The NIR absorption properties are also comparable to III/V components.This paper reports on the monolithic integration of Ge and GeSn detector arrays on Si substrates for the realization of a camera system. The entire system consists of a photonic chip, a readout chip and a standard microcontroller, which is connected to a laptop via USB. The SNR (signal-to-noise ratio) is an important parameter for such an integrated system. The quantum efficiency of each individual pixel sensor has to be maximized and a high fill factor per pixel is aimed for. A particularly high fill factor is achieved here with optical light coupling via the substrate back-side, since the front-side metallization does not interfere with the optical coupling area. Furthermore, the metallization acts then as a mirror, the light thus passes through the absorption area twice and leads to a higher quantum efficiency.However, the main obstacle of Ge and GeSn, compared to III/V devices, is the higher intrinsic charge carrier concentration, which leads to a significantly higher dark current. A possible solution is the zero bias operation of the detector at the expected dark current minimum. The dark current is 3 orders of magnitude smaller at 0 V compared to an operating point at -1 V. Another criterion for the circuit is that a signal range or photocurrent supports a wide dynamic range (between nA and µA). For this purpose, the photocurrent is fed into the evaluation electronics via a triple cascaded current mirror. The measured value is output to a 12-bit ADC (Analog Digital Converter) integrated in the microcontroller via a current/voltage converter, two buffers and a sample hold element. With the help of additional multiplexers, the circuit can be used to read out several detectors and thus address a pixel matrix.We report on the fabrication of the photonic chip, which is carried out using CMOS compatible processes and MEMS (Micro-Electro-Mechanical System) processes in combination with an epitaxial growth of the active device structures. The photonic chip is based on 150 mm Si substrates, which were prepared first with multiple ion implantation steps. The active pin detector layers, consisting of Si and Ge or GeSn, were grown by means of molecular beam epitaxy. Afterwards, deep trenches were now etched between the detectors in a MEMS process to minimize crosstalk between neighboring pixels. The detectors were structured then using CMOS processes, and the backside is polished or structured. Finally, a two layer frontside-metallization is applied for the contacts. We demonstrate the functionality of both two-dimensional and linear detector arrays and show possible applications such as NIR cameras or NIR spectrometers.

Modified microstrip fed of pentagon shape aperture coupling with RDRA for 5G wireless application

In this paper, a rectangular dielectric resonator antenna (RDRA) with modified microstrip feed is proposed. A pentagon-shaped aperture coupling with a bifurcated modified microstrip-line (MSTL) was used to excite the DRA element on the FR4 substrate's backside, resulting in a 3.8 GHz band. Optimizing the design parameters yields a 10% increase in impedance bandwidth, covering frequencies between 3.08 and 3.8 GHz. Maximum gain and radiation efficiency are shown to be 4.85 dB and 90%, respectively, in the operational band using the proposed DRA. As a result, the proposed antenna may be appropriate for use in 5G NR band systems.

Resistor loaded wideband conformal metamaterial absorber for curved surfaces application

In this study, a resistor-loaded wideband conformal metamaterial absorber has been designed, fabricate, and analyzed experimentally. The proposed absorber consists of lumped resistors loaded on cross-shaped resonators at the top side of the flexible substrate and copper metal film separated by flexible foam on the substrate's backside. The total thickness of the absorber is 0.07λo, where λo is the lowest absorption frequency. The simulated results exhibited absorption from 3.25 − 13.6 GHz (absorption bandwidth 123%). The wideband absorption mechanism of the absorber was analyzed through the equivalent circuit model and parametric study. The designed structure has been tested on the planar and curved surfaces and measured the results. The simulated and experimental results have good agreement between them. The designed absorber can be suitable for scientific and military applications as of its wideband absorption bandwidth, polarization-insensitive, and conformability.

Improving backside (N-face) GaN substrate roughening by pre-annealing for GaN-on-GaN LED

This work attempted to improve roughening on backside (N-face) of GaN substrate by increasing the density of hexagonal pyramids for enhanced GaN-on-GaN LED performance. Prior to the roughening by ammonium hydroxide-based etching, the substrate was annealed in two different ambiences; air and oxygen. After the roughening, the hexagonal pyramids with a density of 4.3 × 1010 cm−2 were formed on the substrate with oxygen pre-annealing. For the substrate with air pre-annealing, the hexagonal pyramids density was 2.0 × 1010 cm−2. Meanwhile, the pyramids density for the roughened GaN substrate without pre-annealing was 0.5 × 1010 cm−2. The oxygen pre-annealing introduced more Ga–O compound on the surface. This increased the density of hexagonal pyramids, which resulted after the etching. The GaN-on-GaN LEDs grown on the roughened GaN substrates with pre-annealing (air and oxygen) emitted at 488 nm, while the LED on the roughened GaN substrate without pre-annealing at 510 nm. The optical power increased significantly when the LED grown on the roughened GaN substrate with the oxygen pre-annealing. Overall, this work revealed that the backside GaN roughening can be improved by oxygen pre-annealing, leading to enhance the GaN-on-GaN LED performance.

Effects of Waste Glass Powder Filler on Intumescent Coating for Steel Structures Application

Intumescent coating is a passive fire protection system used to prevent and resist the spreading of fire. The coating swells several times of its thickness on exposure to the fire, forming cellular foam and acts as an insulative barrier, thus delaying the heat transfer to the protected substrate. The study aims to analyse waste glass powder filler’s effect into intumescent coating formulation limited to one size of waste glass powder. Waste glass is a broken form of leftover by-product from industrial and domestic. Millions of tons of waste glass generated every year, adding with their non-biodegradable nature causing additional environmental pollution. Waste glass powder contains high silica composition known for its high thermal stability, weather resistance, hydrophobicity, low surface tension, and high oxidation resistance. The coating showed improved thermal stability, weather resistance, and adhesion when added into intumescent coating formulation. The lowest recorded backside substrate temperature 154.6 °C compare to coating without the waste glass filler, 333.7 C. The coating also showed less than 0.1% total weight loss for samples with 4% wt. filler after immersion in seawater for 15 days compared to the control formulation, 0.19%. The char morphology analysis showed the emergence of silica and calcium elements occupying the expandable char’s gaps, thus strengthening the char structure.

Reducing On-Resistance for SiC Diodes by Thin Wafer and Laser Anneal Technology

This work presents the influence of Thin Wafer und Laser Anneal Technology on the electrical performance of 4HSiC devices. Substrate thinning and backside ohmic contact formation via laser annealing were successfully applied to in-house designed and manufactured 6 A 650 V SiC diodes at IISB, improving its forward characteristics. The given devices exhibit an on-state voltage drop (VF) reduction from 1.78 V to 1.62 V at 6 A rated current while maintaining blocking capabilities of more than 1.1 kV with leakage currents less than 1 μA at 650 V nominal voltage. On-resistance (RON) was lowered by approx. 30 % to 90 mΩ and 60 % to 12 mΩ in Schottky and conductivity modulation state, respectively. Wafer thinning also allows reducing the influence of non-homogeneous distributed substrate doping concentrations, leading to a more narrow distribution of the forward characteristics of the devices across the wafer.

Microtrench‐Patterned Elastomeric Substrate for Stretchable Electronics with Minimal Interference by Bodily Motion

AbstractChallenges associated with local stress concentration on layers in stretchable devices under mechanical deformation by bodily motions, which causes strain‐induced signal interference and generates cracks, constitute one of the remaining issues for realization of skin‐attachable stretchable electronics. Herein, a new structural engineering approach is introduced for an elastomeric substrate, a microtrench‐patterned stretchable substrate, in which microtrenches are formed on the substrate backside, effectively mitigating local stress on the surface layers under stretching. Combining the microtrench pattern on the backside and 3D stress‐absorbing microstructured surface on the frontside of the elastomeric substrate for stress engineering results in effective suppression of stress concentration on the crack‐prone carbon paste electrode and piezoresistive pressure sensing layer on the frontside surface due to stress‐concentration on microtrench pattern and, in turn, minimal change in their resistance with deformation. This approach using a simple and facile method to minimize stress in device layers under motion‐induced deformation has great potential for applications of diverse materials for body‐attachable stretchable electronics with minimal strain‐responsiveness.

Highly efficient InGaN-based LED with pre-roughening backside of GaN substrate

This work proposes that roughening on the backside of a GaN substrate prior to InGaN-based LED growth not only simplifies fabrication steps for the LED but also cleans the other side of the substrate that was served as the surface growth for the LED. As compared to post-roughening, forward voltage of the LED has reduced at 3.48 V through the pre-roughening. Further, the peak external quantum efficiency of the LED on the pre-roughened substrate is 21.6% at 12 m A / c m 2 , while the LED on the post-roughened GaN substrate is 20.6% at 14 m A / c m 2 .

Highly efficient InGaN based LED with pre-roughening backside of GaN substrate

This work proposes that roughening on the backside of a GaN substrate prior to InGaN-based LED growth not only simplifies fabrication steps for the LED but also cleans the other side of the substrate that was served as the surface growth for the LED. As compared to post-roughening, forward voltage of the LED has reduced at 3.48 V through the pre-roughening. Further, the peak external quantum efficiency of the LED on the pre-roughened substrate is 21.6% at 12mA/cm2, while the LED on the post-roughened GaN substrate is 20.6% at14mA/cm2.

Elaboration and characterization of a 200 mm stretchable and flexible ultra-thin semi-conductor film

We describe a process for transferring a 200 nm thick, 200 mm wide monocrystalline silicon (mono c-Si) thin film from a silicon-on-insulator onto a flexible polymer substrate. The result is a stretchable and flexible ultra-thin semi-conductor film that can be subjected to tensile stress experiments. The process uses off-the-shelf 200 mm wafers and standard polymer temporary bonding techniques. The backside substrate and buried oxide are removed using grinding and wet etching processes. No cracks or wrinkles are observed on the film prior to the tensile stress experiments. The stretching of the flexible structure results in up to 1.5% uniaxial tensile elastic strain on the thin mono c-Si film.

Water in contact with the backside of a silicon substrate enables drilling of high-quality holes through the substrate using ultrashort laser pulses.

Holes through silicon substrates are used in silicon microsystems, for example in vertical electrical interconnects. In comparison to deep reactive ion etching, laser drilling is a versatile method for forming these holes, but laser drilling suffers from poor hole quality. In this article, water is used in the silicon drilling process to remove debris and the shape deformations of the holes. Water is introduced into the drilling process through the backside of the substrate to minimize negative effects to the drilling process. Drilling of inclined holes is also demonstrated. The inclined holes could find applications in radio frequency devices.

Вирощування гетероепітаксійних шарів на неізоперіодних підкладках мeтодом скануючої рідиннофазової епітаксії

Heterostructures with lattice mismatched and compositionally different layers are widely used in modern electronic and optoelectronic device engineering. Generally such structures are manufactured by the methods of metal-organic vapor phase epitaxy, metal-organic chemical vapor deposition and molecular-beam epitaxy. However, the methods of deposition from a liquid phase are the most inexpensive and simple yet. Thus obtaining the above mentioned heterostructures from a liquid phase is still promising. In this work we demonstrated the possibility of using the method of scanning liquid phase epitaxy to grow continuous heteroepitaxial layers over the substrate surface highly mismatched by lattice constant and having different crystal-chemical properties. By controlling basic parameters of the method we created the conditions close to the solution-melt saturation limit. In other words, we created the conditions of ultra-fast solution-melt cooling and, respectively, high growth rate. We obtained the heterostructures of Ge layers grown on GaP substrates where the lattice mismatch made 3.7%. Gallium was used as the solvent for Germanium. The heterostructure was grown by the method of scanning liquid phase epitaxy in the conditions of ultra-fast initial cooling of the solution-melt. Overcooling at the crystallization front was controlled by an extra heater of the substrate back side. The growing time was 1 and 20 seconds for the two test samples. The layers thickness was determined by the spherical slice technique to be 1.2 and 1.5 μm for these two growing time values, accordingly. We showed that it was possible to obtain more perfect Ge layers on GaP substrate by lowering the growth rate in the final growth stage. This method can be used to grow heterostructures used in creating such modern electronic and optoelectronic devices as structures based on А3В5 compounds and their solid solutions, which cannot be obtained by other classical methods of liquid phase epitaxy due to significant differences in lattice constants and / or crystal-chemical properties.

Влияние условий формирования геттера в высокоомном кремнии на характеристики PIN-фотодиодов

The influence of gettering conditions in high resistivity silicon during the PIN photodiode fabrication process on the reverse dark currents has been studied. It was demonstrated that the getter formation of backside substrate by a combination of phosphorus ion implantation and deposition of polysilicon film followed by phosphorus doping at the temperatures below 900 0C results in reduction of reverse dark current value and increasing of nonequilibrium carrier lifetime.

Interfacial Strength Evaluation of Oxide Films on Carbon Steel by Using the Laser Shock Adhesion Test

We investigate the adhesion strength (interfacial strength) of the oxide film formed on a carbon steel substrate by using a laser shock adhesion test (LaSAT). A rolled carbon steel (SS400) plate is first heated at high temperature (700 °C) under the atmosphere (heat treatment) to cause the formation of oxide films about 20-50 μm thick on the steel surface. The film consisted of multiple layers, including wustite (FeO), magnetite (Fe3O4), and hematite (Fe2O3). Next, the x-ray diffraction method was used to measure the residual stress in the film. We find that compression stress develops in the film because of a mismatch of thermal strain in between the film and substrate after the heat treatment. With LaSAT, strong elastic wave generates by a pulsed laser ablation of the substrate backside, and results in interfacial fractures in the oxide films. To monitor the normal (out-of-plane) displacement of the top surface film, a laser ultrasonic interferometer is simultaneously utilized, such that we detect film delamination and determine the critical laser energy for interfacial fracture to obtain the critical stress (interfacial strength). Furthermore, additional pulsed laser irradiation is conducted against a pre-delaminated specimen in order to examine the growth of delamination area and evaluate the interfacial fracture toughness. Finally, elastic wave propagation in the sample is computed using the finite element method (FEM) in order to evaluate the interfacial stress field, accurately. For the FEM, multiple layers in the oxide film are modeled, and the residual stress due to thermal strain mismatch is introduced. The FEM computations reveal the stress distribution around the interface and evaluate the critical stress and critical stress intensity factor for delamination. We thus quantitatively evaluate the interfacial strength and interfacial fracture toughness of the oxide film formed on carbon steel. The mechanism of interfacial fracture is also discussed on the basis of microstructures in a film with multiple layers. This result may be useful for understanding the adhesion quality of oxide film during the hot-rolling process.