Backplane Bus Research Articles

Electronics of Time-of-Flight Measurement for Back-n at CSNS

Back-n is a white neutron experimental facility at China Spallation Neutron Source (CSNS). The time structure of the primary proton beam make it fully applicable to use TOF (time-of-flight) method for neutron energy measuring. We implement the electronics of TOF measurement on the general-purpose readout electronics designed for all of the seven detectors in Back-n. The electronics is based on PXIe (Peripheral Component Interconnect Express eXtensions for Instrumentation) platform, which is composed of FDM (Field Digitizer Modules), TCM (Trigger and Clock Module), and SCM (Signal Conditioning Module). T0 signal synchronous to the CSNS accelerator represents the neutron emission from the target. It is the start of time stamp. The trigger and clock module (TCM) receives, synchronizes and distributes the T0 signal to each FDM based on the PXIe backplane bus. Meantime, detector signals after being conditioned are fed into FDMs for waveform digitizing. First sample point of the signal is the stop of time stamp. According to the start, stop time stamp and the time of signal over threshold, the total TOF can be obtained. FPGA-based (Field Programmable Gate Array) TDC is implemented on TCM to accurately acquire the time interval between the asynchronous T0 signal and the global synchronous clock phase. There is also an FPGA-based TDC on FDM to accurately acquire the time interval between T0 arriving at FDM and the first sample point of the detector signal, the over threshold time of signal is obtained offline. This method for TOF measurement is efficient and not needed for additional modules. Test result shows the accuracy of TOF is sub-nanosecond and can meet the requirement for Back-n at CSNS.

Architecture Design of Aviation Fault-tolerant Computer Based on ARINC659 Bus Technology

The ARINC659 backplane bus is suitable for high safety and high reliability requirements of aircraft on-board computer communication systems. This paper analyzes the structure of ARINC 659 serial backplane bus and the bus fault tolerance mechanism. On the basis of backplane bus, a 4 degree of aviation fault-tolerant computer is designed. Moreover, the computer architecture and computer system of the instruction branch and monitoring branch are designed in the computer channel. The fault-tolerant management of the computer is realized by bus fault tolerance, redundancy voting between computers and the monitoring of the instruction and monitoring branches.

Availability analysis of safety grade multiple redundant controller used in advanced nuclear safety systems

We analyze the availability of the Safety Programmable Logic Controller (SPLC) having multiple redundant architectures. In the SPLC, input/output and processor module are configured as triple modular redundancy (TMR), and backplane bus, power and communication modules are configured as dual modular redundancy (DMR). The voting logics for redundant architectures are based on the forwarding error detection. It means that the receivers perform the voting logics based on the status information of transmitters. To analyze the availability of SPLC, we construct the Markov model and simplify the model adopting the system unavailability rate. The results show that the fault coverage factor should be ≥0.8 and Mean Time To Repair (MTTR) should be ≤100h in order to satisfy the requirement that the availability of the safety grade PLC should be ≥0.995. Also we evaluate the availability of SPLC comparing to other PLCs such as simplex, processor DMR (pDMR) and independent TMR (iTMR) PLCs used in the existing nuclear safety systems. The availability of SPLC is higher than those of the simplex, pDMR but is lower than that of iTMR for one month which is the periodic off-line test and inspection. That’s why the number of redundant modules used in PLC is more dominant to increasing the availability than the number of fault masking methods such as voting logics used in PLC on the assumption that operation time is in the early stage. But the availability of iTMR, which has many redundant modules but has only a voting logic fast decrease and eventually is the lowest after 8000h. Also if the MTTR of each module in PLC is required to be increased to 200h, the availability of SPLC would be better than iTMR.

ARINC659总线接口组件抗单粒子翻转加固设计及试验验证

ARINC659是一种标准的多点串行通信总线，具有通用、高效、高可靠等优点，已经越来越多地成为航天器综合电子系统计算机背板总线的理想选型。本文在对ARINC659总线架构和工作机制研究的基础上，对ARINC659总线标准背板总线组件在空间环境应用下的单粒子翻转效应敏感环节进行识别，并提出了有针对性的抗单粒子翻转加固设计措施，最后通过地面模拟试验对抗单粒子翻转加固措施的正确性和有效性进行了验证。试验表明进行单粒子翻转加固设计后的ARINC659总线接口组件满足辐照环境下的应用要求，为ARINC659总线应用于航天领域奠定了基础。 ARINC659 as a standard multipoint serial communication bus, and with the advantage of more general, high efficiency and reliability, has increasingly become the idea selection of backplane bus within the computer of spacecraft avionics system. This paper based on the study of ARINC659 bus architecture and underlying communication mechanism, identifies the sensitive of single event upset for ARINC659 bus interface components applied to space radiation environment, and a set of targeted reinforcement design is put forward for single event upset hardened. Finally, the correction and validity of the reinforcement design are verified by ground simulation experiment, which shows that ARINC659 bus interface components after reinforcement design meet the application in the radiation environment and provide the basis for the application of ARINC659 bus in aerospace.

Architecture and Implementation of OpenPET Firmware and Embedded Software.

OpenPET is an open source, modular, extendible, and high-performance platform suitable for multi-channel data acquisition and analysis. Due to the flexibility of the hardware, firmware, and software architectures, the platform is capable of interfacing with a wide variety of detector modules not only in medical imaging but also in homeland security applications. Analog signals from radiation detectors share similar characteristics - a pulse whose area is proportional to the deposited energy and whose leading edge is used to extract a timing signal. As a result, a generic design method of the platform is adopted for the hardware, firmware, and software architectures and implementations. The analog front-end is hosted on a module called a Detector Board, where each board can filter, combine, timestamp, and process multiple channels independently. The processed data is formatted and sent through a backplane bus to a module called Support Board, where 1 Support Board can host up to eight Detector Board modules. The data in the Support Board, coming from 8 Detector Board modules, can be aggregated or correlated (if needed) depending on the algorithm implemented or runtime mode selected. It is then sent out to a computer workstation for further processing. The number of channels (detector modules), to be processed, mandates the overall OpenPET System Configuration, which is designed to handle up to 1,024 channels using 16-channel Detector Boards in the Standard System Configuration and 16,384 channels using 32-channel Detector Boards in the Large System Configuration.

Manufacturable Polymeric Optical Waveguide based Bus Structures for Board Level Optical Interconnects

Abstract:In this paper, we studied the optimization of preparation for polymeric optical waveguide based bus structures with embedded 45 degree micro-mirrors by metallic hard mold method. The 45º facets on the metallic hard mold, which were used to create the 45 degree micro-mirrors, were studied by the atomic force microscopy (AFM). The surface roughness of the 45 degree facets was reduced from 70nm to be 2nm by a photopolymer coating step. High speed test on the waveguide shows the low loss and high Q-factor performance of the waveguide structures. A backplane bus with 10 Gbits/sec channel will be reported.

Networks on chips — using DQQB (Distributed Queue Quad-Bus) on multi-CPU chips

This paper discusses using a new protocol based on DQDB (Distributed Queue Dual Bus), called DQQB, or Distributed Queue Quad-Bus. The idea is to modify the backplane bus of current architecture by utilizing four busses in the backplane. One bus going in the positive y direction and one going in the negative y direction would allow multiple CPUs on the y -axis to talk to various components by requesting slots and sending data packets (in the reverse direction) reliably. The other two busses are in the positive x direction for upstream and the negative x direction for downstream. The system is inherently stochastic as the data packets may incur bit-flips due to various types of interference, but by applying network protocols for reliable data transfer, we can reduce the probability of error. Also, by redesigning the architecture to account for DQQB, we can dramatically increase our system’s throughput.

15-gb/s bit-interleaved optical backplane bus using volume photopolymer holograms

A 15-Gb/s bit-interleaved optical backplane bus interconnection is experimentally demonstrated in a three-board system based on optical backplane using volume photopolymer holograms. During upstream data transferring, bit pulses from each daughter board are superposed to form an interleaved sequence while for downstream data transferring, the data broadcast from the central board are time-division demultiplexed locally at each daughter board, and only the destined bits are stored respectively. In this way, slow electronic chips can be coordinated to generate a high aggregated bandwidth to relieve wiring congestion. Both nonreturn-to-zero and return-to-zero signaling modes based on vertical-cavity surface-emitting laser sources and pulse lasers are independently employed to implement 2.5- and 15-Gb/s operations. This optical bus architecture also provides a secure and reliable data storage method at 850 nm with a bit-error rate better than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12 </sup>

An optical centralized shared-bus architecture demonstrator for microprocessor-to-memory interconnects

An architecture demonstrator of an innovative interconnect scheme called the optical centralized shared-bus is presented. This architecture retains the advantages of shared-bus topology while at the same time specifying a uniform interface between the electrical and the optical backplane layers in contrast to other proposed architectures. For the first time, a fanout equalized optical backplane bus is demonstrated. In this architecture demonstrator, the data paths required for the microprocessor-to-memory interconnects are provided by the optical centralized shared-bus. The optoelectronic interface modules are optimized to support data rates up to 1.25 Gb/s. The objective of this microprocessor-to-memory interconnects demonstration is to ensure the feasibility of applying this innovative architecture in real systems.

Performance analysis of BusNet protocol for backplane bus-based interprocessor communication

Nowadays, backplane bus-based multiprocessor systems often utilize the standard network protocol such as TCP/IP for communication between processors on the backplane bus. In such systems, it is common for the backplane bus to emulate the standard MAC protocols such as CSMA/CD. This paper aims to analyze the delay performance of the MAC emulation-based backplane network by constructing queueing models based on detailed bus operations. For this purpose, we choose BusNet as a target protocol. BusNet is an ANSI standard network protocol and its specification contains basic operations commonly used in most backplane buses. We investigate the throughput-delay characteristics in terms of packet size, block transfer scale, and arbitration scheme. We also compare the packet delay in BusNet with the IEEE 802.3 CSMA/CD network which BusNet is expected to be compatible with. The simulation result shows how an optimal block transfer scale can be determined in respect of the performance trade-off between BusNet and other real-time traffics.

A method for rebroadcasting signals in an optical backplane bus system

A guided-wave optical backplane bus system intended for use in high-performance board-to-board interconnects is described. Its multiplexed polymeric holograms can implement optical signal broadcast between boards so that all boards share common optical channels. By introducing an active coupler to the doubly multiplexed hologram at the center board, signals received from any board can be rebroadcast to all other boards. We describe the design concepts for a centralized optical backplane and the resulting performance and assembly advantages over previously developed guided-wave and free-space optical backplane bus systems used for broadcasting signals. These advantages include equalized fan-out power, increased interconnect distance, and simpler fabrication.

Continuous Data Block Placement in and Elevation from Tertiary Storage in Hierarchical Storage Servers

Given the cost of memories and the very large storage and bandwidth requirements of large-scale multimedia databases, hierarchical storage servers (which consist of disk-based secondary storage and tape-library-based tertiary storage) are becoming increasingly popular. Such server applications rely upon tape libraries to store all media, exploiting their excellent storage capacity and cost per MB characteristics. They also rely upon disk arrays, exploiting their high bandwidth, to satisfy a very large number of requests. Given typical access patterns and server configurations, the tape drives are fully utilized uploading data for requests that “fall through” to the tertiary level. Such upload operations consume significant secondary storage device and bus bandwidth. In addition, with present technology (and trends) the disk array can serve fewer requests to continuous objects than it can store, mainly due to IO and/or backplane bus bandwidth limitations. In this work we address comprehensively the performance of these hierarchical, continuous-media, storage servers by looking at all three main system resources: the tape drive bandwidth, the secondary-storage bandwidth, and the host's RAM. We provide techniques which, while fully utilizing the tape drive bandwidth (an expensive resource) they introduce bandwidth savings, which allow the secondary storage devices to serve more requests and do so without increasing demands for the host's RAM space. Specifically, we consider the issue of elevating continuous data from its permanent place in tertiary for display purposes. We develop algorithms for sharing the responsibility for the playback between the secondary and tertiary devices and for placing the blocks of continuous objects on tapes, and show how they achieve the above goals. We study these issues for different commercial tape library products with different bandwidth and tape capacity and in environments with and without the multiplexing of tape libraries.

An 8-Gb/s optical backplane bus based on microchannel interconnects: design, fabrication, and performance measurements

We describe the characteristics of a microchannel-based optical backplane including signal-to-noise ratio (SNR), interconnect distances, and data transfer rates. The backplane employs 250 /spl mu/m-spacing two-dimensional (2-D) vertical cavity surface emitting lasers (VCSELs) and a microlens array to implement 500 /spl mu/m-, 750 /spl mu/m-, and 1-mm optical beam arrays. By integrating the transmitter and a multiplexed polymeric hologram as a deflector/beam-splitter for the guided-wave optical backplane, the result demonstrates a multibus line architecture and its high-speed characteristics. Maximum interconnect distances of 6 cm and 14 cm can be achieved to satisfy 10/sup -12/ bit error rate (BER) using 2/spl times/2 beams of 500 /spl mu/m- and 1 mm-spacing array devices. The total data transfer rate of the developed backplane has shown 8 Gb/s from eye diagram measurements.

Computer-aided experiments for a course in dynamic systems and control technology

A new laboratory course has been developed with a set of computer-controlled experiments. The objective is to offer the students 5 to 10 different experiments that build on a generic infrastructure, namely a standard personal computer, an intelligent process interface and an experiment. The processor board communicates through a back plane bus with the instrumentation cards and on the other side provides standard communication interfaces such as RS232 for the communication with the personal computer. This allows the students to use their own notebook computer, which is made available to every student in the university since last year. The user interface is presently built in Lab View and the combination of Matlab and Simulink is used for simulations and other analytical off-line tasks. The experimental setups are designed such that they are mobile, flexible and easy to maintain. Furthermore, they can be used for both educational and research activities in our group.

Design of a bus-based shared-memory multiprocessor DICE

DICE is a shared-bus multiprocessor based on a distributed shared-memory architecture, known as cache-only memory architecture (COMA). Unlike previous COMA proposals for large-scale multiprocessing, DICE utilizes COMA to effectively decrease the speed gap between modem high-performance microprocessors and the bus. DICE tries to optimize COMA for a shared-bus medium, in particular to reduce detrimental effects of the cache coherence and the `last memory block' problem on replacement. In this paper, we present a global bus design of DICE based on the IEEE futurebus+ backplane bus and the Texas Instruments chip-set. Our design demonstrates that necessary bus transactions for DICE can be done efficiently with existing standard bus signals. Considering the benefits of COMA and the moderate design complexity it adds to the conventional shared-bus multiprocessor design, a bus-based COMA multiprocessor, such as DICE, can become a viable candidate for future shared-bus multiprocessor designs.

Testing methodology for FireWire

This article describes a methodology for testing a high-performance serial bus interface commonly referred to as FireWire. Specified by the IEEE 1394 document, FireWire is offered by IC manufacturers in various scalable configurations. In general, it is a low-cost device used to provide a highspeed data path between various systems and products, such as PCs and video devices. FireWire is also usable as a backplane bus interconnect. Application-specific IC manufacturers offer FireWire standard cells for use in custom device designs. To assure cost-effective production, the tester and implementation costs must be reasonable, the execution time must be short, and test results must be accurate. Our methodology fulfils these goals with a minimum of compromises. We validated it using a plastic leaded chip carrier device with an 8-bit parallel port and multiple serial ports on an Advantest T6682 VLSI Logic Test System.

Point-to-Point Real-Time Communication Over a Backplane Bus

This paper suggests two scheduling methods for a real-time point-topoint communication over a backplane bus which has limited priorities for the bus mastership. Fixed priority assignment(FPA) algorithm based on the rate monotonic scheduling is suggested for the periodic hard real-time applications. Dynamic priority assignment(DPA) algorithm based on the earliest deadline first scheduling is suggested for the sporadic soft real-time applications. The worst communication latency for the proposed methods is analyzed and then the schedulability is evaluated using computer simulation.

Prospects of distributed shared memory for reducing global traffic in shared-bus multiprocessors

As an effort, not a mutually exclusive but rather complementary to developing better backplane bus, this paper considers adapting distributed shared-memory (DSM) architectures to improve traditional shared-bus designs. We consider two well-known DSM architectures, namely Cache-coherent Non-Uniform Memory Architecture (NUMA) and Cache-Only Memory Architecture (COMA), in reducing bus traffic. Our study shows that COMA provides excellent opportunity of significantly reducing bandwidth requirement for the bus while cache-coherent NUMA provides a marginal improvement.

On timing constraints of snooping in a bus-based COMA multiprocessor

Cache only memory architecture has the potential to decrease global bus traffic in shared-bus multiprocessors, thereby reducing the speed gap between modern microprocessors and global backplane bus systems. However, the (huge) size of attraction memory (AM) in each processor node makes it difficult to properly match the access time of its state and tag storage to the bus cycle. This becomes a serious burden in efficient snooping, much more than in conventional shared-bus multiprocessors, especially when a high bus clock frequency is used. In this paper, we propose a scheme to relax the timing constraints of snooping in a bus-based COMA multiprocessor, which allows an efficient design of a global bus protocol, and a cost-effective implementation of the overall system by using slower and cheaper memory for the state and tag storage of AM.

An architectural framework for the support of integrated services by broadband customer premises equipment

The ATM customer premises equipment (CPE) architecture proposed in this paper supports a broad range of user applications with varying service requirements. A backplane bus was chosen as a cost effective, reliable means of providing the necessary internal interconnection bandwidth. Incorporating a novel access mechanism and graceful performance degradation under fault conditions, this bus provides a foundation for Quality of Service provision. Essential functions including traffic management, connection admission control and signalling are then built on top of this. A prototype system which uses a semi-custom ASIC to implement the backplane access mechanism is briefly described. The architecture provides a flexible basis for service provision, allowing a single CPE device to meet a variety of end user requirements. Results of simulations showing the effectiveness of internal bandwidth access mechanisms are presented.