Background Calibration Algorithm Research Articles

Digital background calibration algorithm for pipelined ADC based on time-delay neural network with genetic algorithm feature selection

This paper presents a novel background calibration method for pipelined analog-to-digital converters (ADCs) using a time-delay neural network (TDNN), which is optimized through genetic algorithm (GA) techniques. The proposed technique leverages TDNN to create enhanced feature sets, significantly improving the calibration of nonlinear errors exhibiting memory effects. It harnesses the GA's global optimization capabilities for feature selection, effectively reducing the feature dimension and consequently alleviating the NN's computational burden. A parallel pipeline architecture is devised for the calibration circuit, with its implementation realized on FPGA to facilitate forward inference processing. The inference circuit is synthesized using TSMC's 90 nm CMOS process, achieving a power consumption of 40.11 mW and an area of 0.45 mm2. Simulations based on MATLAB for a 14-bit Pipelined ADC demonstrate that the proposed calibration method significantly improves the SFDR from 59.77 dB to 165.52 dB, and ENOB from 8.79 bits to 19.23 bits, surpassing the target ADC's specifications. Moreover, the dimensionality of features is effectively reduced by up to 34 % without compromising the calibration performance.

A fully digital timing background calibration algorithm based on first-order auto-correlation for time-interleaved ADCs

This paper presents a fully digital background calibration method for time-interleaved (TI) analog-to-digital converters (ADCs). The timing detector employs a timing detection method based on an enhanced autocorrelation function, combined with matrix operations, to improve the accuracy of timing mismatch acquisition. The algorithm makes full use of the autocorrelation functions of each channel and proposes a more precise method for obtaining autocorrelation derivatives. Furthermore, the algorithm features a simple structure, low computational complexity, and can support timing calibration for any number of channels without requiring additional channels. The algorithm was validated using an ADC + FPGA combined system, with a 8-channel TI-ADC manufactured in 28 nm technology and a sampling rate of 20 GS/s. Results demonstrate that compared to the uncalibrated state, the algorithm significantly improves the SNDR and SFDR from 27.98 dB and 30.76 dB to 39.38 dB and 42.13 dB, respectively when the inputs are near the Nyquist frequency.

A Timing Mismatch Background Calibration Algorithm With Improved Accuracy

This brief presents a novel timing mismatch background calibration algorithm for time-interleaved (TI) analog-to-digital converters (ADCs). It can calibrate an arbitrary number of channels with an arbitrary input frequency. It also increases the calibration accuracy by applying the autocorrelation functions with an expanded interval. Besides, the proposed algorithm effectively prevents the small derivative values in the correlation difference from degrading the skew estimation accuracy. Compared to prior works on calibration, this work has at least five times better detection accuracy when the frequency of the input signal is close to the Nyquist frequency. This is without the need for calculating the high-order statistics. Finally, we simulate a four-channel 12-bit TI ADC with non-ideal effects added. Simulation results show that the proposed algorithm increases the signal to noise-plus-distortion ratio (SNDR) and spurious-free dynamic range (SFDR) from 35.5 and 40.0 dB to 63.3 and 84.6 dB, respectively, when the input frequency is close to the Nyquist frequency.

A Redundancy-Based Background Calibration for Comparator Offset/Threshold and DAC Gain in a Ping-Pong SAR ADC

A background calibration algorithm is proposed for comparator offsets and thresholds, and for DAC gains. It leverages redundancy in a 2-step ADC to detect errors without the need for additional analog blocks. The algorithm considers an error to have occurred when the fine phase outputs a result within its redundant range. The detected errors are classified into possible erroneous comparisons, and the source of the error is estimated by analyzing the error occurrence pattern. It has been implemented off-chip for a 4× time-interleaved Ping-Pong SAR ADC, which demonstrates the tolerance for ±8% VDD variation and convergence within 180k samples after a sudden 5% VDD drop.

Low Power SAR ADC Design with Digital Background Calibration Algorithm

This paper proposed a digital background calibration algorithm with positive and negative symmetry error tolerance to remedy the capacitor mismatch for successive approximation register analog-to-digital converters (SAR ADCs). Compensate for the errors caused by capacitor mismatches and improve the ADC performance. Combination with a tri-level switching scheme based on the common-mode voltage Vcm to achieve capacitor reduction and high switching energy efficiency. The proposed calibration algorithm significantly improves capacitor mismatch without resorting to extensive computation or dedicated circuits. The active area is 0.046 mm2 in 40 nm Complementary Metal-Oxide-Semiconductor (CMOS) technology. The post-simulation results show the effective number of bits (ENOB) improves from 8.23 bits to 11.36 bits, signal-to-noise-and distortion ratio (SNDR) improves from 51.33 dB to 70.15 dB, respectively, before and after calibration. This improves the spurious-free dynamic range (SFDR) by 24.13 dB, from 61.50 dB up to 85.63 dB. The whole ADC’s power consumption is only 0.3564 mW at sampling rate fs =2 MS/s and Nyquist input frequency, with a figure-of-merit (FOM) 67.8 fJ/conv.-step.

Digital background calibration algorithm and its FPGA implementation for timing mismatch correction of time-interleaved ADC

Sample time error can degrade the performance of time-interleaved analog to digital converters (TIADCs). A fully digital background algorithm is presented in this paper to estimate and correct the timing mismatch errors between four interleaved channels, together with its hardware implementation. The proposed algorithm provides low computation burden and high performance. It is based on the simplified representation of the coefficients of the Lagrange interpolator. Simulation results show that it can suppress error tones in all of the Nyquist band. Results show that, for a four-channel TIADC with 10-bit resolution, the proposed algorithm improves the signal to noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) by 19.27 dB and 35.2 dB, respectively. This analysis was done for an input signal frequency of $$0.09f_s$$ . In the case of an input signal frequency of $$0.45f_s$$ , an improvement by 33.06 dB and 43.14 dB is respectively achieved in SNDR and SFDR. In addition to the simulation, the algorithm was implemented in hardware for real-time evaluation. The low computational burden of the algorithm allowed an FPGA implementation with a low logic resource usage and a high system clock speed (926.95 MHz for four channel algorithm implementation). Thus, the proposed architecture can be used as a post-processing algorithm in host processors for data acquisition systems to improve the performance of TIADC.

A 10-Bit 600-MS/s Time-Interleaved SAR ADC With Interpolation-Based Timing Skew Calibration

This brief presents a 10-bit 600 MS/s 4-channel time-interleaved (TI) successive approximation register analog-to-digital converter (ADC). A background calibration algorithm using Lagrange polynomial interpolation is introduced to calibrate timing skew. It consists of digital detection and adaptive derivative-based correction, employing low filter taps and resulting in hardware reduction. Two reference voltage generators are implemented on-chip to provide a stable reference voltage for the sub-ADCs, enhancing the reliability and robustness of the circuits. The TI-ADC prototype is fabricated in the 65-nm CMOS process and occupies an area of 0.69 mm2. The measurement results show that at a sampling rate of 600 MS/s the ADC achieves a 49-dB SNDR after calibration while dissipating 34 mW from a 1.2/2.5-V supply.

Low complexity digital background calibration algorithm for the correction of timing mismatch in time-interleaved ADCs

A low-complexity post-processing algorithm to estimate and compensate for timing skew error in a four-channel time-interleaved analog to digital converter (TIADC) is presented in this paper, together with its hardware implementation. The Lagrange interpolator is used as the reconstruction filter which alleviates online interpolator redesign by using a simplified representation of coefficients. Simulation results show that the proposed algorithm can suppress error tones for input signal frequency from 0 to 0.4fs. The proposed structure has, at least, 41% reduction in the number of required multipliers. Implementation of the algorithm, for a four-channel 10-bit TIADC, show that, for a 0.4fs input signal frequency, the Signal to Noise and Distortion Ratio (SNDR) and Spurious-Free Dynamic Range (SFDR) are improved 31.26 dB and 43.7 dB, respectively. Our proposed approximation technique does not degrade the performance of system, resulting in the same SNDR and SFDR as the exact coefficient values. In addition, the proposed structure provides an acceptable performance in the presence of wideband signals.

PN-assisted digital background calibration of two-step ADC to over 14-bit accuracy

A new non-binary multiplying digital-to-analog converter (MDAC) structure with signal-dependent dithering scaling technique is proposed in this paper. A full digital background calibration algorithm based on pseudo-random dithers injection is used to calibrate the nonlinear errors of MDAC. By measuring sampling capacitor mismatch and op-amp gain errors of the pipelined analog-to-digital converter (ADC) in background, the errors will be greatly reduced by the proposed calibration algorithm. At the same time, the signal-dependent dithering scaling technique provides a swing margin to the injected pseudo-random signal. By using this technique, the errors caused by the capacitor mismatch and op-amp gain errors can be calibrated at the same time. What’s more, this method greatly accelerates the convergence speed. A two-stage 14-bit pipelined ADC is used to simulate and verify the proposed algorithm. The simulation results indicate the effectiveness of the technique, in which the signal-to-noise plus distortion (SNDR) and the spurious-free dynamic range (SFDR) performance of a 14-bit two-step ADC are improved from 49.12 and 56.25 to 85.68 and 102.23 dB with the input frequency being 0.06 * f s , respectively. The SFDR is more than 98 dB. The SNDR reaches 84 dB in the whole Nyquist bandwidth after calibration. Integral nonlinearity is improved from 80 to 1.5 least significant bits after calibration.

Novel background calibration algorithm for image in non-uniform illumination field

For the purpose of solving the high quality required in some image based measurement systems, a new calibration algorithm for a non-uniform illumination field image is proposed on the basis of some existing algorithm. In this algorithm, by analysing the characteristics of the potential function for target detection, a new potential function for target detection was designed. A measurement function for standardisation of variety was deduced thereafter. After that, the mapping function from the original image to the background calibration image was given. Numerical simulations showed that the proposed algorithm can restrain the non-uniform background illumination field and calibrate the strong fluctuant background of the illumination field image and thus improve the quality of the image. Meanwhile, the algorithm is simple to carry out and very suitable in practice.

Digital background calibration of capacitor mismatches and harmonic distortion in pipelined ADC

A correlation-based digital background calibration algorithm for pipelined Analog-to-Digital Converters (ADCs) is presented in this paper. The merit of the calibration algorithm is that the main errors information, which include the capacitor mismatches and residue amplifier distortion, are extracted integrally. A modified 1st pipelined stage is adopted to solve the signal overflow caused by the Pseudo-random Noise (PN) sequences. Behavioral simulation results verify the effectiveness of the algorithm. It improves the Signal-to-Noise-plus-Distortion Ratio (SNDR) and Spurious-Free-Dynamic-Range (SFDR) of the pipelined ADC from 41.8 dB to 78.3 dB and 55.6 dB to 98.6 dB, respectively, which is comparable to the prior arts.

A digital background calibration algorithm of a pipeline ADC based on output code calculation

This paper proposes a digital background calibration algorithm to correct linearity errors in a pipelined analog-to-digital converter (ADC). The algorithm does not modify the analog circuit of pipelined stages and calibrates the raw conversion output by using a backend digital logic. Based on the analysis of the output codes, the calibration logic estimates the bit weight of each stage and corrects the outputs. An experimental 14-bit pipelined ADC is fabricated to verify the algorithm. The results show that INL errors drop from 20 LSB to 1.7 LSB, DNL errors drop from 2 LSB to 0.4 LSB, SNDR grows from 57 to 65.7 dB and THD drops from −58 to −81 dB. The linearity of the pipelined ADC is improved significantly.

All-Digital Background Calibration of a Successive Approximation ADC Using the “Split ADC” Architecture

The “split ADC” architecture enables fully digital calibration and correction of nonlinearity errors due to capacitor mismatch in a successive approximation (SAR) ADC. The die area of a single ADC design is split into two independent halves, each converting the same input signal. Total area and power is unchanged, resulting in minimal increase in analog complexity. For each conversion, the half-sized ADCs generate two independent outputs which are digitally corrected using estimates of capacitor mismatch errors for each ADC. The ADC outputs are averaged to produce the ADC output code. The difference of the two outputs is used in a background calibration algorithm which estimates the error in the correction parameters. Any nonzero difference drives an LMS feedback loop toward zero difference which can only occur when the average error in each correction parameter is zero. A novel segmentation and shuffling scheme in the SAR capacitive DAC enables background calibration for a wide range of input signals including dc. Simulation of a 16 bit 1 Msps SAR ADC in 180 nm CMOS shows calibration convergence within 200 000 samples.

Background Self-Calibration Algorithm for Pipelined ADC Using Split ADC Scheme

This brief paper describes a background calibration algorithm for a pipelined ADC with an open-loop amplifier using a Split ADC structure. The open-loop amplifier is employed as a residue amplifier in the first stage of the pipelined ADC to realize low power and high speed. However the residue amplifier as well as the DAC suffer from gain error and non-linearity, and hence they need calibration; conventional background calibration methods take a long time to converge. We investigated the split ADC structure for its background calibration with fast convergence, and validated its effectiveness by MATLAB simulation.

Variable-amplitude dither-based digital background calibration algorithm for linear and high-order nonlinear error in pipelined ADCs

Dither-based digital background calibration algorithm has been used to eliminate the influence of linear and nonlinear errors in pipelined ADC. However, this algorithm suffers from two disadvantages: too slow convergent speed and deduction of transmitting signal’s amplitude in analog circuits due to dither injection. Input-dependent variable-amplitude dither-based algorithm is used in this paper to conquer both disadvantages. This proposed algorithm is implemented in a 14-bit, 100MHz sample-rate pipelined ADC. The simulation results illustrate signal-to-noise and distortion (SINAD) of 76.56dB after calibration of linear and nonlinear errors. Furthermore, the convergent speed is improved much more.

A 1.2-V 250-mW 14-b 100-MS/s Digitally Calibrated Pipeline ADC in 90-nm CMOS

This paper describes a digitally calibrated pipeline analog-to-digital converter (ADC) implemented in 90 nm CMOS technology with a 1.2 V supply voltage. A digital background calibration algorithm reduces the linearity requirements in the first stage of the pipeline chain. Range scaling in the first pipeline stage enables a maximal 1.6 Vpp input signal swing, and a charge-reset switch eliminates ISI-induced distortion. The 14b ADC achieves 73 dB SNR and 90 dB SFDR at 100 MS/s sampling rate and 250 mW power consumption. The 73 dB SNDR performance is maintained within 3 dB up to a Nyquist input frequency and the FOM is 0.68 pJ per conversion-step.

Digital Background-Calibration Algorithm for “Split ADC” Architecture

The ldquosplit ADCrdquo architecture enables continuous digital background calibration by splitting the die area of a single ADC design into two independent halves, each converting the same input signal. The two independent outputs are averaged to produce the ADC output code. The difference of the two outputs provides information for a background-calibration algorithm. Since both ADCs convert the same input, when correctly calibrated, their outputs should be equal, and the difference should be zero. Any nonzero difference provides information to an error-estimation algorithm, which adjusts digital-calibration parameters in an adaptive process similar to a least mean square algorithm. This paper describes the calibration algorithm implemented in the specific realization of a 16-bit 1-MS/s algorithmic cyclic ADC. In addition to correcting ADC linearity, the calibration and estimation algorithms are tolerant of offset error and remove linear scale-factor-error mismatch between the ADC channels. Simulated results are presented confirming self-calibration in approximately 10 000 conversions, which represents an improvement of four orders of magnitude over previous statistically based calibration algorithms.

A fully digital fast convergence algorithm for nonlinearity correction in multistage ADC

This paper describes a fast digital background calibration algorithm for pipeline or cyclic analog-to-digital converters. The proposed method corrects for the finite gain/bandwidth of the interstage operational amplifier and for capacitor mismatch in multiplying digital-to-analog converters stages. The new algorithm, fast gain error correction, converges more than 100 times faster than other correlation-based correction techniques presented in literature. The high speed of convergence of the error estimation is due to the use of a polynomial interpolation that cancel the interference in the error estimation process caused by the input signal. This new method does not need any added analog circuitry, does not perturb the output samples, and requires only a digital finite-impulse response filter to implement the polynomial interpolation as opposed to existing fast converging correlation techniques.