Abstract
This paper proposed a digital background calibration algorithm with positive and negative symmetry error tolerance to remedy the capacitor mismatch for successive approximation register analog-to-digital converters (SAR ADCs). Compensate for the errors caused by capacitor mismatches and improve the ADC performance. Combination with a tri-level switching scheme based on the common-mode voltage Vcm to achieve capacitor reduction and high switching energy efficiency. The proposed calibration algorithm significantly improves capacitor mismatch without resorting to extensive computation or dedicated circuits. The active area is 0.046 mm2 in 40 nm Complementary Metal-Oxide-Semiconductor (CMOS) technology. The post-simulation results show the effective number of bits (ENOB) improves from 8.23 bits to 11.36 bits, signal-to-noise-and distortion ratio (SNDR) improves from 51.33 dB to 70.15 dB, respectively, before and after calibration. This improves the spurious-free dynamic range (SFDR) by 24.13 dB, from 61.50 dB up to 85.63 dB. The whole ADC’s power consumption is only 0.3564 mW at sampling rate fs =2 MS/s and Nyquist input frequency, with a figure-of-merit (FOM) 67.8 fJ/conv.-step.
Highlights
In recent years, various applications extensively use analog-to-digital converters, successive approximation register analog-to-digital converter (SAR ADC) domain in low power and medium-speed systems
A traditional fully differential capacitive charge-redistribution SAR ADC consists of four fundamental components: sample and holds (S&H) circuits, capacitive digital-to-analog (CDAC) circuit, dynamic comparator, and SAR control logic circuit
This paper presents a digital background calibration technique based on technique capacitance array redundancy, reducingcaused the voltage difference causedand by capacitancebased array on redundancy, reducing the voltage difference by parasitic capacitance parasitic capacitance and capacitor mismatch, improving the ADC’s performance
Summary
Various applications extensively use analog-to-digital converters, successive approximation register analog-to-digital converter (SAR ADC) domain in low power and medium-speed systems. A traditional fully differential capacitive charge-redistribution SAR ADC consists of four fundamental components: sample and holds (S&H) circuits, capacitive digital-to-analog (CDAC) circuit, dynamic comparator, and SAR control logic circuit. In this architecture, the capacitor mismatch is the main reason for deteriorating the whole ADC performance. This paper proposed a digital background calibration algorithm with positive and negative symmetry error tolerance to remedy the capacitor mismatch for successive approximation register analog-to-digital converters (SAR ADCs). The post-simulation results show the effective number of bits (ENOB) improves from 8.23 bits to 11.36 bits, signal-to-noise-and distortion ratio (SNDR) improves from 51.33 dB to 70.15 dB, respectively, before and after calibration This improves the spurious-free dynamic range (SFDR) by 24.13 dB, from 61.50 dB up to 85.63 dB. The whole ADC’s power consumption is only 0.3564 mW at sampling rate fs =2 MS/s and Nyquist input frequency, with a figure-of-merit (FOM) 67.8 fJ/conv.-step
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