Back-gate Voltage Research Articles

High performance tunnel field effect transistors based on in-plane transition metal dichalcogenide heterojunctions

In-plane heterojunction tunnel field effect transistors based on monolayer transition metal dichalcogenides are studied by means of self-consistent non-equilibrium Green’s functions simulations and an atomistic tight-binding Hamiltonian. We start by comparing several heterojunctions before focusing on the most promising ones, i.e. WTe2-MoS2 and MoTe2-MoS2. The scalability of those devices as a function of channel length is studied, and the influence of backgate voltages on device performance is analyzed. Our results indicate that, by fine-tuning the design parameters, those devices can yield extremely low subthreshold swings (<5 mV/decade) and ION/IOFF ratios higher than 108 at a supply voltage of 0.3 V, making them ideal for ultra-low power consumption.

Monolithic Wafer Scale Integration of Silicon Nanoribbon Sensors with CMOS for Lab-on-Chip Application.

Silicon ribbons (SiRi) have been well-established as highly sensitive transducers for biosensing applications thanks to their high surface to volume ratio. However, selective and multiplexed detection of biomarkers remains a challenge. Further, very few attempts have been made to integrate SiRi with complementary-metal-oxide-semiconductor (CMOS) circuits to form a complete lab-on-chip (LOC). Integration of SiRi with CMOS will facilitate real time detection of the output signal and provide a compact small sized LOC. Here, we propose a novel pixel based SiRi device monolithically integrated with CMOS field-effect-transistors (FET) for real-time selective multiplexed detection. The SiRi pixels are fabricated on a silicon-on-insulator wafer using a top-down method. Each pixel houses a control FET, fluid-gate (FG) and SiRi sensor. The pixel is controlled by simultaneously applying frontgate (VG) and backgate voltage (VBG). The liquid potential can be monitored using the FG. We report the transfer characteristics (ID-VG) of N- and P-type SiRi pixels. Further, the ID-VG characteristics of the SiRis are studied at different VBG. The application of VBG to turn ON the SiRi modulates the subthreshold slope (SS) and threshold voltage (VTH) of the control FET. Particularly, N-type pixels cannot be turned OFF due to the control NFET operating in the strong inversion regime. This is due to large VBG (≥25 V) application to turn ON the SiRi sensor. Conversely, the P-type SiRi sensors do not require large VBG to switch ON. Thus, P-type pixels exhibit excellent ION/IOFF ≥ 106, SS of 70–80 mV/dec and VTH of 0.5 V. These promising results will empower the large-scale cost-efficient production of SiRi based LOC sensors.

High-Performance Two-Dimensional Schottky Diodes Utilizing Chemical Vapour Deposition-Grown Graphene-MoS2 Heterojunctions.

Heterostructures based on two-dimensional (2D) materials have attracted enormous interest as they display unique functionalities and have potential to be applied in next-generation electronics. In this report, we fabricated three types of heterostructures based on chemical vapor deposition-grown graphene and MoS2. A significant rectification was observed in the Au-MoS2-Gr heterojunction, with a rectification ratio over 2 × 104. The rectifying behavior is reproducible among nearly all 44 devices and is attributed to an asymmetrical Schottky barrier at Au-MoS2 and MoS2-graphene contacts. This rectification can be tuned by external gating and laser illumination, which have different impact on the rectifying ratio. This modulation of the Schottky barrier is evidenced by output characteristics of two symmetrical heterostructures: Au-MoS2-Au and Gr-MoS2-Gr field-effect transistors. The effective heights of MoS2-graphene and MoS2-Au Schottky barriers and their response to back-gate voltage and laser irradiation were extracted from output characteristics of Au-MoS2-Au and Gr-MoS2-Gr field-effect transistors. The tuned Schottky barriers could be explained by the Fermi level change of graphene and MoS2. These results contributed to our understanding of 2D heterostructures and have potential applications in novel electronics and optoelectronics.

Bias- and Gate-Tunable Gas Sensor Response Originating from Modulation in the Schottky Barrier Height of a Graphene/MoS2 van der Waals Heterojunction

We report on the gas-sensing characteristics of a van der Waals heterojunction consisting of graphene and a MoS2 flake. To extract the response actually originating from the heterojunction area, the other gas-sensitive parts were passivated by gas barrier layers. The graphene/MoS2 heterojunction device demonstrated a significant change in resistance, by a factor of greater than 103, upon exposure to 1 ppm NO2 under a reverse-bias condition, which was revealed to be a direct reflection of the modulation of the Schottky barrier height at the graphene/MoS2 interface. The magnitude of the response demonstrated strong dependences on the bias and back-gate voltages. The response further increased with increasing reverse bias. Conversely, it dramatically decreased when measured at a large forward bias or a large positive back-gate voltage. These behaviors were analyzed using a metal-semiconductor-metal diode model consisting of graphene/MoS2 and counter Ti/MoS2 Schottky diodes.

Visible-infrared dual-mode MoS2-graphene-MoS2 phototransistor with high ratio of the Iph/Idark

2D materials such as graphene and transition metal dichalcogenides exhibit novel electrical and optoelectrical properties, which are promising for the application in sensing and imaging. However, the photoresponse ability of pure monolayer graphene in room temperature and ratio of Iph and Idark are still unsatisfactory, due to the weak light absorption itself, short lifetime of photo-excited carriers and large dark current, especially in the infrared range. Here, we successfully constructed a broadband graphene-based phototransistor consisting of lateral MoS2-graphene-MoS2 heterostructure by chemical vapor deposition technique. It shows broadband photodetection and a low dark current less than 1 pA at applied bias of 0.5 V, resulting in excellent specific detectivity more than 1012 Jones and nearly 109 Jones in visible and infrared band, respectively. Moreover, the ratio of Iph and Idark could be modulated by the back-gate voltage when the phototransistor is under the infrared illumination. And a high ratio of 105 was exhibited. This type of graphene-based phototransistor by chemical vapor deposition demonstrates an approach for the room temperature broadband photodetection of monolayer graphene by energy engineering. All the results address key challenges for broadband detection by graphene-based phototransistor, and are promising for the large scale fabrication and integration in the future electronic and optoelectronic applications.

A compact interband tunneling current model for Gate-on-Source/Channel SOI-TFETs

A tunneling probability-based drain current model for tunnel field-effect transistors (FETs) is presented. First, an analytical model for the surface potential and the potential at the channel–buried oxide interface is derived for a Gate-on-Source/Channel silicon on insulator (SOI)-tunnel FET (TFET), considering the effect of the back-gate voltage. Next, a drain current model is derived for the same device by using the tunneling probability at the source–channel junction. The proposed model includes physical parameters such as the gate oxide thickness, buried oxide thickness, channel thickness, and front-gate oxide dielectric constant. The proposed model is used to investigate the effects of variation of the front-gate voltage, drain voltage, back-gate voltage, and front-gate dielectric thickness. Moreover, a threshold voltage model is developed and the drain-induced barrier lowering (DIBL) is calculated for the proposed device. The effect of bandgap narrowing is considered in the model. The model is validated by comparison with Technology Computer-Aided Design (TCAD) simulation results.

Comparison of Electrical and Photoelectrical Properties of ReS2 Field-Effect Transistors on Different Dielectric Substrates.

As one of the newly discovered transition-metal dichalcogenides (TMDs), rhenium disulfide (ReS2) has been investigated mostly because of its unique characteristics such as the direct band gap nature even in bulk form, which is not prominent in other TMDs (e.g., MoS2, WSe2, etc.). However, this material possesses a low mobility and an on/off ratio, which restrict its usage in high-speed and fast switching applications. Low mobilities or on/off ratios can also be caused by substrate scattering as well as environmental effects. In this study, we used few-layer ReS2 (FL-ReS2) as a channel material to investigate the substrate-dependent mobility, current on/off ratio, Schottky barrier height (SBH), and trap density of states of different dielectric substrates. The hexagonal boron nitride (h-BN)/FL-ReS2/h-BN structure was observed to exhibit a high mobility of 45 cm2 V-1 s-1, current on/off ratio of about 107, the lowest SBH of about 12 mV at a zero back-gate voltage ( Vbg), and a low trap density of states of about 5 × 1013 cm-3. These quantities are reasonably superior compared to the FL-ReS2 devices on SiO2 substrates. We also observed a nearly 5-fold improvement in the photoresponsivity and external quantum efficiency values for the FL-ReS2 devices on h-BN substrates. We believe that the photonic characteristics of TMDs can be improved by using h-BN as the substrate and capping layer.

Dual-material gate dual-stacked gate dielectrics gate-source overlap tri-gate germanium FinFET: analysis and application

This study proposes a novel dual-material-gate dual-stacked-gate dielectrics gate–source overlap Ge FinFET and compares its characteristics with conventional FinFET. The proposed device shows very less leakage current (IOFF) (~ 10−17 A), significant on drain current (~ ION) (~ 10−4 A), very high ratio of ION to IOFF (ION/IOFF) (~ 1013) and less subthreshold swing of (SS) (71 mV/dec). This study presents the effect of different dielectrics, oxide thicknesses (tox) and back-gate voltages (VGB) on transfer characteristics of the proposed device. The effect of channel concentration on ION/IOFF, threshold voltage (Vth), transconductance (gm) and SS is also investigated. The effect of overlap length (Lov) on analog parameter, gate–source capacitance (Cgs), is also analyzed. Moreover, the effect of fin thickness (Tfin) on Vth and SS is also studied. The height of the BOX plays an important role in reducing IOFF. Moreover, with emphasis on digital application, by using the proposed device a digital inverter circuit is implemented, and this study investigates the characteristics using mixed-mode simulation.

Influence of back gate voltage on electrical transport in Zn1-(y+x)(Alx,Euy)O thin films

We investigated the back gate voltage (VBG) dependent electrical conductivity of Zn1-(y+x)(Alx,Euy)O (x = 0.00, 0.01; y = 0.00, 0.01, 0.02 and 0.05) thin films. Zn1-(y+x)(Alx,Euy)O (x = 0.00, 0.01; y = 0.00, 0.01, 0.02 and 0.05) thin films were synthesized with combining sol-gel and spin coating techniques. Electrical conductivity measurements was monitored by longitudinal conductivity curves of Eu doped (Zn, Al)O thin films. The measurements show a sharp decrease or increase in conductivity of Eu doped (Zn, Al)O thin films by an applied ±VBG, which was not observed for Al doped ZnO thin films. The Eu amount in (Zn, Al)O lattice was the key parameter to manage the change in conductivity by ±VBG. The highest increase in conductivity by applied ±VBG was observed for 1 mol% Eu-doped Zn1-(y+0.01)(Al0.01,Euy)O films, which also performed the highest longitudinal conductivity without a VBG. By applied VBG = −100 V, the change ratio in conductivity reached up to 436% for 1 mol% Eu doped (Zn, Al)O thin films. The response to VBG were drastically decreased by increase in Eu amounts in the lattice, and furthermore no change in conductivity was observed for 5 mol% Eu doped (Zn, Al)O thin films.

Electric-field tuning of the valley splitting in silicon corner dots

We perform an excited state spectroscopy analysis of a silicon corner dot in a nanowire field-effect transistor to assess the electric field tunability of the valley splitting. First, we demonstrate a back-gate-controlled transition between a single quantum dot and a double quantum dot in parallel which allows tuning the device into corner dot formation. We find a linear dependence of the valley splitting on back-gate voltage, from 880 μeV to 610 μeV with a slope of −45 ± 3 μeV/V (or equivalently a slope of −48 ± 3 μeV/(MV/m) with respect to the effective field). The experimental results are backed up by tight-binding simulations that include the effect of surface roughness, remote charges in the gate stack, and discrete dopants in the channel. Our results demonstrate a way to electrically tune the valley splitting in silicon-on-insulator-based quantum dots, a requirement to achieve all-electrical manipulation of silicon spin qubits.

(Invited) SOI Wafer Technology for Advanced Mos Applications

Emerging microelectronic applications such as Internet-Of-Things (IOT) or mixed signal processing utilize fully depleted MOSFETs built on SOI wafers. Advanced FD devices such as planar MOSFETs with back gate biasing require wafers with thin Si top layer as well as ultra thin BOX layer. To sustain good electrostatic control of the channel and to keep back-gate voltages reasonably low, top Si layer thickness has to be in the 5-10 nm range and BOX thickness needs to be less than 20 nm. The SmartCutTM process is the only technology that allows transferring extremely thin layers of silicon on a wide range of handling substrates with industrial quality. As threshold voltage of FD SOI transistor depends on the thickness of Si layer, the thickness has to be controlled within extremely tight tolerance, typically + /- 5A in full range of spatial frequencies spanning from 10 nm till 300 mm [1]. This creates challenge not only for manufacturing technology, but requires development of new thickness metrology. Introduction of differential reflection microscopy (DRM) [2] allows in-line SOI thickness control in wide range of spatial frequencies with unprecedented throughput and precision. The principles and main applications of DRM will be discussed in the presentation. The key process steps with their influence on specific spatial frequencies are identified. One of the main contributors to mid range frequency (in mm range) thickness variation is the interaction of propagating fracture front with acoustic waves emitted by itself. The experimental verification of this mechanism as well as the results of numerical simulations will be presented. Another critical process in SOI technology is reduction of high frequency thickness variations during finishing steps. Possibilities of using pure surface diffusion as well as chemically enhanced high temperature smoothing will be demonstrated. It will be shown that during high temperature annealing in neutral atmosphere Si surface evolution can be described by Mullings-Herring equation with two extra stochastic terms, responsible for conservative and non-conservative noise, while addition of HCl to the annealing atmosphere changes surface behavior to surface relaxation described by the Edwards-Wilkinson model. General linear 4th order surface development model is proposed covering both mechanisms. Material parameters for the model are determined experimentally in the case of HCl(<1%)/H2 etching of silicon. For some advanced applications base wafer of SOI structure can play functional role in the final device, not limited to a mechanical support. One of such examples is RF SOI substrates specifically designed for RF analog applications, such as front end RF modules in smartphones. Introduction of thermally stable layer with high density of carrier traps between BOX layer and high resistivity Si substrate significantly improves high frequency electrical parameters of the devices built on such substrates [3]. Insertion loss, second harmonic generation of coplanar waveguides as well as quality factors of inductors are such main parameters. Empirical model is presented which allows prediction of the results of RF measurements from simple SRP data.

Yield and Reliability of Nanocrystalline Graphene Field-Effect Gas Sensors

Nanocrystalline graphene field-effect transistors show promising properties for the detection of ammonia (1). For large scale fabrication the yield of transfer-free in situ grown nanocrystalline graphene field-effect transistors is investigated on the basis of the input characteristics of 524 devices with nominal width of 20µm and lengths of 3µm. Furthermore, a first study on the reliability on ncGFETs is given in respect to the charge trapping behavior of the ncGFETs. For that purpose, continuous input characteristics of individual ncGFETs have been recorded, analyzing the stability of the devices. Moreover, the hysteresis of the ncGFETs seen from the input characteristics is characterized in respect to the backgate voltage transient.

Anisotropic superconductivity and frozen electronic states at the (111) LaAlO3/SrTiO3 interface

In spite of Anderson's theorem, disorder is known to affect superconductivity in conventional s-wave superconductors. In most superconductors, the degree of disorder is fixed during sample preparation. Here we report measurements of the superconducting properties of the two-dimensional gas that forms at the interface between LaAlO$_3$ (LAO) and SrTiO$_3$ (STO) in the (111) crystal orientation, a system that permits \emph{in situ} tuning of carrier density and disorder by means of a back gate voltage $V_g$. Like the (001) oriented LAO/STO interface, superconductivity at the (111) LAO/STO interface can be tuned by $V_g$. In contrast to the (001) interface, superconductivity in these (111) samples is anisotropic, being different along different interface crystal directions, consistent with the strong anisotropy already observed other transport properties at the (111) LAO/STO interface. In addition, we find that the (111) interface samples "remember" the backgate voltage $V_F$ at which they are cooled at temperatures near the superconducting transition temperature $T_c$, even if $V_g$ is subsequently changed at lower temperatures. The low energy scale and other characteristics of this memory effect ($<1$ K) distinguish it from charge-trapping effects previously observed in (001) interface samples.

Implementation of Low Power Programmable Flash ADC Using IDUDGMOSFET

In this brief, a novel programmable low power analog-to-digital converter (ADC) circuit design is proposed using independently driven underlap double gate MOSFET (IDUDGMOS) to operate in radio frequency domain and its performance is studied. The primary motivation of the design is to eliminate the need for a resistor ladder for reference voltage selection and to minimize the number of transistor used in the flash ADCs. The proposed design utilizes the back gate voltage controllability of IDUDGMOS for varying reference voltage of the comparators in the ADCs. The parameters of the designed ADC analyzed are the bandwidth, the linearity, and the power consumption of the circuit. The proposed circuit offers wider bandwidth and lower power consumption compared to earlier ADC designs.

Correlation between superconductivity, band filling, and electron confinement at the LaAlO3/SrTiO3 interface

By combined top- and backgating, we explore the correlation of superconductivity with band filling and electron confinement at the LaAlO$_3$-SrTiO$_3$ interface. We find that the top- and backgate voltages have distinctly different effects on the superconducting critical temperature, implying that the confining potential well has a profound effect on superconductivity. We investigate the origin of this behavior by comparing the gate-dependence of $T_c$ to the corresponding evolution of the band filling with gate voltage. For several backgate voltages, we observe maximum $T_c$ to consistently coincide with a kink in tuning the band filling for high topgate voltage. Self-consistent Schr\"odinger-Poisson calculations relate this kink to a Lifshitz transition of the second $d_{xy}$ subband. These results establish a major role for confinement-induced subbands in the phase diagram of SrTiO$_3$ surface states, and establish gating as a means to control the relative energy of these states.

Intrinsic counterclockwise hysteresis in Mn-doped Pb(Zr,Ti)O3 gated MoS2 field effect transistors

The intrinsic counterclockwise hysteresis induced by the ferroelectric polarization is always concealed in Pb(Zr,Ti)O3 (PZT) gated MoS2 filed-effect transistors (FETs). Here, we observed the well-defined counterclockwise hysteresis in MoS2 FETs with the Mn-doped PZT (Mn-PZT) dielectric layer. The evolution of hysteresis with varying the range of back-gate voltage (Vbg,max) was investigated. The good linear relation was obtained for hysteresis area (〈A〉) with varying Vbg,max. The similar variation tendencies were observed for memory windows (ΔV) of the FET and the coercive voltage (2 Vc) of the PZT film with increasing Vbg,max, indicating the memory windows were defined by the coercive voltages. The hysteresis behavior in this study was thought to be dominant by the intrinsic hysteresis effect of the ferroelectric polarization, which was discussed by the disappearance of the dead layer and the decrease of oxygen vacancies at the PZT/MoS2 interface due to Mn doping.

A Low Power CMOS-Based VCO Design with I-MOS Varactor Tuning Control

This paper presents a new design of low power voltage controlled oscillator (VCO) circuit using three transistors NOR-gate and I-MOS (inversion mode) varactor tuning method. Variation in the oscillation frequency has been obtained by varying the output load capacitance with the use of I-MOS varactor tuning consisting of two PMOS transistors connected in parallel. Variable capacitance across the I-MOS varactor has been achieved by varying the source/drain voltage ([Formula: see text] and back-gate voltage ([Formula: see text]. Variation of [Formula: see text] from 1[Formula: see text]V to 2[Formula: see text]V provides the frequency deviation from 1.970[Formula: see text]GHz to 1.379[Formula: see text]GHz with I-MOS width of 8 [Formula: see text]m at power supply voltage ([Formula: see text] of 1.8[Formula: see text]V. Power consumption of the circuit is 1.296[Formula: see text]mW with [Formula: see text] of 1.8[Formula: see text]V. The results have been obtained for different I-MOS varactor widths like 5[Formula: see text][Formula: see text]m, 8[Formula: see text][Formula: see text]m and 10[Formula: see text][Formula: see text]m. Further, variations in the frequency have been obtained from 0.650 GHz to 2.584 GHz with the Vdd variation from 1[Formula: see text]V to 3[Formula: see text]V. In addition, by variations of [Formula: see text] from 0[Formula: see text]V to 1.8[Formula: see text]V and [Formula: see text] from 1[Formula: see text]V to 3[Formula: see text]V, the proposed oscillators operate in the frequency range from 0.556[Formula: see text]GHz to 2.584[Formula: see text]GHz for 8[Formula: see text][Formula: see text]m width of I-MOS varactor. Proposed VCO circuit show a phase noise of [Formula: see text][Formula: see text]dBc/Hz at 1[Formula: see text]MHz offset from the carrier frequency and the figure of merit (FoM) for the VCO is 154.51[Formula: see text]dB/Hz. Proposed VCO shows an improved performance in terms of power consumption, output frequency and FoM.

Role of the charge state of interface defects in electronic inhomogeneity evolution with gate voltage in graphene

Evolution of electronic inhomogeneities with back-gate voltage in graphene on SiO$_2$ was studied using room temperature scanning tunneling microscopy and spectroscopy. The reversal of local contrast in some places in the STS maps and sharp changes in cross-correlations between topographic and conductance maps, when graphene Fermi energy approaches its Dirac point, are attributed to change in charge-state of interface defects. The spatial correlations in the conductance maps, described by two different length scales and their growth during approach to Dirac point, show a qualitative agreement with the predictions of the screening theory of graphene. Thus a sharp change in the two length-scales close to the Dirac point, seen in our experiments, is interpreted in terms of the change in charge state of some of the interface defects. A systematic understanding and control of the charge state of defects will help in memory applications of graphene.

(Invited) Individual Nanowire/Sheet Devices for Electrocatalysis

Nowadays, substantial works have been devoted to electrochemical energy storage and conversion due to the increasing global energy demand. The individual nanowire/sheet electrochemical devices can establish an intrinsic relationship between the electrochemical performance and electronic transport. Meanwhile, it is a fantastic platform to tune the electrochemical behavior (including electrochemical energy storage and electrocatalytic) with external fields, which is meaningful on understanding the reaction mechanism and further developing new optimize strategy. Here, we highlight the recent developments of individual nanowire-sheet electrochemical devices in energy storage and catalysis.1 In the electrocatalytic field, we designed an in-situ testing platform with individual Ni-graphene nanosheet based oxygen evolution reaction devices.2 It is demonstrated that the oxygen acts as a barrier to significantly reduce the concentration of OH− ions at catalyst surface, slowing down the charge transfer process and OER kinetics. By removing oxygen in the electrolyte, a significant decrease in Tafel slope of over 20% and an early onset potential of 1.344 V vs. RHE have been achieved. Afterwards, the individual electrocatalytic devices were applied to understand how does the external electric field tune the hydrogen evolution reaction (HER) behavior. Increasing the back gate voltage from 0 to 5 V, the overpotential of individual MoS2 nanosheet decreases from 240 to 38 mV.3 Such strategy is further extended to VSe2 nanosheet.4 Our results indicate that HER performance improves along with the increasing of the negative back gate voltage. Besides, charge transfer resistance and high-frequency time constant drop dramatically, which demonstrates a much faster charge transfer process. Reference Mai L*, Yan M, Zhao Y. Track batteries degrading in real time. Nature 2017, 546(7659): 469.Wang P, Yan M*, Meng J, Jiang G, Qu L, Pan X, Mai L*, et al. Oxygen evolution reaction dynamics monitored by an individual nanosheet-based electronic circuit. Nature Communications 2017, 8.Wang J, Yan M*, Zhao K, Liao X, Wang P, Pan X, Mai L*, et al. Field Effect Enhanced Hydrogen Evolution Reaction of MoS2 Nanosheets. Advanced Materials 2017, 29(7).Yan M, Pan X, Wang P, Chen F, He L, Jiang G, et al. Field-effect tuned adsorption-dynamics of VSe2 nanosheet for enhanced hydrogen evolution reaction. Nano Letters 17(7): 4109.

On-chip Heaters for Tension Tuning of Graphene Nanodrums.

For the study and application of graphene membranes, it is essential to have means to control their resonance frequency and temperature. Here, we present an on-chip heater platform for local tuning of in-plane tension in graphene mechanical resonators. By Joule heating of a metallic suspension ring we show thermomechanical resonance frequency tuning in a few-layer (FL) graphene nanodrum, which is accompanied by an increase in its quality factor, which we attribute to the increase of the in-plane tension. The in situ control of temperature, in-plane tension, resonance frequency, and quality factor of suspended two-dimensional (2D) nanodrums makes this device a unique platform for investigating the origin of dissipation in these ultrathin structures and can be of fundamental importance for studying the thermal properties of 2D materials. Moreover, by simultaneously controlling the heater and the backgate voltage, we can independently control the resonance frequency and quality factor, which is of great importance for applications in sensors and resonant mechanical filters.