Back End Of Line Process Research Articles

Bevel RIE Application to Reduce Defectivity in Copper BEOL Processing

Bevel etch used during wafer fabrication for semiconductor devices is discussed. In this paper, the bevel etch process was utilized in middle of the line processing to reduce back end of line (BEOL) defectivity. Tungsten and titanium nitride films, from the formation of contacts to the transistors, extend into the bevel region of the wafer and have been shown to initiate arcing. This can spread foreign material defects on the front side of the wafer in various BEOL postprocessing steps, including subsequent reactive ion etching, SEM metrology, and film depositions. The bevel etch tool confines a plasma etch to the outer edge of the front side of the wafer (which can be individually adjusted), and can remove dielectric, organic, and Ti/TiN/W films using a fluorine based chemistry.

(Invited) Optimization of WAl2O3Cu(-Te) Material Stack for High-Performance Conductive-Bridging Memory Cells

In this paper, we optimize the thermal stability of WAl2O3Cu and WAl2O3Cu-Te conductive-bridging cells for integration of 1-Transistor/1-Resistor (1T1R) memory elements. Thermal stability up to the back-end-of-line (BEOL) processing temperature of 400°C is ensured by Cu-Te composition tuning and carbon alloying developments, while Cu in-diffusion processes during BEOL processing is limited through the engineering of thin Ti-, Ta-, and TiW-based metallic liners inserted at the Al2O3Cu(-Te) interface. The integrated 1T1R cells are demonstrated to operate in the nanosecond range using moderate voltages. Write endurance of >106 cycles is achieved using 10ns-short pulses while high voltage-disturb robustness is observed at lower voltages, resulting in excellent voltage-time characteristics of the cells. Finally, images of device filaments programmed in low- and high-resistance states are successfully obtained by means of conductive atomic-force-microscopy

Integration of Wet Cleaning in 45 Nm Pitch BEOL Processing

A partial-trench via first with self-aligned double patterning (SADP) approach is used to realize a 45 nm pitch using a dual damascene compatible hardmask. This back-end of line (BEOL) integration approach is used to investigate the ability to integrate advanced low-k materials and more specifically to assess their patterning performance. Throughout this SADP integration approach, different specific cleaning steps are required. A first cleaning process is needed after spacer etch and amorphous-carbon (a-C) strip to remove the spacer etch residues that are formed. Further in the integration flow, a TiN clean is needed together with a post-etch residue removal (PERR) after low-k etch.

Tantalum-Nitride Antifuse Electromechanical OTP for Embedded Memory Applications

Embedded nonvolatile memory (NVM) integrated in the back-end of line processes are of high interest, particularly for rugged environments (high temperature/radiation or vibration). This letter demonstrates the use of tantalum nitride microbeams as antifuse one-time programmable (OTP) NVM. It needs a single mask process and can be integrated above an integrated circuit. Typical fusing current is 1 mA, operating voltage is 4 V, and the measured contact resistance is <;2 kQ. A hybrid one-transistor/one microbeam/bit memory array is proposed for back-end compatible and low-cost OTP NVM integration.

Wet Removal of Post-Etch Residues by a Combination of UV Irradiation and a SC1 Process

In back-end of line processing (BEOL), the polymer deposited on the dielectric sidewalls during the etch process must be removed prior to subsequent processing steps to achieve high adhesion and good coverage of materials deposited in the etched features [1, . Typically, this is done by a combination of a short plasma treatment and a diluted wet clean, or by wet cleans alone. On the one hand, for porous dielectric stacks, a mild plasma treatment that preserves the integrity of the low-k dielectrics would not be sufficient to effectively remove this residue. With regard to wet clean, diluted aqueous solutions (e.g. HF-based) are not efficient for polymer removal without etching the underlying dielectric to lift off the polymer, leading to unacceptable critical dimension (CD) loss. In addition, analytical techniques available for direct characterization of sidewall residues are limited. For a fast screening of potential chemistries capable of dissolving/removing polymer residues generated during the low-k etch, a model fluoropolymer was deposited on a blanket, checkerboard low-k substrate. The present study mainly focused on the characterization of model polymer after deposition (as-deposited) and after immersion in aqueous and solvent-based cleaning solutions. The polymer removal efficiency was influenced/ improved by UV treatments prior to wet clean processes. In the second part of the study, selected UV treatment conditions and cleaning solutions were applied to low-k patterned structures using Angle-resolved X-ray photoelectron spectroscopy (AR-XPS) to characterize the dielectric sidewall before and after UV modification and the subsequent cleaning process.

Modification of Post-Etch Residues by UV for Wet Removal

In back-end of line processing, the polymer deposited on the dielectric sidewalls during the etch must be removed prior to subsequent processing steps to achieve high adhesion and good coverage of materials deposited in the etched features [1,. Typically, this is done by a combination of short plasma treatment and diluted wet clean, or by wet cleans alone. On the one hand, for porous dielectric stacks, a mild plasma treatment that preserves the integrity of the low-k dielectrics would not be sufficient to efficiently remove this residue. Furthermore, aqueous cleaning solutions is not efficient to achieve a complete removal without etching the underlying layer. Hence appropriate wet clean chemistries are needed to dissolve/decompose these polymers without etching the dielectric. On the other hand, analytical techniques available for direct characterization of sidewall polymer are limited. For a fast screening of potential chemistries capable of dissolving/removing polymer residues generated during the low-k etch, a fluoropolymer deposited on a blanket, checkerboard low-k substrate was used as a model polymer. In our recent study [, using X-ray photoelectron spectroscopy (XPS), it was shown that the polymer was composed of CF, CF2, and CF3 groups. This model polymer was found to be very similar to the polymer residue generated during the etch of the low-k stack using similar plasma. The present study mainly focused on the effect of UV treatment and the concentration of active component in wet clean solution on the structure change of the polymer and the enhancement of polymer removal.

Fabrication of low-loss SOI nano-waveguides including BEOL processes for nonlinear applications

We report successful fabrication of low-loss SOI nano-waveguides with integrated PIN diode structures. The entire fabrication process is done on a 200 mm BiCMOS toolset using front-end-of-line (FEOL) and back-end-of-line (BEOL) processes and does not show any undesirable influence upon the photonic performance. Such a waveguide technology forms an attractive platform for a wide range of nonlinear applications due to efficient free carrier removal as well as use of standard substrates and processing technology. Nonlinear experiments were conducted to investigate the potential of the introduced technology. The performance of the designed waveguides can be used as a benchmark for future development of proposed platform for integrated silicon photonics and electronics circuits.

Cu pumping in TSVs: Effect of pre-CMP thermal budget

When Cu ‘Through-Silicon-Vias’ (TSVs) are exposed to high temperatures as typically encountered during the back-end of line (BEOL) processing, the higher coefficient of thermal expansion (CTE) of Cu forces it to expand more than Si. This causes compressive stress in the confined Cu inside the TSV. This stress can partly be released near the top of the TSV, by out-of-plane expansion of the Cu, the so-called ‘Cu pumping’. It can severely damage the BEOL layers. In this paper the effect of a pre-CMP thermal budget (temperature and time) on Cu pumping is studied for various Cu chemistries and TSV aspect ratios. It is shown that to suppress Cu pumping a pre-CMP anneal is required that is either very long or at a temperature very close to the maximum temperature used in the BEOL processing.

Bottom‐Up Engineering of Subnanometer Copper Diffusion Barriers Using NH2‐Derived Self‐Assembled Monolayers

AbstractA 3‐aminopropyltrimethoxysilane‐derived self‐assembled monolayer (NH2SAM) is investigated as a barrier against copper diffusion for application in back‐end‐of‐line (BEOL) technology. The essential characteristics studied include thermal stability to BEOL processing, inhibition of copper diffusion, and adhesion to both the underlying SiO2 dielectric substrate and the Cu over‐layer. Time‐of‐flight secondary ion mass spectrometry and X‐ray spectroscopy (XPS) analysis reveal that the copper over‐layer closes at 1–2‐nm thickness, comparable with the 1.3‐nm closure of state‐of‐the‐art Ta/TaN Cu diffusion barriers. That the NH2SAM remains intact upon Cu deposition and subsequent annealing is unambiguously revealed by energy‐filtered transmission electron microscopy supported by XPS. The SAM forms a well‐defined carbon‐rich interface with the Cu over‐layer and electron energy loss spectroscopy shows no evidence of Cu penetration into the SAM. Interestingly, the adhesion of the Cu/NH2SAM/SiO2 system increases with annealing temperature up to 7.2 J m−2 at 400 °C, comparable to Ta/TaN (7.5 J m−2 at room temperature). The corresponding fracture analysis shows that when failure does occur it is located at the Cu/SAM interface. Overall, these results demonstrate that NH2SAM is a suitable candidate for subnanometer‐scale diffusion barrier application in a selective coating for copper advanced interconnects.

RF-MEMS switching devices using vertical comb-drive actuation in the CMOS process

Radio frequency micro-electro-mechanical system (RF-MEMS) switching devices using vertical comb-drive actuation toward low-voltage actuation, fast response are presented in this paper. The switching devices, which comprise comb-drive electrodes, are actuated entirely by the electrostatic forces applied not only for the down-state but also for the up-state. The cost-effective MEMS process compatible with the complementary metal oxide semiconductor (CMOS) process is presented in this paper as well. The fabrication process is composed by adapting the CMOS 0.18 µm back end of line (BEOL) process on 200 mm wafers. The MEMS process in the CMOS process enables the realization of passive devices integrated with active devices, which is effective for size and cost reduction. Two metal interconnection layers in the BEOL process are used for the MEMS process. Interconnection aluminum and inter-layer dielectric tetraethoxysilane (TEOS) are used as MEMS structural material and sacrificial material, respectively. The chemical mechanical polishing (CMP) process is implemented to planarize the sacrificial material surface. The structures were fabricated using a simple low-cost two-mask process. The characteristics of switching capacitors, C-V, RF performance, switching speed and continuous drive cycles are measured on the fabricated devices. The capacitance ratio for the down-state/up-state is Cdown/Cup = 5.4. The characteristics of switching speed response/actuation voltage in the down-state and up-state are 4.5 µs/5 V and 8.0 µs/5 V, respectively. The switching speed is stable up to 107 cycles in spite of the fact that the unipolar voltage speed is stable up to 107 cycles.

The Evaluation Technologies of Materials Such as Polymers Used in a Semiconductor BEOL Process

An introduction of new materials has been the important breakthrough in each technology node. For the rapid development of novel materials, material suppliers have founded Consortium for Advanced Semiconductor Materials and Related Technologies (CASMAT) in 2003. CASMAT provides whole equipment for process of Back-end- Of-Line (BEOL), and applies new materials to 300mm silicon wafers. CASMAT evaluates, and reveals important characteristics of those materials, points out issues, also offers efficient solutions to material suppliers. As a result, they can shorten the research and development period of materials, and expand their business because of bringing new products to the market rapidly. As the examples, Test Element Group (TEG) masks and wafers, a quantitative evaluation method of adhesion strength, and an integrated solution for wiring with a polymer low-k material are presented here.

CMOS integrated radio frequency dome resonator

Resonant RF MEMS structures can offer excellent performance for integrated sensing and RF signal processing applications. MEMS devices offer small size and low power consumption and improved physical parameters such as FQ product; however, significant impediments to a large scale commercial adoption include: production cost, difficulty of implementation and signal transduction. In this paper, we developed a generic pathway for CMOS–MEMS integration by designing MEMS dome resonators in multiple layers of stacked polycrystalline silicon in standard CMOS back end of line process and demonstrate the quality factor of dome resonator both optically and electrically. In this work, we report the highest FQ product of integrated resonator at micron level using commercial CMOS technology and the lowest operation power.

Analysis of Cu/Low- k structure under back end of line process

As the progress of the semiconductor process develops to achieve miniaturization and attain better performances for the electronic device, next-generation IC chips with deep sub-micron Cu/low-k stacked structures adopting the fabrication of (dual) damascene are developed to meet the urgent requirements of reducing high RC delay; the purpose of this is to obtain high-speed signal communication. However, due to poor adhesion and intrinsically lower fracture toughness of low-k materials as well as process loading that introduces flaws and delaminations, the phenomenon of crack growth is observed. To investigate the large scale difference problem, such as the back end of line (BEoL) structure to the silicon chip, a special multi-scale finite element simulation technology, global–local finite element method, is used to deal with this issue. The interfacial crack in the BEoL structure is modeled using the global–local technique. The chemical vapor deposition (CVD) process that induced loading to a micro crack in the interface between etch stop layer and metal track layer (ESL/Mx interface) will also be discussed through a statistical factorial design method in order to understand the crack growth phenomena that might occur during the BEoL process.

Application of Electron Projection Lithography to Via Formation in Two-Layer Metallization

In this paper we showed electron projection lithography (EPL) applicability to via formation in a back-end-of-line (BEOL) process for 45-nm technology node through fabricating a two-layer metallization device. We developed a single-layer via-resist process for 45-nm technology node. In order to prevent resist profile deteriorations, we optimized process conditions of a bottom anti-reflective coating (BARC) and an electrical conductive film (ECF). As a result, fine 60-nm (1:1) via-patterns were obtained after low-k dry-etching and 67-nm via-holes filling with Cu could be confirmed by using cross-sectional transmission electron microscope (TEM). These results suggested the single-layer via-resist process we developed could be applied for 45-nm technology node. In addition, for 32-nm technology node, we developed a tri-layer via-resist process that had a high resolution compared with a single-layer resist process. There, we could obtain extremely fine 40-nm (1:1) top-layer via-resist patterns. We believe that EPL has high applicability to via formation in BEOL process for not only 45-nm but also 32-nm technology node.

Novel Back End-of-Line Process Scheme for Improvement of Negative Bias Temperature Instability Lifetime

A novel back end-of-line (BEOL) process scheme is proposed to improve negative bias temperature instability (NBTI) characteristics through the characterization of the impact of each BEOL process on NBTI of p+ gate metal oxide semiconductor field-effect transistor (PMOSFETs). It is demonstrated that NBTI is strongly dependent on the plasma enhanced nitride (PE-SiN) passivation film and H2 sintering anneal. A new process scheme of N2 annealing instead of H2 annealing prior to PE-SiN deposition is proposed and proven to be highly efficient in improving NBTI without degradation of device performance and n+ gate metal oxide semiconductor (NMOS) hot carrier lifetime.

Two-level BEOL processing for rapid iteration in MRAM development

The implementation of magnetic random access memory (MRAM) hinges on complex magnetic film stacks and several critical steps in back-end-of-line (BEOL) processing. Although intended for use in conjunction with silicon CMOS front-end device drivers, MRAM performance is not limited by CMOS technology. We report here on a novel test site design and an associated thin-film process integration scheme which permit relatively inexpensive, rapid characterization of the critical elements in MRAM device fabrication. The test site design incorporates circuitry consistent with the use of a large-area planar base electrode to enable a processing scheme with only two photomask levels. The thin-film process integration scheme is a modification of standard BEOL processing to accommodate temperature-sensitive magnetic tunnel junctions (MTJs) and poor-shear-strength magnetic film interfaces. Completed test site wafers are testable with high-speed probing techniques, permitting characterization of large numbers of MTJs for statistically significant analyses. The approach described in this paper provides an inexpensive means for rapidly iterating on MRAM development alternatives to converage on an implementation suitable for a production environment.

Characterization and optimization of a new Cu/SiN/TaN/Cu damascene architecture for metal–insulator–metal capacitors

The MIM capacitor is a key passive component for analog and RF applications. To be integrated among copper interconnect levels, MIM capacitors have to be compatible with Back End Of Line processes and materials. In this way, a new MIM Cu/Si 3N 4/TaN/Cu stack has been implemented between upper copper interconnect levels using a damascene architecture. Physical and electrical characterizations were carried out to optimize processes, leading to the RF evaluation of high-performances MIM capacitors.

Characterization and Comparison of Single and Stacked MIMC in Copper Interconnect Process for Mixed-Mode and RF Applications

This letter presents the dc and RF study and comparison on four manufacturable single- (one and dual additional masks) and stacked- (intraand multiple inter-) metal-insulator-metal capacitors (MIMCs) in a Cu dual-damascene backend of line process. The capacitors were found to exhibit low leakage and high breakdown field strength, absence of dispersive behavior, and good voltage and temperature linearity. Their quality factor (Q) values are different due to the different electrode series resistance as a result of different architectures. The stacked MIMC offers reduced chip area for the same capacitance value and is a viable manufacturable alternative for current and future precision mixed-mode capacitor incorporating SiN or high-/spl kappa/ dielectric materials.

Mechanical analysis of interconnected structures using process simulation

An elastoplastic model has been implemented in a technology computer-aided design (TCAD) program with the aim of predicting the mechanical behavior of polycrystalline materials used in silicon-based technology in microelectronics. In order to analyze microstructures combining both nonlinear viscoelastic and elastoplastic materials, we propose a computational process with quick convergence. This model is now included in a stress simulation system, thus allowing the prediction of variations in stress according to the stage of the process. The modeling takes into account not only thermal stress but also intrinsic/extrinsic stresses and etching-related stress. The stress evolution of aluminum copper (Al–Cu) periodic lines embedded within silicon dioxide has been examined. The tensile and compressive yield strengths of thin-film Al–Cu have been characterized using the von Mises criterion for various film thicknesses. Comparisons with experimental results, based on passivated and unpassivated line structures, show that von Mises yield stress is independent of linewidth. It was also found that the correct prediction of the principal stresses strongly depends on the accurate characterization of thin-film yield strength. The use of incorrect values can lead to large errors in the determination of the line aspect ratio giving the maximum principal stresses. Finally, the analysis of an industrial back end of line process is performed to demonstrate what we can now carry out with TCAD to solve stress-related reliability problems in interconnects.

MIM capacitors using atomic-layer-deposited high-/spl kappa/ (HfO/sub 2/)/sub 1-x/(Al/sub 2/O/sub 3/)/sub x/ dielectrics

Metal-insulator-metal (MIM) capacitors with (HfO/sub 2/)/sub 1-x/(Al/sub 2/O/sub 3/)/sub x/ high-/spl kappa/ dielectric films were investigated for the first time. The results show that both the capacitance density and voltage/temperature coefficients of capacitance (VCC/TCC) values decrease with increasing Al/sub 2/O/sub 3/ mole fraction. It was demonstrated that the (HfO/sub 2/)/sub 1-x/(Al/sub 2/O/sub 3/)/sub x/ MIM capacitor with an Al/sub 2/O/sub 3/ mole fraction of 0.14 is optimized. It provides a high capacitance density (3.5 fF//spl mu/m/sup 2/) and low VCC values (/spl sim/140 ppm/V/sup 2/) at the same time. In addition, small frequency dependence, low loss tangent, and low leakage current are obtained. Also, no electrical degradation was observed for (HfO/sub 2/)/sub 1-x/(Al/sub 2/O/sub 3/)/sub x/ MIM capacitors after N/sub 2/ annealing at 400/spl deg/C. These results show that the (HfO/sub 2/)/sub 0.86/(Al/sub 2/O/sub 3/)/sub 0.14/ MIM capacitor is very suitable for capacitor applications within the thermal budget of the back end of line process.