Average Network Latency Research Articles

Development of a routing method for ground-air Ad-Hoc network of special purpose

The object of the study is the process of forming control decisions to ensure the operation of the ground-air communication network routing subsystem based on neural network algorithms. The carried-out research is based on the application of the numerical-analytical approach to the selection of modern scientific and applied solutions for building management models for promising Ad-Hoc communication networks. In the Google Collab simulation environment, using the Python programming language, it was possible: firstly, to simulate the operation of a ground-to-air communication network based on previously obtained models and a routing process management system based on the FA-OSELM algorithm. Secondly, in accordance with the scenario of route construction and maintenance described in the article, to experimentally determine the communication metrics of the proposed method of intelligent routing of the ground-air Ad-Hoc special-purpose network, in order to assess its efficiency, adequacy and reliability of the results obtained. Thus, in order to evaluate the effectiveness of the proposed solutions, a comparative analysis of the application of three existing routing methods (FLCA, Q-Routing, Neuro Routing) used in Ad-Hoc networks relative to the developed method was conducted. The result of the experiment showed that the proposed routing method MAODV-FA-OSELM provides significant advantages over analogs. Thus, the method exhibits the best network throughput (2.12e+06), the lowest average network latency (0.12), the lowest packet loss (6.32), the lowest bit error rate (2.41), and the lowest overhead (0.10e+06). However, it should be noted that a promising direction of further research may be the study of the computational complexity of the routing management process and the determination of the minimum allowable representative sample of initial data to ensure online decision-making.

Performance analysis of congestion-aware Q-routing algorithm for network on chip

<p>A network on chip’s performance is greatly impacted by network congestion due to the substantial increase in latency and energy utilized. Designing routing strategies that keep the network informed of the status of traffic is made easier by machine learning techniques. In this work, a reinforcement-based congestion-aware Q-routing (CAQR) technique has been presented. The proposed algorithm performed better in comparison to the conventional XY routing method tested against the SPEC CPU2006 benchmark suite in the gem5 NoC simulator tool. The suite used has 4 benchmarks, namely, namd, lbm, leslie3d and bzip2 which can be used for the cores in the network in any combination. The tests were run with 16 cores on a 44 network with the maximum instruction count supported by the system (here 5,000). The proposed Q-routing algorithm showed an average of 19% reduction for benchmark simulation as compared to the Dimension-ordered (X-Y) routing for readings of average packet latency which is a crucial factor in determining a network’s efficiency. The analysis also shows an average reduction of 24%, 10%, 23% and 47% in terms of average packet network latency, average flit latency, average flit network latency and average energy consumption across various benchmarks.</p>

Efficient application mapping approach based on grey wolf optimization for network on chip

In modern chip designs with multiple processors, network-on-chip (NoC) has emerged as a critical solution, offering scalability, flexibility, modularity, and efficiency. However, a significant challenge in application mapping is minimizing communication costs as they directly affect performance and energy consumption. Although several mapping algorithms have been developed, they often suffer from complexity, suboptimal performance, and slow convergence. To address these challenges, this paper proposes a novel approach for mapping using the grey wolf optimization (GWO) technique inspired by nature. The proposed GWO-based mapping approach for NoC (GNoC) is augmented with an effective clustering-based initial mapping strategy, further enhancing its capabilities. Furthermore, a second heuristic algorithm is introduced, incorporating a modified GWO method with polynomial regression (GNoC-PR). This modification optimizes the runtime efficiency and enhances the overall mapping quality. The proposed method was evaluated through comprehensive simulations and compared with state-of-the-art solutions. The results demonstrate that the proposed algorithm outperforms existing methods in several key metrics, including a power consumption reduction of 19.7%, energy efficiency improvement of 17%, and a significant 40% decrease in computational overhead on average. To validate the effectiveness of our mapping technique, we evaluated both embedded and synthetic applications, considering various metrics such as communication cost, average network latency, and power consumption.

Fast and Accurate NoC Latency Estimation for Application-Specific Traffics via Machine Learning

Latency is one of the critical performance metrics for Networks-on-Chips (NoCs). When designing an NoC, the designers have to explore enormous design parameters and various traffic patterns, thus a fast and accurate latency estimator is essential to explore the large design space. In this paper, we present an ideal neural network-based methodology for latency estimation in NoCs, especially for application-specific traffics. By inputting the sequence of extracted traffic features and NoC parameters, the neural network model will infer the corresponding average network latency in a fast while accurate way. Instead of training one neural network model for each benchmark from scratch, we adopt transfer learning to train the network model for a new benchmark from another trained one. Experimental results on a set of widely used application-specific NoC benchmarks show that, our method can achieve an average estimation accuracy of 95%, and a 17.1X speedup for large NoCs compared to BookSim2 simulations. Our method can also achieve 20% to 70% improvement in accuracy over the other state-of-art machine learning-based works.

SpecMap: An efficient spectral partitioning based static application mapping algorithm for 2D mesh NoCs

SummaryNetwork‐on‐chip (NoC) is adopted as a flexible and effective communication backbone by multiprocessor systems with core counts ranging from a few to hundreds. The performance of NoC based systems greatly rely on the communication between cores when two dependent tasks of an application are mapped to these cores. Hence, application mapping becomes a critical issue in NoC‐based systems as it affects the overall performance of the system. Application mapping aims to reduce the communication among the cores by carefully mapping the highly communicating tasks. Most of the existing static mapping approaches consider only single‐task platforms. In this article, we propose an efficient multi‐task static mapping algorithm called , for regular 2D NoC systems. consists of three stages namely, (i) graph partitioning, (ii) topology clustering, and (iii) mapping. In the graph partitioning stage, accurately identifies and groups the highly communicating tasks based on spectral graph partitioning. Then, the clustering and mapping stages allocate the most communicating tasks in the same or adjacent multi‐tasking cores. It also eliminates the interference between multiple applications by mapping them into different clusters of the NoC network. Simulations of have been conducted on different synthetic and real‐life applications using Gem5 simulator. The simulation results show considerable improvements for SpecMap in terms of communication cost, average network latency, energy consumption, throughput, and execution time as compared to the state‐of‐the‐art algorithms.

Laser Intersatellite Link Range in Free-Space Optical Satellite Networks: Impact on Latency

Laser communication terminals for establishing laser intersatellite links (LISLs) are in high demand by companies, such as SpaceX and Telesat, who want to equip their satellites with LISLs to realize free-space optical satellite networks (FSOSNs). Such terminals offer LISLs with ranges spanning from 4500 to 45,000 km. How does LISL range affect network latency in FSOSNs? To investigate this effect, we employ the satellite constellation for Phase I of SpaceX's Starlink, and examine six different LISL ranges for satellites in this constellation in three different scenarios for long-distance intercontinental data communications. We observe that the satellite connectivity and thereby the network connectivity improves with an increase in the LISL range as more and farther satellites become available within the LISL range of a satellite. A higher LISL range leads to better shortest paths offering lower average network latency. Furthermore, improvement in average network latency with increase in LISL range is seen in all scenarios.

Improved secure dynamic bit standard technique for a private cloud platform to address security challenges

The numerous technologies and procedures used to safeguard private cloud infrastructure are private cloud security. Despite multitenant public cloud environments, resources are dedicated to individual companies in a private cloud. Cloud computing uses several data security mechanisms, including authentication and identification, access control, encryption, secure deletion, integrity checking, and data masking. Cloud computing relies heavily on security and traffic management. Because data must be transferred from a local computer to a remote computer when using a cloud computing service, data protection is becoming an increasingly important security problem. Research on cloud computing-based secure dynamic bit standard (CC-SDBS) technology has increased data security. This technique’s cryptographic algorithms (CA) improve cloud computing security. As a result of the private cloud security level algorithm (PCSLA), the client’s private data can be easily accessed in the cloud. For the client’s private cloud data, PCSLA provides dynamic security measures. Cloud computing applications can use the tests’ better data security in the future. The proposed algorithm’s testing results have shown a noticeable improvement in cipher size and execution time compared with other commonly used cloud computing. Numerical results revealed that CC-SDBS improved average energy consumption by 20%, average network latency by 25%, average key generation time analysis by 4.3%, and average network use by 15%.

An Intelligent Routing for Internet of Things Mesh Networks

AbstractInternet of Things (IoT) is gaining popularity due to its complex network architecture, formed by the tremendous connection of objects. Sensors used in different IoT applications are installed in unfavorable terrains and conditions. Since each sensor node can sense, compute, and promote wireless communication, a novel intelligent routing algorithm is required, as the traditional ones do not fulfill the current network requirements. Reinforcement learning models can help overcome the wireless network's challenges faced during routing due to its dynamicity by selecting and adapting weights that optimize the paths based on the requirement of the applications and operating conditions. In this article, a routing agent with Q‐learning is proposed that adjusts the routing policy of a network based on local information to converge toward an optimal solution by maintaining the overall balance between latency and the network's lifetime. A reward is given to an agent that increases the network lifetime and reduces the average network latency. The evaluation of the proposed model was done using network simulators (NS‐2) on different network scenarios that showed improved results in terms of network lifetime compared to centralized minimum angle and distributed minimum angle.

Load Based Dynamic Priority Arbiter for NoC Architecture

The evolution of Very Large Scale Integration (VLSI) and the semiconductor industry have led to the focus on multicore architectures. Network on Chip (NoC) is one of such arrangement which is an interconnection framework comprised of cores, routers, and links. The output port for each request from the input port must be computed, and the output channel must be reserved for the next router. However, the same output port can be requested by more than one input port, but only one request can be granted at a time. Multiple requests for a single output channel will lead to congestion of the packets, thereby increasing the network latency and leading to packet losses. The arbiter selects any one of the input ports and grants permission to use the requested output port while putting the other input port requests to wait. For a congestion-free traversal of packets and to avoid dropping of packets, a Load based Dynamic Priority Arbiter (LDPA) with dynamically changing priorities during run time based on the input port load has been proposed. The proposed customized arbiter LDPA works based on the updates made in the reservations of each input port. The priority of each input port is given according to the average load. More weight is allotted to the highly loaded input ports. By randomization, the chance is given to the lower priority input ports to reduce starvation and hence latency. With the use of the proposed LDPA, the average network latency is reduced by about 15.98% when compared to that of baseline FIFO arbiter, without any compromise in power and throughput.

Reliable Fault Tolerant-Based Multipath Routing Model for Industrial Wireless Control Systems

Communication in industrial wireless networks necessitates reliability and precision. Besides, the existence of interference or traffic in the network must not affect the estimated network properties. Therefore, data packets have to be sent within a certain time frame and over a reliable connection. However, the working scenarios and the characteristics of the network itself make it vulnerable to node or link faults, which impact the transmission reliability and overall performance. This article aims to introduce a developed multipath routing model, which leads to cost-effective planning, low latency and high reliability of industrial wireless mesh networks, such as the WirelessHART networks. The multipath routing model has three primary paths, and each path has a backup node. The backup node stores the data transmitted by the parent node to grant communication continuity when primary nodes fail. The multipath routing model is developed based on optimal network planning and deployment algorithm. Simulations were conducted on a WirelessHART simulator using Network Simulator (NS2). The performance of the developed model is compared with the state-of-the-art. The obtained results reveal a significant reduction in the average network latency, low power consumption, better improvement in expected network lifetime, and enhanced packet delivery ratio which improve network reliability.

Temporary Laser Inter-Satellite Links in Free-Space Optical Satellite Networks

Laser inter-satellite links (LISLs) between satellites in a free-space optical satellite network (FSOSN) can be divided into two classes: permanent LISLs (PLs) and temporary LISLs (TLs). TLs are not desirable in next-generation FSOSNs (NG-FSOSNs) due to high LISL setup time, but they may become feasible in next-next-generation FSOSNs (NNG-FSOSNs). Using the satellite constellation for Phase I of Starlink, we study the impact of TLs on network latency in an NG-FSOSN (which has only PLs) versus an NNG-FSOSN (which has PLs and TLs) under different long-distance inter-continental data communications scenarios, including Sydney–Sao Paulo, Toronto–Istanbul, Madrid–Tokyo, and New York–Jakarta, and different LISL ranges for satellites, including 659.5 km, 1,319 km, 1,500 km, 1,700 km, 2,500 km, 3,500 km, and 5,016 km. It is observed from the results that TLs provide higher satellite connectivity and thereby higher network connectivity, and they lead to lower average network latency for the NNG-FSOSN compared to the NG-FSOSN in all scenarios at all LISL ranges. In comparison with the NG-FSOSN, the improvement in latency with the NNG-FSOSN is significant at LISL ranges of 1,500 km, 1,700 km, and 2,500 km, where the improvement is 16.83 ms, 23.43 ms, and 18.20 ms, respectively, for the Sydney–Sao Paulo inter-continental connection. For the Toronto–Istanbul, Madrid–Tokyo, and New York–Jakarta inter-continental connections, the improvement is 14.58 ms, 23.35 ms, and 23.52 ms, respectively, at the 1,700 km LISL range.

ICLA Unit: Intra-Cluster Locality-Aware Unit to Reduce L2 Access and NoC Pressure in GPGPUs

As the number of streaming multiprocessors (SMs) in GPUs increases, in order to gain better performance, the reply network faces heavy traffic. This causes congestion on Network-on-Chip (NoC) routers and memory controller’s (MC) buffers. By taking advantage of cooperative thread arrays (CTAs) that are scheduled locally in clusters, there is a high probability of finding the same copy of data in other SM’s [Formula: see text] cache in the same cluster. In order to make this feasible, it is necessary for the SMs to have access to local [Formula: see text] cache of the neighboring SMs. There is a considerable congestion in NoC due to unique traffic pattern called many-to-few-to-many. Thanks to the reduced number of requests that is attained by our proposed Intra-Cluster Locality-Aware (ICLA) unit, this congested replying network traffic becomes many-to-many traffic pattern and the replied data goes through the less-utilized core-to-core communication that mitigates the NoC traffic. The proposed architecture in this paper has been evaluated using 15 different workloads from CUDA SDK, Rodinia, and ISPASS2009 benchmarks. The proposed ICLA unit has been modeled and simulated in the GPGPU-Sim. The results show about 23.79% (up to 49.82%) reduction in average network latency, 15.49% (up to 36.82%) reduction in average [Formula: see text] cache access, and 18.18% (up to 58.1%) average improvement in the instruction per cycle (IPC).

A Novel Genetic Service Function Deployment Management Platform for Edge Computing

The various applications of the Internet of Things and the Internet of Vehicles impose high requirements on the network environment, such as bandwidth and delay. To meet low-latency requirements, the concept of mobile edge computing has been introduced. Through virtualisation technology, service providers can rent computation resources from the infrastructure of the network operator, whereas network operators can deploy all kinds of service functions (SFs) to the edge network to reduce network latency. However, how to appropriately deploy SFs to the edge of the network presents a problem. Apart from improving the network efficiency of edge computing service deployment, how to effectively reduce the cost of service deployment is also important to achieve a performance-cost balance. In this paper, we present a novel SF deployment management platform that allows users to dynamically deploy edge computing service applications with the lowest network latency and service deployment costs in edge computing network environments. We describe the platform design and system implementation in detail. The core platform component is an SF deployment simulator that allows users to compare various SF deployment strategies. We also design and implement a genetic algorithm-based service deployment algorithm for edge computing (GSDAE) in network environments. This method can reduce the average network latency for a client who accesses a certain service for multiple tenants that rent computing resources and subsequently reduce the associated SF deployment costs. We evaluate the proposed platform by conducting extensive experiments, and experiment results show that our platform has a practical use for the management and deployment of edge computing applications given its low latency and deployment costs not only in pure edge computing environments but also in mixed edge and cloud computing scenarios.

READ: Robustness-Oriented Edge Application Deployment in Edge Computing Environment

In recent years, edge computing has emerged as a prospective distributed computing paradigm that overcomes several limitations of cloud computing. In the edge computing environment, a service provider can deploy its application instances on edge servers at the edge of the network to serve its own users with low latency. Given a limited budget <inline-formula><tex-math notation="LaTeX">$\mathcal {K}$</tex-math></inline-formula> for deploying applications on the edge servers in a particular geographical area, a number of approaches have been proposed very recently to determine the optimal deployment strategy that achieves various optimization objectives, e.g., to maximize the servers’ coverage, to minimize the average network latency, etc. However, the robustness of the services collectively delivered by the service provider’s applications deployed on the edge servers has not been considered at all. This is a critical issue, especially in the highly distributed, dynamic and volatile edge computing environment. In this article, we make the first attempt to tackle this challenge. Specifically, we formulate this <i>Robustness-oriented Edge Application Deployment</i> (READ) problem as a constrained optimization problem and prove its <inline-formula><tex-math notation="LaTeX">$\mathcal {NP}$</tex-math></inline-formula> -hardness. Then, we provide an integer programming based approach named READ- <inline-formula><tex-math notation="LaTeX">$\mathcal {O}$</tex-math></inline-formula> for solving this problem precisely. We also provide an approximation algorithm, namely READ- <inline-formula><tex-math notation="LaTeX">$\mathcal {A}$</tex-math></inline-formula> , for finding near-optimal solutions to large-scale READ problems efficiently. We prove its approximation ratio is not worse than <inline-formula><tex-math notation="LaTeX">$\mathcal {K}/2$</tex-math></inline-formula> , which is a constant regardless of the total number of edge servers. We evaluate our approaches experimentally on a widely-used real-world dataset against five representative approaches. The experiment results demonstrate that our approaches can solve the READ problem effectively and efficiently.

Stochastic multi-objective Pareto-optimization framework for fully automated ab initio network-on-chip design

Abstract With the advent of multi-core processors, network-on-chip design has been crucial in addressing network performances, such as bandwidth, power consumption, and communication delays when dealing with on-chip communication between the increasing number of processor cores. As the numbers of cores increase, network design becomes inherently more complex. Therefore, there is a critical need in soliciting computer aid in determining network configurations that afford optimal performance given multi-objectives, such as resource and design constraints. We have devised a stochastic multi-objective Pareto-optimization framework that fully automatically explores the space of possible network configurations to determine optimal network latencies, power consumption, and the corresponding link allocations, i.e., the actual network-on-chip design, ab initio with only the number of routers given. For a given number of routers, average network latency and power consumption as example performance objectives can be displayed in form of Pareto-optimal fronts, thus not only offering a powerful automatic network-on-chip design tool, but also affording trade-off studies for the chip designers.

Latency and Lifetime Enhancements in Industrial Wireless Sensor Networks: A Q-Learning Approach for Graph Routing

Industrial wireless sensor networks usually have a centralized management approach, where a device known as network manager is responsible for the overall configuration, definition of routes, and allocation of communication resources. Graph routing is used to increase the reliability of communication through path redundancy. Some of the state-of-the-art graph-routing algorithms use weighted cost equations to define preferences on how the routes are constructed. The characteristics and requirements of these networks complicate to find a proper set of weight values to enhance network performance. Reinforcement learning can be useful to adjust these weights according to the current operating conditions of the network. In this article, we present the Q-learning reliable routing with a weighting agent approach, where an agent adjusts the weights of a state-of-the-art graph-routing algorithm. The states of the agent represent sets of weights, and the actions change the weights during network operation. Rewards are given to the agent when the average network latency decreases or the expected network lifetime increases. Simulations were conducted on a WirelessHART simulator considering industrial monitoring applications with random topologies. Results show, in most cases, a reduction of the average network latency while the expected network lifetime and the communication reliability are at least as good as what is obtained by the state-of-the-art graph-routing algorithms.

A New Algorithm for Controller Placement in SDN

SDN network supports centralized network management by splitting control plane and data plane of forwarding devices and places the network intelligence in a software entity called controller. The controller can be placed in selective places of network to effectively monitor and control network activities. Large scale network needs multiple controller to manage control activities of network. In order to identify the optimum number of controllers and its effective locations in the network, a new algorithm is proposed using cut-vertex concept from graph theory. The proposed algorithm is simulated using Mininet SDN emulator. To study the performance of the proposed algorithm, multiple scenarios were used in the simulation and performance was analysed using parameters viz., flow installation time, average latency of network, throughput.

A novel packet exchanging strategy for preventing HoL-blocking in fat-trees

Fat-tree interconnection network is one of the most popular and widely-used networks in massively parallel processing systems. Its superb characteristics such as deterministic routing, in-order delivery and providing the same performance as adaptive routing methods have made it an attractive interconnection network. However, due to its deterministic routing as well as simultaneously usage of switch links, Head of Line (HoL)-blocking may occur in buffers during high traffic workload. In order to mitigate this problem, in this paper, a novel strategy in switch buffers based on the blocking of the paths is proposed. It has been shown that combining packets with different blocked paths can reduce congestion by packet exchanging. To exchange packets, we used short and medium depth buffers and also considered two exchanging states; consecutive and non-consecutive. This novel strategy provides a trade-off between the performance improvement and reduction of buffers’ depths, while doesn’t change the delivery order of the packets. Simulation results show that in comparison with one buffer in each switch, 22% and 33% average network latency is improved with consecutive and one unit non-consecutive exchanging states respectively and also the depth of buffers in each switch is reduced 43.75% and 37.5% in comparison with multiple buffers.

Extending BookSim2.0 and HotSpot6.0 for power, performance and thermal evaluation of 3D NoC architectures

With the increase in number and complexity of cores and components in Chip-Multiprocessors (CMP) and Systems-on-Chip (SoCs), a highly structured and efficient on-chip communication network is required to achieve high-performance and scalability. Network-on-Chip (NoC) has emerged as a reliable communication framework in CMPs and SoCs. Many 2-D NoC architectures have been proposed for efficient on-chip communication. Cycle accurate simulators model the functionality and behaviour of NoCs by considering micro-architectural parameters of the underlying components to estimate performance, power and energy characteristics. Employing NoCs in three-dimensional integrated circuits (3D-ICs) can further improve performance, energy efficiency, and scalability characteristics of 3D SoCs and CMPs. Minimal error estimation of energy and performance of NoC components is crucial in architecture trade-off studies. Accurate modeling of re:Horizontal and vertical links by considering micro-architectural and physical characteristics reduces the error in power and performance estimation of 3D NoCs. Additionally, mapping the temperature distribution in a 3D NoC reduces estimation error.This paper presents the 3D NoC modelling capabilities extended in two existing state-of-the-art simulators, viz., the 2D NoC Simulator - BookSim2.0 and the thermal behaviour simulator - HotSpot6.0. With the extended 3D NoC modules, the simulators can be used for power, performance and thermal measurements through micro-architectural and physical parameters. The major extensions incorporated in BookSim2.0 are: Through Silicon Via power and performance models, 3D topology construction modules, 3D Mesh topology construction using variable X, Y, Z radix, tailored routing modules for 3D NoCs. The major extensions incorporated in HotSpot6.0 are: parameterized 2D router floorplan, 3D router floorplan including Through Silicon Vias (TSVs), power and thermal distribution models of 2D and 3D routers.Using the extended 3D modules, performance (average network latency), and energy efficiency metrics (Energy-Delay Product) of variants of 3D Mesh and 3D Butterfly Fat Tree topologies have been evaluated using synthetic traffic patterns. Results show that the 4-layer 3D Mesh is 2.2 × better than 2-layer 3D Mesh and 4.5 × better than 3D BFT variants in terms of network latency. 3D Mesh variants have the lowest Energy Delay Product (EDP) compared to 3D BFT variants as there is an 80% reduction in link lengths and up to 3 × more TSVs. Another observation is that the EDP of the 4-layer 3D BFT (with transpose traffic) is 1.5 × the EDP of the 4-layer 3D Mesh (with transpose traffic). Further optimizations towards a tailored 3D BFT for transpose traffic could reduce this EDP gap with the 4-layer 3D Mesh. From the 3D NoC heat maps, it was found that the edge routers in the floorplan of the tested 3D Mesh and 3D BFT topologies have the least ambient temperature.

Low latency multicasting architecture implemented using new network topology

An important service in distributed systems, as multiprocessors, is the ability to transmit multicast messages. Cache coherence protocols and parallel algorithms are examples of applications requiring multicast messages. Several algorithms have been developed to implement multicasting namely the path based, and the tree based. These algorithms were able to ease the rapid saturation effect generated by such type of transmission. However, for some applications, these algorithms are not always efficient, and the multicast service might still generate the network saturation for low data loads. That's why recent studies have tried to apply these routing algorithms using a new network topology based on 3D integrated circuit technology (3DIC) . However, the 3DIC has not reached maturity because of the use of multiple number of TSV (through silicon vias).In this paper, we demonstrate the benefits of implementing adaptive multicast algorithm on a VRNOC architecture. Simulations and hardware synthesis results show that the proposed on-chip network architecture provides significant improvements in average network latency (15%) and resources (33% in number of links) than a fully 3D NOC.