Avalanche Stress Research Articles

Suppression Effect of Split-Gate Structure on Repetitive Avalanche Stress Induced Degradation for SiC MOSFETs

Suppression Effect of Split-Gate Structure on Repetitive Avalanche Stress Induced Degradation for SiC MOSFETs

Review on the Reliability Mechanisms of SiC Power MOSFETs: A Comparison Between Planar-Gate and Trench-Gate Structures

To clarify the current research situation and offer a better understanding of the reliability for silicon carbide (SiC) power metal-oxide-semiconductor field-effect transistors (MOSFETs), a comparison among the reliability mechanisms between planar-gate and trench-gate SiC power MOSFETs, which have not been comprehensively summarized, is made in this work. The latest studies focusing on the reliability issues of commercial SiC MOSFET products, including the planar-gate device, the double-trench device and the asymmetric trench-gate device, are reviewed. For the existing of the gate trenches and the unique structures protecting them, SiC trench-gate MOSFETs express quite different instability phenomena from the planar-gate ones under various ultimate and long-term electro-thermal stresses. The influences of these stresses closely related to the practical operation conditions on SiC power MOSFETs, including the avalanche stress, the short-circuit (SC) stress, the surge current stress of the body diode, and the switching stress, are discussed and reviewed in details.

Impact Analysis of Off-State Avalanche-Breakdown Stress on 650 V-Class Superjunction MOSFET

In this work, the reliability degradation of a 650 V-class superjunction (SJ) MOSFET under continuous violent OFF-state avalanche-breakdown stress is studied. Decreased threshold voltage and increasing saturation current have been observed which are attributed to the injection of hot holes below the trench bottom into the gate oxide layer. High-energy electrons and holes are generated under OFF-state avalanche stress leading to accelerated and violent collision ionization. The body diode suffers from severe avalanche breakdown leading to heat generation by collision ionization. In addition, the injection of hot holes is further enhanced with the assistance of the electrical field at the bottom of the gate. These phenomena are further analyzed by experimental characterizations and theoretical simulation using TCAD tools. Our comprehensive study on the reliability degradation behaviors of SJ devices under OFF-state avalanche-breakdown stress can be instructive in future device optimization and failure analysis.

Investigation of Failure Mechanisms of 1200 V Rated Trench SiC MOSFETs Under Repetitive Avalanche Stress

In this article, the repetitive avalanche ruggedness of silicon carbide metal–oxide–semiconductor field-effect transistors (MOSFETs) with asymmetric trench (AT) and double trench (DT) structure is investigated experimentally. The different failure mechanisms, i.e., thermal-induced fatigue or field oxide breakdown for AT-MOSFET and electric field induced gate oxide degradation or breakdown for DT-MOSFET, are verified by device decapsulation and TCAD simulation. Different from the transient failure in single-pulse avalanche test, the degradation and failure under repetitive avalanche stress are related to the accumulation of gate oxide traps or thermal stress. Under high energy ratio condition, DT-MOSFET fails with shorted gate-drain terminal after only 2k unclamped inductive switching (UIS) cycles. Microscopic failure analysis shows an obvious crack through the bottom gate oxide to N-drift layer, whereas the electrical parameters of AT-MOSFET remain stable during 12k UIS cycles until gate leakage current of 10 mA exceeds the failure threshold of devices. The thermal-induced field oxide breakdown is found upon polysilicon gate in AT-MOSFET. Under low energy ratio condition, over 5% reduction of threshold voltage and <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> -state resistance is observed in DT-MOSFET due to hot holes injection in gate oxide. However, the threshold voltage of AT-MOSFET is almost constant and an approximately 10% increase of <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> -state resistance caused by thermal fatigue is observed.

Degradation and breakdown behaviors of SGTs under repetitive unclamped inductive switching avalanche stress

The repetitive unclamped inductive switching (UIS) avalanche stress is conducted to investigate the degradation and breakdown behaviors of conventional shield gate trench MOSFET (C-SGT) and P-ring SGT MOSFETs (P-SGT). It is found that the static and dynamic parameters of both devices show different degrees of degradation. Combining experimental and simulation results, the hot holes trapped into the Si/SiO2 interface and the increase of crystal lattice temperature should be responsible for the degradation and breakdown behaviors. Moreover, under repetitive UIS avalanche stress, the reliability of P-SGT overcomes that of C-SGT, benefitting from the decreasing of the impact ionization rate at bottom of field oxide caused by the existence of P-ring.

Influence of Different Device Structures on the Degradation for Trench-Gate SiC MOSFETs: Taking Avalanche Stress as an Example.

The variations in the degradation of electrical characteristics resulting from different device structures for trench-gate SiC metal-oxide-semiconductor field effect transistors (MOSFETs) are investigated in this work. Two types of the most advanced commercial trench products, which are the asymmetric trench SiC MOSFET and the double-trench SiC MOSFET, are chosen as the targeted devices. The discrepant degradation trends caused by the repetitive avalanche stress are monitored. For the double-trench device, the conduction characteristic improves while the gate-drain capacitance (Cgd) increases seriously. It is because positive charges are injected into the bottom gate oxide during the avalanche process, which are driven by the high oxide electronic field (Eox) and the high impact ionization rate (I.I.) there. Meanwhile, for the asymmetric trench SiC MOSFET, the I–V curve under the high gate bias condition and the Cgd remain relatively stable, while the trench bottom is well protected by the deep P+ well. However, it’s threshold voltage (Vth) decreases more obviously when compared with that of the double-trench device and the inclined channel suffers from more serious stress than the vertical channel. Positive charges are more easily injected into the inclined channel. The phenomena and the corresponding mechanisms are analyzed and proved by experiments and technology computer-aided design (TCAD) simulations.

Investigation and Modeling of the Avalanche Failure Mechanism of 1.2-kV 4H-SiC JMOS

We studied the avalanche failure mechanism of a 1.2-kV 40-A monolithic junction barrier-controlled Schottky-diode-integrated SiC MOSFET (JMOS) using a single-pulse unclamped inductive switching (UIS) test to evaluate its avalanche ruggedness. The avalanche electro-thermal (AET) model was established to illustrate the transient electro-thermal behavior in single-pulse avalanche stress to present the thermal runaway failure process of the JMOS and obtain the dynamic temperature function during UIS. The AET model also proposes a critical failure temperature of 1240 K for determining the failure region. The electro-thermal TCAD mixed mode simulation study demonstrates that the critical temperature and failure area appear in the Schottky barrier diode (SBD) region, which is also verified by a focused-ion beam (FIB) microsection analysis. The enhancement of avalanche ruggedness of JMOS can be achieved by adjusting the properties of the SBD region.

Investigations on the Resistance Reduction Effect of Double-Trench SiC MOSFETs under Repetitive Avalanche Stress

The unexpected resistance reduction effect of double-trench SiC MOSFETs under repetitive avalanche stress is investigated in this work. After enduring repetitive avalanche stress, the ON-state drain-source resistance (Rdson) of the device decreases. With the help of TCAD simulations, the dominant mechanism is proved to be the injection of positive charges into the gate trench bottom oxide, which is almost irreversible under zero-voltage bias condition at room temperature. For the injected positive charges attract extra electrons just beneath the gate trench bottom, where the carriers pass through under ON state, the resistivity there is reduced, improving the conduction capability of the device. Moreover, an optimization method is proposed. Since the impact ionization rate (I.I.) and the vertical oxide electric field (E⊥) along the gate trench bottom oxide interface contribute to the injection of positive charges, it is recommended to make the bottom oxide thicker to suppress this effect.

Breakdown Voltage Walk-in Phenomenon and Optimization for the Trench-Gate p-Type VDMOS Under Single Avalanche Stress

An anomalous breakdown voltage (BV) walk-in phenomenon of the trench-gate p-type vertical double-diffused metal–oxide–semiconductor (VDMOS) after single avalanche stress has been experimentally investigated. It is found that the BV of the VDMOS is decreased after the single avalanche stress, while other electrical parameters remain unchanged. T-CAD simulations and emission microscope (EMMI) analysis have been carried out. As a result, the shift of the breakdown point of the VDMOS, which results in the hot hole injection and trapping at the termination region, should be responsible for the BV degradation. A novel device structure with different trench depths in the termination region for the trench-gate p-type VDMOS is proposed to suppress the BV walk-in phenomenon.

Modeling Avalanche Induced Degradation for 4H-SiC Power MOSFETs

In this letter, a model that predicates the degradation of 4H-SiC power metal-oxide-semiconductor field-effect transistors under repetitive avalanche stress is proposed. Since positive charges are injected into the gate oxide interface of the JFET region, the gate-drain capacitance $(C_{gd})$ is chosen as the targeted parameter to quantify the avalanche induced degradation. The relationship between the increment of the $C_{gd}$ and the injected charge density is calculated and validated to demonstrate the rationale of the model. It is found that the increment of $C_{gd}$ has a linear relationship with the logarithm of the total avalanche energy ( E AV) dissipated on the device. Excellent agreement is also achieved between the simulated degraded data and the measured one, further proving the accuracy of the proposed degradation model.

Review and analysis of SiC MOSFETs’ ruggedness and reliability

SiC MOSFETs (silicon carbide metal-oxide semiconductor field-effect transistors) are replacing Si insulated gate bipolar transistors in many power conversion applications due to their superior performance. However, ruggedness and reliability of SiC MOSFETs are still big concern for their widespread applications in the market, especially in safety-critical applications. The objective of this study is to provide a comprehensive picture on the ruggedness and reliability of commercial SiC MOSFETs, discover their failure or degradation mechanism, and propose some possible mitigation methods through both literature survey and in-depth analysis. The ruggedness of SiC MOSFETs discussed here includes short-circuit (SC) ruggedness, avalanche ruggedness, and their failure mechanism. The reliability issues include gate oxide reliability, degradation under high-temperature bias stress, repetitive SC stress, avalanche stress, power cycling stress, body diode's surge current stress, and their degradation mechanism. Furthermore, this study discusses methods and solutions to improve their ruggedness and reliability.

Verification of Single-Pulse Avalanche Failure Mechanism for Double-Trench SiC Power MOSFETs

The failure mechanism of double-trench silicon carbide (SiC) power metal-oxide-semiconductor field-effect transistors (MOSFETs) under single-pulse avalanche stress is verified. Instead of the widely reported burning out failure mechanism for planar-gate devices, double-trench SiC power MOSFETs suffer from a totally different failure mechanism, as they can only endure a much lower maximum single-pulse avalanche energy (E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">as</sub> ). It is found that during the avalanche process, obvious gate leakage current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> ) appears, which is resulted from the high impact ionization rate and high electric field along the gate trench bottom oxide interface, especially the trench corners. The I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> continuously grows along with the increase in the peak load current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> peak</sub> ), eventually leading to the breakdown of the trench bottom gate oxide under avalanche status. By increasing the value of gate resistor (R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> ), the I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> raises the gate-source voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> gs</sub> ) during the avalanche process, forcing the channel region in an inversion state. Part of the avalanche current is then diverted into the forward conductive current, changing the failure mode from breakdown of the gate oxide to burning out of the entire device. Moreover, the influence of different avalanche stress conditions, including the di/dt and the ambient temperature (T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">a</sub> ), on the single-pulse avalanche endurance capability of double-trench SiC power MOSFETs is investigated. All the samples express a similar failure phenomenon. The higher the di/dt is, the shorter the avalanche time the device can endure. This is because the higher I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">peak</sub> results in a higher I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> during the avalanche process, leading to early failure of the gate oxide. However, the T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">a</sub> rarely influences the E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> as</sub> of the device, indicating that the single-pulse avalanche-induced failure of double-trench SiC power MOSFETs has little business with the melting of the lattice or package, demonstrating the correctness of the failure mechanism proposed in this article.

Investigation of the avalanche ruggedness of SiC MPS diodes under repetitive unclamped-inductive-switching stress

State of the art freewheeling diodes are connected antiparallel with a switch like IGBT or MOSFET and for latter also with the internal body diode. The diodes have to be rugged enough to overcome temporary overvoltage and overcurrent conditions during transient operation. SiC merged pin Schottky (MPS) diodes are one of the superior contenders and thus it is essential to make investigations under high avalanche energy. In this work, an avalanche ruggedness of 20 A/1.2 kV SiC MPS diodes was investigated far beyond the specified maximum ratings of the device under unclamped inductive switching (UIS) measurement. The function of avalanche energy versus applied inductance was investigated under single event avalanche stress. The reliability under high repetitive avalanche energy was studied in detail. A forward voltage drift, change in the Schottky junction voltage and increase in the leakage current was observed after the high repetitive avalanche stress far beyond the safe operating area. Detailed failure analysis was made, focusing on the degradation of the metallization and possible stacking faults (SFs) in the SiC bulk. Furthermore, the temperature was determined as a function of the blocking voltage during avalanche stress.

Safe Operation of Maximum Temperature for Planar Gate SiC Mosfet under Avalanche Stress Shock

The silicon carbide (SiC) metal-oxide-semiconductor-field-effect transistors (MOSFET) exhibits its superior dynamic characteristic due to significant shrink of chip size as a result of SiC wide band gap. This advantage transfers to the fast switching speed (i.e., higher dI/dt, dV/dt) of device, promoting high efficient and high power dense applications. When turn-off process, however, the sharp current variation may result in SiC MOSFET suffering avalanche stress. This shock becomes one of reliability issues for SiC MOSFET, influencing the reliability of the converter further. Recently, the avalanche related studies of SiC MOSFET raise extensive investigations and discussions. It is found that the achieved avalanche energy (E av) of a specific SiC MOSFET is varied based on different load in the unclamped inductive switching (UIS) test and the underlying avalanche breakdown cause is relevant to thermal runaway. Therefore, it is of necessity to fully understand the role of temperature in the SiC MOSFET during avalanche mode. Meanwhile, a relatively direct and concise indicator to estimate the avalanche failure of SiC MOSFET is expected in practical scenario, even though various components are entangled inside the subject during avalanche shock. In this paper, avalanche capability of 1200V CREE SiC MOSFET characterizing planar gate structure is assessed using various load (3.6mH, 1.1mH, 0.3mH) UIS and heat induced avalanche failure is analyzed. Through the SiC MOSFET suitable UIS test bench, the withstanding avalanche energy of 1200V rated CREE MOSFET (planar gate) under various avalanche shocks are achieved. Furthermore, verified by the experimentally calibrated TCAD simulation based-on the subject, the underlying mechanism for the avalanche breakdown is revealed. Through the investigation of temperature distribution inside device during UIS process, it confirms that the maximum temperature play predominant role in avalanche damage. When the temperature located at interface of Pbase/N drift region rises up to melting temperature of metal system of source, i.e., around 900K, it results in avalanche catastrophic failure of device. Based on this failure mechanism, accordingly we establish a maximum temperature limit (T av(max)) of SiC MOSFET to guarantee safe operation in terms of avalanche shock. The indicator T av(max) is defined as a critical limit of avalanche damage inside planar gate SiC MOSFET.

Comprehensive Investigations on Degradations of Dynamic Characteristics for SiC Power &lt;sc&gt;MOSFET&lt;/sc&gt;s Under Repetitive Avalanche Shocks

In this work, degradations of dynamic characteristics for silicon carbide (SiC) power metal-oxide-semiconductor field-effect transistors under repetitive avalanche shocks are investigated in details. With the help of Silvaco TCAD simulations, gate capacitance versus gate voltage ( Cg – Vg ) measurement, and three-terminal charge pumping test, the main damaged position is demonstrated to be the SiC/SiO2 interface along junction FET (JFET) region instead of the body diode where most of the avalanche current passes through. Dominant avalanche degradation mechanism is then confirmed to be the injection of holes into the gate oxide above the JFET region. Since the channel region and the main junction of body diode are not seriously damaged by the avalanche stress, static parameters all remain stable. Meanwhile, due to the injection of holes, the depletion layer beneath the JFET region gets thinner, resulting in the increase of gate-drain capacitance ( C gd) under low drain-source voltage ( V ds) bias condition. It further takes responsibilities for the increments in input capacitance ( Ciss ), output capacitance ( Coss ), and reverse transfer capacitance ( Crss ). Moreover, it results in the extension of Miller plateau. Therefore, the increase of gate charge and delay of turn- off time after being stressed by repetitive avalanche shocks are monitored. Moreover, turn- on and turn- off dissipated energies after different unclamped-inductive-switching stress cycles are extracted. They are rarely influenced by the stress for the overlapping areas of voltage and current during switching procedures are relatively stable.

Investigations on the Degradations of Double-Trench SiC Power MOSFETs Under Repetitive Avalanche Stress

The degradations of electrical parameters for double-trench silicon carbide (SiC) power metal-oxide-semiconductor field-effect transistors (MOSFETs) under repetitive avalanche stress are investigated in this paper. The injection of hot holes into the bottom oxide of the gate trench during avalanche process is demonstrated to be the dominant degradation mechanism, while the channel is rarely influenced by the stress. The injected holes attract extra electrons in the SiC layer along the SiC/SiO2 interface, decreasing the ON-state drain–source resistance ( ${R}_{{dson}}$ ). Due to this reason, the threshold voltage ( ${V}_{{th}}$ ) of the device also reduces slightly. Moreover, other than static electrical parameters, dynamic characteristics including the gate–drain capacitance ( ${C}_{{gd}}$ ) and the switching characteristics of the device also degrade. After being stressed by repetitive avalanche stress, the depletion region beneath the bottom of the gate trench gets thinner, leading to the increase in ${C}_{{gd}}$ , which further influences the switching behaviors. The turn- ON and turn- OFF switching times of the device are calculated. It illustrates that the repetitive avalanche stress results in an obvious delay in the turn- OFF procedure, but hardly influences the turn- ON behaviors of the double-trench SiC MOSFET.

Characterization of the Stability of Current Gain and Avalanche-Mode Operation of 4H-SiC BJTs

The stability of the electrical characteristics of SiC n-p-n bipolar junction transistors (BJTs) is investigated under long-term avalanche-mode, dc, and pulsed-current operation. There is absolutely no change in the blocking I-V characteristics after a 934-h repetitive avalanche stress test. Long-term operation of the base-emitter diode (open-collector mode) alone does not result in any degradation of the ON-state voltage drop V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">F</sub> or current gain β. Long-term operation in common-emitter mode results in negligible V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">F</sub> or β degradation, if the base plate is maintained at 25°C. A greater degradation of β results upon increasing the base-plate temperature. The same total electrical charge, if passed through the BJT as a pulsed current, instead of a dc current, results in smaller β reduction. It is also shown that the β degradation can be reversed by annealing at ≥200°C, suggesting the possibility of degradation-free operation of SiC BJTs, when operating in pulsed current mode at ≥200°C temperatures.

Stability of Electrical Characteristics of SiC “Super” Junction Transistors under Long-Term DC and Pulsed Operation at various Temperatures

ABSTRACTThe reliability of the electrical characteristics of SiC “Super” Junction Transistors (SJTs) is investigated under long-term avalanche-mode, DC and pulsed-current operation. There is absolutely no change in the blocking I-V characteristics after a 934 hour repetitive avalanche stress test. Long-term operation of the Gate-Source diode (open-Drain mode) alone does not result in any degradation of the on-state voltage drop (VF) or current gain (β). Long-term operation in common-Source mode results in negligible VF or β degradation, if the base-plate is maintained at 25 °C. A greater degradation of β results with increasing base-plate temperature. The same total electrical charge, if passed through the SJT as a pulsed current instead of a DC current results in a smaller β reduction. It is also shown that this β degradation can be reversed by annealing at ≥ 200 °C, suggesting the possibility of degradation-free operation of SiC SJTs, when operating in pulsed current mode at ≥ 200 °C temperatures.

SILICON CARBIDE “SUPER” JUNCTION TRANSISTORS OPERATING AT 500 °C

1200 V/ 3 mm2 active-area SiC “Super” Junction Transistors (SJTs) display current gains as high as 88 and majority carrier operation up to 250 °C. The SJT operation shifts from purely unipolar to bipolar-mode at temperatures ≥ 300 °C. The leakage currents at a blocking voltage of 1200 V remain below 100 μA, even at 325 °C. Temperature-independent turn-on and turn-off times &amp;lt; 15 ns are measured up to 250 °C. A short-circuit withstand time of 22 μs at VDS=800 V, and a single-pulse avalanche energy of 20.4 mJ are measured. No degradation of the blocking I-V characteristics was observed after a 934 hour repetitive avalanche stress test.

Effects of X-ray lithography and irradiation damage on Si-devices

Studies of radiation effects and comparison of degradation characteristics of Si-devices are presented. X-ray and optically patterned insulated gate field effect transistors (IGFETs), subjected to different types and levels of electrical stress, are included. The degradation in device transconductance due to drain avalanche stress (DAHCS) is much more deteriorating than channel hot carrier stress (CHCS). While the former depends on drain voltage, the latter depends on gate voltage. The performance degradation is maximum for the value of gate voltage which produces maximum substrate current. An empirical relationship between the transconductance degradation and stress time as a function of the effective channel length, for the biasing conditions producing maximum stress, is found. Transconductance degradation of X-ray patterned IGFETs is almost the same as optically patterned ones. Extrinsic irradiation to three different radiation doses of 3, 6 and 8 Mrads (SiO 2) shows a transconductance rebound behavior in Si-devices. The mechanisms behind the variations are explained on the basis of generation of fixed oxide charges and balancing of interface traps.