Automatic Hardware Research Articles

Hardware automatic test scheme and intelligent analyze application based on machine learning model

Abstract Hardware testing has always been the core of hardware development, and improving the performance and efficiency of hardware testing is very important for hardware development. Because hardware quality management is insufficient, many large hardware tools were developed using manual workshop technology in the past and could hardly be maintained. This can lead to the cancellation of the project, causing major personnel and property losses. Improving hardware quality and ensuring security are very complex problems. Hardware testing is usually conducted through manual and automatic testing, and the limitations of manual testing are increasingly obvious. So hardware automatic testing technology has attracted people’s attention in recent years. It has become an important research direction in the field hardware testing and can overcome many problems of traditional testing methods. Strict test rules, based on standards and scores, provide a fully automated test process. With the continuous improvement of network technology, the functions and scope of hardware are constantly enriched and expanded. With the acceleration of hardware updates and development, this has brought a heavy burden to the previous hardware testing work. The purpose of this article was to study the application of machine learning technology in the field of hardware automatic testing and provide an appropriate theoretical basis for optimizing testing methods. This article introduced the research methods of hardware automatic testing technology, introduced three automatic testing framework models, and summarized the application of machine learning in hardware testing. It included hardware security and reliability analysis, hardware defect prediction, and source-based research. Then, this article studied the defect prediction model and machine learning algorithm and constructed a hardware defect prediction model based on machine learning based on the theory. First, the data were preprocessed, and then, the Stacking method was used to build a comprehensive prediction model, and four prediction results evaluation indicators were established. In the experiment part, the defect prediction results of the hardware automatic test model were studied. The results showed that the hardware defect prediction model based on machine learning had higher accuracy, recall rate, F_measure and area under curve. Compared with other models, the average accuracy of the hardware defect prediction model in this article was 0.092 higher, which was more suitable for automatic hardware testing and analysis.

HardGBM: A Framework for Accurate and Hardware-Efficient Gradient Boosting Machines

Gradient boosting machine (GBM) is a powerful and widely used type of ensemble machine learning methods, among which the most famous one is XGBoost. However, the cost of running large GBMs on hardware could become prohibitive given stringent resources. Ensemble reduction on boosting ensemble is intrinsically hard because member models are constructed in a sequential order, where the training targets for latter ones depend on the performance of the former ones. In this work, a GBM reduction framework is proposed for the first time to tackle the problem. For the first time, the framework supports automatic hardware implementation of regression tree ensembles. Experiments on 24 datasets from various applications demonstrate that our method reduces overall area utilization by 81.60% (80.64%) and power consumption by 21.15% (19.06%), while exceeding or successfully maintaining the performance level comparing with the original XGBoost (LightGBM) ensembles. In comparative experiments, to attain approximately the same accuracy level as our framework or XGBoost, deep learning-based solutions require >52.7× footprints, 6.0× power consumption, and 1.4× training time. Equipped with tunable parameters, the framework is expected to seek a Pareto optimal front considering hardware resource limitation, accuracy and stability, and computation (training) efficiency.

Fuzzy Hardware Tool: An Adaptable Tool to Facilitate the Implementation of Fuzzy Inference Systems in Hardware

A Fuzzy Inference System (FIS) is a system that represents human reasoning based on fuzzy if-then rules to extract valid results from imprecise or uncertain information. These systems have been applied to various engineering fields, such as control and image recognition, and have encouraged the search for development tools that provide facilities for the design, simulation, and implementation of FISs. Most of the available software tools for the design of FISs have been developed by the scientific community, and very few are commercial tools. According to the state of the technology, the fuzzy systems implemented in hardware have shown higher performance than software implementations. For this reason, different strategies for automatic hardware synthesis of FISs have been proposed in the literature. The available tools for FIS implementation, including MATLAB, Simulink, and Xfuzzy environment, require advanced hardware knowledge, and it is necessary to synthesize and implement the program on FPGA each time a change is made to the code. This paper presents a novel approach for the implementation of fuzzy systems on hardware devices that enables the direct implementation of FISs through a graphical user interface. The VHDL code is pre-synthesized and integrated with the interface, allowing users to experiment with different input parameters, such as membership functions and fuzzy rules, without resynthesizing the code on an FPGA. To verify the effectiveness of the proposed approach, experiments were conducted on two similar System-on-Chip (SoC) devices, VEEK-MT and VEEK-MT2. The results showed that the proposed solution represents a significant advancement in the study of fuzzy systems on hardware devices, providing a flexible and user-friendly approach to their design and implementation.

Ultrasonic Blind Walking Stick

An elegant on foot Stick which is an Electronic move towards to Assist Visually disable people. Their machine is a Node Mcu based automatic hardware that be able to assist a sightless to detect obstacle in face of him/her punctually. This hardware consists of lump Mcu Esp-32 pin with ultrasonic antenna for obstruction discovery. The straightforwardness of the future intends makes it simple to use by one person and at the similar occasion the price of developed such firewood is reserved low. The control consumption of the future attach is low and know how to be run easily. It is also awfully low-priced compare to the straight ones. Barrier and crack can be strong-minded easily by antenna reading. Also, it can be code-protected so that its safekeeping cannot be override excluding by the client or merchant. The planned structure used four Ultrasonic detectors which are for purpose uncovering, gentleman whole recognition; sentence the vanished stick by means of Bluetooth. When the self coupled to the Bluetooth then it harmonizing and gives the jumpy on fasten by click the button. Thus, being can find that mislaid fuse.

Features of the Application of Instrumental Methods for Lumbosacral Muscle Groups Functional State Assessing

The use of instrumental diagnosis methods is a way to form an individual strategy of rehabilitation treatment and effectiveness monitoring. However, there is a lack of methods for objective assessment of the muscle groups’ functional state in both patients with dorsopathy and healthy individuals, as well as incorrect use of existing diagnostic tools due to the lack of the regulatory framework. The subjects had no complaints on low back pain, and there was no history of pain episodes associated with spinal pathology. All the volunteers were comparable in height and weight before being included in the study. The study was conducted in accordance with the terms of the Helsinki Declaration, all subjects signed an informed consent before the start of diagnostic activities. Aim. To determine the normative values of the strength of the flexor muscle group (FM) and extensor muscles (EM) of the lumbosacral spine and to establish the ratio of the obtained results to the automatic hardware norm. Material and methods. The present clinical study included 22 healthy volunteers aged 23 to 61 years (the average age was 38.4±12.8 years), including 14 women (63.6%) and 8 men (36.4%). Results and discussion. The results obtained demonstrate that the real normative indicators for MS and MR in healthy individuals can vary in the range from the hardware norm value calculated automatically by the device to a value of 20% lower. Exceeding this parameter is not a pathological deviation. When assessing the muscle strength, a decrease in this indicator is of physiological and clinical significance, since it reflects the dysfunction of this area and is a predictor of the pain syndrome chronicity. Conclusion. The standard values findings allow us to assess correctly the initial clinical condition and use this instrumental method with biofeedback for patients with degenerative spinal lesion and non-specific pain in the lumbosacral region and patients who have undergone spinal surgery to develop individual rehabilitation programs. As a further prospect for the use of diagnostic systems with biofeedback, it is suggested that the examination plan should include the determination of the ratio of the FM strength to the EM strength, as well as the strength of the muscles involved in the lateral slopes of the trunk.

APMT: an automatic hardware counter-based performance modeling tool for HPC applications

The ever-growing complexity of HPC applications and the computer architectures cost more efforts than ever to learn application behaviors. In this paper, we propose the APMT, an Automatic Performance Modeling Tool, to understand and predict performance efficiently in the regimes of interest to developers and performance analysts while outperforming many traditional techniques. In APMT, we use hardware counter-assisted profiling to identify the key kernels and non-scalable kernels and build each kernel model according to our performance modeling framework. Meantime, we also provide an optional refinement modeling framework to further understand the key performance metric, cycles-per-instruction (CPI). Our evaluations show that by only performing a few small-scale profiling, APMT is able to keep the average error rate around 15% with average performance overheads of 3% in different scenarios, including NAS parallel benchmarks, dynamical core of atmosphere model of the Community Earth System Model (CESM), and the ice component of CESM on commodity clusters. APMT improve the model prediction accuracies by 25–52% in strong scaling tests comparing to the well-known analytical model and the empirical model.

Automatic FPGA-based Hardware Accelerator Design: A Case Study with Image Processing Applications

We present a case study of automatic FPGA-based hardware accelerator design using our proposed framework with the image processing domain. With the framework, the ultimate systems are optimized in both performance and energy consumption. Moreover, using the framework, designers can implement FPGA platforms without manually describing any hardware cores or the interconnect. The systems offer accelerations in execution time compared to traditional general purpose processors and accelerator systems designed manually. We use two applications in the image processing domain as experiments to report our work. Those are Canny edge detection and jpeg converter. The experiments are conducted in both embedded and high-performance computing platforms. Results show that we achieve overall speed-ups by up to 3.15´ and 2.87´ when compared to baseline systems in embedded and high-performance platforms, respectively. Our systems consume less energy than other FPGA-based systems by up to 66.5%.

Improving Performance and Energy Consumption in Embedded Systems via Binary Acceleration: A Survey

The breakdown of Dennard scaling has resulted in a decade-long stall of the maximum operating clock frequencies of processors. To mitigate this issue, computing shifted to multi-core devices. This introduced the need for programming flows and tools that facilitate the expression of workload parallelism at high abstraction levels. However, not all workloads are easily parallelizable, and the minor improvements to processor cores have not significantly increased single-threaded performance. Simultaneously, Instruction Level Parallelism in applications is considerably underexplored. This article reviews notable approaches that focus on exploiting this potential parallelism via automatic generation of specialized hardware from binary code. Although research on this topic spans over more than 20 years, automatic acceleration of software via translation to hardware has gained new importance with the recent trend toward reconfigurable heterogeneous platforms. We characterize this kind of binary acceleration approach and the accelerator architectures on which it relies. We summarize notable state-of-the-art approaches individually and present a taxonomy and comparison. Performance gains from 2.6× to 5.6× are reported, mostly considering bare-metal embedded applications, along with power consumption reductions between 1.3× and 3.9×. We believe the methodologies and results achievable by automatic hardware generation approaches are promising in the context of emergent reconfigurable devices.

Microcontroller Implementation for Automatic Smart Bell

This study aims to design automatic school bell hardware based on the ATmega32 microcontroller, design automatic school bell software based on the ATmega32 microcontroller using Basic programming language, and test the performance of the automatic school bell based on the ATmega32 microcontroller. This automatic school bell uses a minimum system of ATmega32 microcontrollers which equipped with data input from the push button, LCD to display character output, ISD2560 to output sound, and a timer taken from DS1307 RTC. This research is a Research or Development (R & D) research. This research is carried out through two stages of design. The first stage is the stage of hardware design. The second stage is the stage of software design. Programs are made using the Basic programming language using the Bascom-AVR application. The results of the product were tested using the black box method with two stages. In the first stage, software testing uses a series of simulations on the Proteus 7 Professional application. The second stage, testing hardware.

Optoelectronic complex for express laser diodes lifetime prediction

This paper presents the optoelectronic complex, which provides both preparations for carrying out an express lifetime prediction of edge emitted strip single-mode laser diodes. It is shown that for this purpose the complex should consist of four operational units: an input control unit; a spectral radiation characteristics measurement unit; a laser lifetime forecasting unit and automatic processing hardware unit. The use of this complex makes it possible to predict the lifetime of a laser diode according to their spectral characteristics at the initial stage of its operation.

Automatic Feature Selection of Hardware Layout: A Step toward Robust Hardware Trojan Detection

Recently, the problem of hardware Trojan detection has gained a tangible significance in academia and industry. That problem, by its nature, is complex, time consuming and error prone due to design and fabrication outsourcing of hardware circuits to external untrusted foundries. Researchers have proposed different approaches, either destructive or non-destructive, to overcome that problem. The destructive approach depends on reverse engineering via decapsulation, delayering and layout identification. This paper presents a first trial of a new approach that can afford an automatic and robust solution for the step of layout identification. The proposed technique takes the underlying digital circuit as input, and automatically determines its basic features using Haar feature extractor. Based on that features, a decision tree is trained to act as a weak classifier, which is later boosted, by making use of AdaBoost learning algorithm, to produce a strong classifier in a chain of cascaded classifiers. Accordingly, a classification model is built up to provide an automatic hardware Trojan location and detection tool. To evaluate the proposed model, ISCAS89 benchmark dataset was used for training and testing. The hardware dataset has been altered deliberately to show different Trojan examples ---namely, Trojan insertion, Trojan deletion and Trojan parametric- inside hardware circuits. By investigating the underlying experimental results, the capabilities of the proposed model are evaluated, and the evaluation shows that the approach can detect different hardware Trojan types in different circuit layouts, with high accuracy rate. The proposed approach is not only automatic, but also robust and promising.

Efficient Hardware Design of Iterative Stencil Loops

A large number of algorithms for multidimensional signals processing and scientific computation come in the form of iterative stencil loops (ISLs), whose data dependencies span across multiple iterations. Because of their complex inner structure, automatic hardware acceleration of such algorithms is traditionally considered as a difficult task. In this paper, we introduce an automatic design flow that identifies, in a wide family of bidimensional data processing algorithms, subportions that exhibit a kind of parallelism close to that of ISLs; these are mapped onto a space of highly optimized ad-hoc architectures, which is efficiently explored to identify the best implementations with respect to both area and throughput. Experimental results show that the proposed methodology generates circuits whose performance is comparable to that of manually optimized solutions, and orders of magnitude higher than those generated by commercial high-level synthesis tools.

Pedagogical conditions of vocational training fundamentalization of future computer network specialists

The article is devoted to substantiation of pedagogical conditions of vocational training fundamentalization of future computer network specialists. Due to the dynamic development of the theory of automatic control, automation hardware and modern learning process requires constant updating of training programs, logistical support of the learning process and improve the content of training of future computer system specialists. The importance of the fundamentalization process of continuous vocational training

Main-Memory Hash Joins on Modern Processor Architectures

Existing main-memory hash join algorithms for multi-core can be classified into two camps. Hardware-oblivious hash join variants do not depend on hardware-specific parameters. Rather, they consider qualitative characteristics of modern hardware and are expected to achieve good performance on any technologically similar platform. The assumption behind these algorithms is that hardware is now good enough at hiding its own limitations—through automatic hardware prefetching, out-of-order execution, or simultaneous multi-threading (SMT)—to make hardware-oblivious algorithms competitive without the overhead of carefully tuning to the underlying hardware. Hardware-conscious implementations, such as (parallel) radix join , aim to maximally exploit a given architecture by tuning the algorithm parameters (e.g., hash table sizes) to the particular features of the architecture. The assumption here is that explicit parameter tuning yields enough performance advantages to warrant the effort required. This paper compares the two approaches under a wide range of workloads (relative table sizes, tuple sizes, effects of sorted data, etc.) and configuration parameters (VM page sizes, number of threads, number of cores, SMT, SIMD, prefetching, etc.). The results show that hardware-conscious algorithms generally outperform hardware-oblivious ones. However, on specific workloads and special architectures with aggressive simultaneous multi-threading, hardware-oblivious algorithms are competitive. The main conclusion of the paper is that, in existing multi-core architectures, it is still important to carefully tailor algorithms to the underlying hardware to get the necessary performance. But processor developments may require to revisit this conclusion in the future.

Study on the Application of PLC in Coal Sorting System

In order to reduce the coal production cost and labor, PLC is designed as the core technology of coal sorting, and a lot of sensor to distinguish colors and properties of coal join in this system. The sorting effect is very good. PLC coal sorting system has stable, safe, simple, reliable and other advantages, can improve the efficiency of coal production, and has brought the huge profit space for the enterprise. This paper first analyzes the PLC sorting system requirements and functions, and then discusses the control principle of PLC automatic sorting, the total design scheme of automatic sorting and related hardware design analysis, researches and hopes to help PLC coal sorting technology.

A review of bioinspired computer‐aided design tools for hardware design

SUMMARYDuring the tools have been also influenced by this evolutionary fashion. In this paper, we give a broader view of the application of techniques inspired by nature to hardware design and parallel architectures problem solving. Our aim is to furnish an overview of the various bioinspired techniques based tools that have been used so far to solve the problems of automatic hardware design. We can claim that a lot of the approaches found in the literature suffer from a lack of interdisciplinary interaction among researchers of both evolutionary computation and hardware design fields. In addition, we have also detected that some multi‐objective problems do not use the appropriate algorithms. Copyright © 2012 John Wiley & Sons, Ltd.

Special issue on parallel architectures and bioinspired algorithm: guest editors message

This special issue includes the extended version of selected papers presented at the fourth Parallel Architectures and Bioinspired Algorithms Workshop held in Galveston Island (TX, USA) on October 14, 2011 in conjunction with Parallel Architectures and Compilation Techniques (PACT). This workshop follows the success of the three previous workshops held in conjunction with PACT 2008 in Toronto, Canada [1], PACT 2009 in Raleigh, USA [2], and PACT 2010 in Vienna [3], Austria and the two previous Workshops on Parallel Bioinspired Algorithms [4] held in Oslo, 2005, (together with IEEE International Conference on Parallel Processing (ICPP)) [5] and London, 2007 (together with Association for Computing Machinery (ACM) Genetic and Evolutionary Computation Conference (Gecco) 2007) [6]. These series of workshops has shown that knowledge fields such as parallel computer architectures and Parallel and Distributed Computing and Bioinspired Algorithms, which could seem quite different in a first approach, are able to find transversal elements that enrich them. Bioinspired Algorithms comprise a set of heuristics that can help to optimize a wide range of problems, including many tasks faced by parallel architectures designers, such as balancing computer load, fault-tolerance and dependability, thermal-aware design, and NoC design. In addition, Bioinspired Algorithms may help in finding solutions related to compilation and resource sharing issues, which are interesting problems for parallel architectures. Parallel architecture designers may also propose infrastructures that allow the improvement of computing performance of Bioinspired Algorithms, which usually face real-world problems that manage huge amounts of data. Alternatives to the classical sequential solution are needed by this community. Therefore, topics such as P2P, cluster and grid computing, cloud computing, and Graphics Processing Unit (GPUs) implementation of Bioinspired Algorithms are very interesting to this field. We have therefore considered this opportunity to give a broader view on the application of nature inspired computing techniques to hardware design and parallel architectures problem solving. We have also considered the interest of including an overview of the available bioinspired techniques based tools that have been used so far to solve problems related to automatic hardware design. We thus invited Professors Oscar Garnica and Juan Lanchares to work with us with this aim. Therefore, this special issue includes the paper entitled A review of bioinspired CAD tools for parallel architectures and hardware design [7] together with four papers carefully selected for

Autofocus Design for Testing System of Small Arms Sights

In order to improve the test accuracy of light weapons sights optical performance parameters, designed a set of photoelectric automatic focusing system which based on image processing, and made a detailed introduction of the automatic focusing system software and hardware systems design. Experiments have repeatedly established that this auto-focusing system has stable performance and high precision. The precision of the optical sighting performance parameter testing of small weapons are improved greatly. So this system has high practice value.

SU-E-T-246: Practical Quality Assurance for Image-Guided Robotic Brachytherapy System

Purpose: To establish device‐specific daily quality assurance procedure for image‐guidedbrachytherapyroboticsystem. To recommend sufficient tests and tolerance levels which would be acceptable for readily identifying and localizing possible deviations from normal system functionalities.Methods: Image‐guidedbrachytherapyrobot consists of three mutually paired functional modules: robotic hardware with sensors, control and planning software, and image acquisition subsystem. Therefore, daily QA procedure should ensure mechanical and software functionality, appropriate systemcalibration, clinical image acquisition and quality, and verification of system accuracy. Recommended daily QA tests can be summarized into three basic groups: mechanical screening, roboticsystem functionality, and overall calibration test. Mechanical screening test includes visual check of connectors, controllers, wires, sensors and motors, connectivity test for controllers, motors, encoders and moving parts, sensors readings and sensitivity, and emergency subsystem functionality test, such as emergency button or manual takeover check. Roboticsystem functionality test incorporates automatic hardware detection and mobility of moving parts, such as probe stage, gantry and insertion mechanism. It also includes image upload and acquisition test. Purpose of overall calibration test is to simulate seed placement into predefined position using captured image sets. Specially designed tool with three markers should be attached to the robot. Tip of each marker has different coordinates. System should drive needle, touch and stop next to each marker. Difference between needle and marker tip should be recorded.Results: First and the second groups of tests are designed to have pass/fail outcome. Tolerance values for third test are ±0.5 mm. Daily QA procedure was developed to minimize test time which is 20min on average Conclusions: Routine daily QA procedure plays crucial role in ensuring overall safety of brachytherapyroboticsystem for clinical implementation. Recommended procedures are intended to support and supplement development of comprehensive brachytherapyrobotic QA program. Acknowledgement: Supported by NCI‐R01‐CA091763.

Automatic Hardware Reconfiguration for Current Reduction at Low Power in RFIC PAs

This paper presents a novel hardware reconfiguration technique implemented in a dual integrated-circuit (IC) GaAs HBT power amplifier (PA) design and demonstrates reduced current and improved efficiency at low power. The method automatically reconfigures the hardware of an RF IC PA over a given power transmission. Hardware interfacing and synchronization from outside the PA is minimized, and automatic gain compensation upon hardware reconfiguration is achieved with minimal temperature-dependant calibration. The challenge of integrating such complex on-chip hardware functions in a GaAs HBT technology was circumvented by the introduction of a gating concept used in conjunction with envelope feedback, and careful tradeoffs between circuit complexity and performance. Designs that suit the on-chip integration of the technique in GaAs HBT or Si bipolar junction transistor technologies are described. Experimental data are reported to support the proposed method.