Automatic Hardware Reconfiguration for Current Reduction at Low Power in RFIC PAs

Abstract

This paper presents a novel hardware reconfiguration technique implemented in a dual integrated-circuit (IC) GaAs HBT power amplifier (PA) design and demonstrates reduced current and improved efficiency at low power. The method automatically reconfigures the hardware of an RF IC PA over a given power transmission. Hardware interfacing and synchronization from outside the PA is minimized, and automatic gain compensation upon hardware reconfiguration is achieved with minimal temperature-dependant calibration. The challenge of integrating such complex on-chip hardware functions in a GaAs HBT technology was circumvented by the introduction of a gating concept used in conjunction with envelope feedback, and careful tradeoffs between circuit complexity and performance. Designs that suit the on-chip integration of the technique in GaAs HBT or Si bipolar junction transistor technologies are described. Experimental data are reported to support the proposed method.